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Static induction transistor

About: Static induction transistor is a research topic. Over the lifetime, 8155 publications have been published within this topic receiving 107058 citations. The topic is also known as: SIT.


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Patent
12 Apr 1976
TL;DR: In this paper, a semiconductor structure for, and method of manufacture of, a linear integrated circuit provides the equivalent of a base function in a transistor, wherein the base function has a dual charge density, with the latter being relatively low in the lower active area of the base between PN junctions for high gain and high breakdown voltage, but high along the upper surface to prevent an unwanted inversion layer from occurring.
Abstract: A semiconductor structure for, and method of manufacture of, a linear integrated circuit provides the equivalent of a base function in a transistor, wherein the base function has a dual charge density, with the latter being relatively low in the lower active area of the base between PN junctions for high gain and high breakdown voltage, but high along the upper surface to prevent an unwanted inversion layer from occurring.

30 citations

Patent
19 Sep 2002
TL;DR: A pixel circuit of an organic EL display includes an EL device, first and second switching devices, a driving thin film transistor, and a capacitor as mentioned in this paper, and the first switching device switches data voltages applied to data lines in response to the selection signal applied to a scan line.
Abstract: A pixel circuit of an organic EL display includes an EL device, first and second switching devices, a driving thin film transistor, and a capacitor. The first switching device switches data voltages applied to data lines in response to the selection signal applied to a scan line and the second switching device connects gate and drain of the driving thin film transistor in response to a compensation signal applied to a compensation line. The driving thin film transistor supplies electric current to the organic EL device in response to the data voltage inputted to a gate from the first switching device and the capacitor maintains the data voltage applied to the gate of the driving thin film transistor for a predetermined period. At this time, the characteristic deviation of the transistor is compensated by connecting the gate and the drain of the driving thin film transistor by applying the compensation signal to the compensation line before applying the data voltage, and then the data voltages are applied to the data lines after cutting off the compensation signal. In this manner, the characteristic deviation of the driving thin film transistors can be compensated.

30 citations

Patent
27 Feb 1996
TL;DR: In this paper, the respective source and drain of P type transistors 13 and 14 are serially connected between a power source and ground, positive logic or negative logic is impressed from an input (IN) side to the gate of the P type transistor 13 and logic for which input is inverted is inverted from an inverted input with upper bar (IN with upper bars), to the ground.
Abstract: PROBLEM TO BE SOLVED: To make a leakage current small, to perform high integration, to perform formation with less processes and to make an output level be appropriate by performing constitution by the transistors of the same conductive type. SOLUTION: The respective source and drain of P type transistors 13 and 14 are serially connected between a power source and ground, positive logic or negative logic is impressed from an input (IN) side to the gate of the P type transistor 13 and logic for which input (IN) is inverted is impressed from an inverted input (IN with upper bar) side to the gate of the P type transistor 14. Then, the source and drain of the P type transistor 12 are interposed between the inverted input (IN with upper bar) to the gate of the P type transistor 14 and a capacitor 15 whose one end is connected between the P type transistor 12 and the gate of the P type transistor 14 and other end is connected between the P type transistor 13 and connection point of the P type transistor 14 is interposed. Thus, a Low level outputted from an output terminal (OUT) is corrected so as to be a potential equivalent to a ground level.

30 citations

Proceedings ArticleDOI
23 Oct 2009
TL;DR: In this article, a new tunneling transistor structure is introduced that offers several advantages over prior designs, including substantially increased tunneling area and improved turn on/off swing by engineering doping profile to ensure tunneling initiates in high electric field region.
Abstract: —A new tunneling transistor structure is introduced that offers several advantages over prior designs. Notably, tunneling area is substantially increased. Turn on/off swing is improved by engineering doping profile to ensure tunneling initiates in high electric field region. TCAD simulations explore the critical design considerations. The concept of heterojunction tunneling is introduced as a means to achieve low effective band gap and low voltage operation for the design in consideration. I. I NTRODUCTION Increasing power consumption presents a major problem for future ICs. A transistor that can operate below 0.5 V supply is highly desirable. Maintaining large I on /I off ratio at such low V dd is a challenge for MOSFET given the 60 mV/decade subthreshold swing limit. This limit governs the turn off/on of any device based on flow of carriers over an energy barrier. Band-to-band tunneling (BTBT) is one process not subject to this limitation. Researchers have long explored the BTBT transistor [1-2]. However, all have relied on the same basic structure -- the gated PN diode. This conventional structure for an n-type FET is shown in Fig. 1. The location of tunneling is indicated by the arrow at the edge of the source region. The transistor “turns on” when the gate voltage exceeds the overlap voltage, V

30 citations

Patent
Akihiko Yoshizawa1
19 Apr 1994
TL;DR: In this paper, the second control voltage is set in a symmetrical relation to the first control voltage with respect to an intermediate potential between the power supply and the ground set as a reference.
Abstract: A VCO includes an oscillator and a controller for controlling the operation of the oscillator. The oscillator is formed by connecting odd number of stages of delay circuits in a ring form. The controller creates a second control voltage based on an input first control voltage. The second control voltage is set in a symmetrical relation to the first control voltage with respect to an intermediate potential between the power supply and the ground set as a reference. Each of the delay circuits includes an inverter, first and second current control circuits, and first and second current value setting circuits. The inverter includes a first transistor of first conductivity type and a second transistor of second conductivity type to receive and output a signal. The first current control circuit is connected between the first transistor and the ground, for controlling a current flowing in the first transistor when the first transistor is set in the conductive state according to the first control voltage. The first current value setting circuit sets the minimum value of the current flowing in the first transistor. The second current control circuit is connected between the second transistor and the power supply, for controlling a current flowing in the second transistor when the second transistor is set in the conductive state according to the second control voltage. The second current value setting circuit sets the minimum value of the current flowing in the second transistor.

30 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20234
20225
20211
20203
20196
20189