Static induction transistor

About: Static induction transistor is a research topic. Over the lifetime, 8155 publications have been published within this topic receiving 107058 citations. The topic is also known as: SIT.

Power FET short circuit protection

Abstract: A protection circuit for a semiconductor device such as a field effect transistor is disclosed having an oscillator which is connected to both the gate turn on circuitry and to the drain-source circuit of the field effect transistor for sensing the voltage of the drain-source circuit and for turning off cyclically the field effect transistor upon the simultaneous occurrence of a gate turn on signal to the gate of the transistor and high drain-source voltage.

Replacement metal gate transistor with controlled threshold voltage

Abstract: A method and structure for a semiconductor device includes a semiconductor substrate and an N-channel transistor and a P-channel transistor provided on the semiconductor substrate. Each of the N-channel transistor and the P-channel transistor has a gate dielectric film on the semiconductor substrate, and a gate electrode is formed on the gate dielectric. The gate electrode comprises a metal conductive layer. The oxygen concentration in the metal conductive layer for the N-channel transistor is different from that for the P-channel transistor.

An integrated device with a bipolar transistor and a MOSFET transistor in an emitter switching configuration

Abstract: A device integrated on a chip of a semiconductor material is disclosed which comprises an NPN bipolar transistor (T2) and an N-channel MOSFET transistor (T3) in an emitter switching configuration, both being vertical conduction types. The bipolar transistor (T2) has its base (13) and emitter (14) regions buried; the MOSFET transistor (T3) is formed with an N region (16) bounded by the base (13) and the emitter (14) regions and isolated by a deep base contact and isolation region (15). To improve the device performance, especially at large currents, an N+ region (17) is provided which extends from the front of the chip inwards of the isolated region (16) and around the MOSFET transistor (T3). In one embodiment of the invention, a MOSFET drive transistor (T1) is integrated which has its drain terminal in common with the collector (C) of the bipolar transistor (T2), its source terminal connected to the base of the bipolar transistor (T2), and its gate electrode connected to the gate electrode (G) of the MOSFET transistor (T3) in the emitter switching configuration.

Exploring Area and Delay Tradeoffs in FPGAs With Architecture and Automated Transistor Design

Abstract: Field-programmable gate arrays (FPGAs) are used in a variety of markets that have differing cost, performance and power consumption requirements. While it would be ideal to serve all these markets with a single FPGA family, the diversity in the needs of these markets means that generally more than one family is appropriate. Consequently, FPGA vendors have moved to provide a diverse set of families that sit at different points in the area-speed-power design space. This paper aims to understand the circuit and architectural design attributes of FPGAs that enable tradeoffs between area and speed, and to determine the magnitude of the possible tradeoffs. This will be useful for architects seeking to determine the number of device families in a suite of offerings, as well as the changes to make between families. We explore a broad range of architectures and circuit designs and developed a transistor sizing tool that automatically optimizes each design. In this paper, we describe this tool and demonstrate that it achieves results that are comparable to past work but with vastly less effort. We then use the designs produced by the tool to explore the range of tradeoffs possible. We find that through architecture and transistor sizing changes it is possible to usefully vary the area of an FPGA by a factor of 2.0 and the performance of an FPGA by a factor of 2.1. We also observe that the range of area and delay tradeoffs possible by varying only the transistor sizing of a single architecture is larger than the ranges observed in past architectural experiments. In addition to transistor size, we note that LUT size is one of the most useful parameters for trading off area and delay.

Non-volatile programmable memory cell and array for programmable logic array

Abstract: A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.