Static induction transistor

About: Static induction transistor is a research topic. Over the lifetime, 8155 publications have been published within this topic receiving 107058 citations. The topic is also known as: SIT.

Clamped inductive switching of LDMOST for smart power IC's

Abstract: This paper explores the energy capability of an integrated clamped lateral power MOS transistor. The energy capability is determined by switching the device on an inductive load. Experimental results show that the rating of the transistor in terms of energy has to be given along with the drain voltage applied during the transient regime. If the clamp voltage increases, the energy capability decreases. This is explained by the presence of a parasitic NPN transistor in the LDMOS transistor. A specific structure is designed in order to determine the energy capability that would correspond to a purely thermal failure mechanism.

Depletion and enhancement MOSFETs with electrically trimmable threshold voltages

Abstract: A switching device having an electrically trimmable threshold voltage comprises a control transistor having favorable programming and erasing characteristics and a sensing transistor suited for stability and high drain voltages. The control transistor includes a floating gate for storing a charge. The control transistor receives an input voltage to vary the charge. The sensing transistor, which has a threshold voltage, includes the floating gate, which is formed from a single, contiguous layer of polysilicon or from separate polysilicon layers connected by metallization, such that the floating gate is shared by the control transistor and the sensing transistor. The control transistor has a tunnel oxide layer between a semiconductor layer and the floating gate having a thickness that is conducive to injection or tunneling of electrons through the tunnel oxide layer. The sensing transistor has a gate oxide layer between the semiconductor layer and the floating gate having a thickness greater than the thickness of the tunnel oxide layer, such as to substantially inhibit injection or tunneling of electrons through the gate oxide layer. Applying the input voltage to the control transistor varies the charge on the floating gate and thereby changes the threshold voltage of the sensing transistor.

High output current in vertical polymer space-charge-limited transistor induced by self-assembled monolayer

Abstract: We present a promising solution-processed vertical transistor which exhibits high output current, high on/off current ratio, and low operation voltage. Numerous poly(3-hexylthiophene) vertical channels are embedded in vertical nanometer pores. Treating the sidewalls of pores by self-assemble monolayer with long alkyl chains enhances the pore-filling and inter-chain order of poly(3-hexylthiophene). The channel current is therefore greatly increased. A grid metal inside the porous template controls the channel potential profile to turn on and turn off the vertical transistor. Finally, the transistor delivers an output current density as 50–110 mA/cm2 at 2 V with an on/off current ratio larger than 10 000.

Low-power cmos flip-flop

Abstract: A flip-flop (10) includes a charge storage area (22) that stores a logic voltage indicating a logic state of the flip-flop (10), a first transistor (20a) having a source or drain connected to a clock generating circuit (40), a second transistor (20b) having a source or drain connected to the clock signal generating circuit (40), a clock signal generated by the clock signal generating circuit (40) that is ramped or sinusoidal, and a latching circuit (18) that latches a latch voltage value based on voltages at the first transistor (20a) and the second transistor (20b). The charge storage area (22) supplies a first voltage representing a state of the storage voltage to a gate of the first transistor (20a) and supplies a second voltage to a gate of the second transistor (20b).

Ion-sensitive field effect transistor and method for producing an ion-sensitive field effect transistor

Abstract: The invention relates to an ion-sensitive field effect transistor which comprises a substrate on which a source region (14) and a drain region (16) are configured. The ion-sensitive field effect transistor, above a channel region (30), has a gate with a sensitive layer (32), which gate comprises a metal oxide nitride mixture and/or a metal oxide nitride mixture compound.