Static induction transistor

About: Static induction transistor is a research topic. Over the lifetime, 8155 publications have been published within this topic receiving 107058 citations. The topic is also known as: SIT.

Organic electro-luminescence display device, driving method therefor, and pixel circuit therefor

Abstract: PROBLEM TO BE SOLVED: To realize high gradations compensating for deviation of a threshold voltage of a thin film transistor when driving an organic electro-luminescence element. SOLUTION: The pixel circuit comprises an organic electro-luminescence element OELD emitting light corresponding to an applied current quantity, a 1st switch S1 for switching a data voltage to be applied to the data line in response to a selection signal applied to a scanning line, a 1st transistor M1 for supplying a current to the organic electro-luminescence element correspondingly to the data voltage inputted to the gate through the 1st switch S1, a 2nd transistor M2 of which the gate is connected with the gate of the 1st transistor M1 for compensating for the deviation of the threshold voltage of this 1st transistor M1, and a capacitor C1 for holding the data voltage applied to the gate of the 1st transistor M1 for prescribed period. COPYRIGHT: (C)2002,JPO

Locos MOS device for ESD protection

Abstract: A MOS transistor having a multilevel gate oxide layer is provided for use in an ESD protection circuit. A thick gate oxide layer near the drain insures that the transistor has a relatively large drain to gate breakdown voltage. A thin gate oxide layer near the source permits the gate voltage to turn the transistor on and off with rapid switching speeds. The thick portion of the MOS transistor multilevel gate oxide layer is formed with a local oxidation of silicon (LOCOS) process, while the thin gate layer is formed in a separate step. An ESD protection circuit and method for fabricating the above-mentioned multilevel gate oxide layer MOS transistor are also provided.

Negative feedback CMOS differential amplifier operating in common mode

Abstract: In a CMOS amplifier having a differential input and differential output, the input stage includes two legs, each of which includes an input transistor. A common mode negative feedback stage includes a load connected to the high supply voltage, a first transistor connected between the load and a common terminal of the input transistors. The first transistor is biased to the desired common mode voltage. A second transistor is connected between the load and the low supply voltage, and has a gate connected to a voltage corresponding to the means voltage of the output stage. An additional transistor is disposed in parallel with each input transistor. Each additional transistor has its gate connected to the desired common mode voltage.

Semiconductor device design and process

Abstract: A method for fabricating a gate-source structure for a recessed-gate static induction transistor. Source impurities are implanted prior to forming the recessed gates. The recessed gates are formed by a first isotropic etching step and a second anisotropic etching step which results in a unique overhanging protective layer used to protect the walls of the grooves during implantation of gate impurities in the bottom of the grooves. Implantations are driven and activated to form gate and source regions, the protective layer is removed and metal deposited to form electrodes. The procedure minimizes the required number of masking steps and associated mask registration problems.

Method of making a high voltage implanted channel device for VLSI and ULSI processes

Abstract: A process for fabricating a high voltage CMOS transistor having a non-self aligned implanted channel which permits the operation of the device at high voltages. The non-self aligned implanted channel does not require alignment with the gate electrode of the CMOS device, but is accurately implanted early in the fabrication of the device through reliance on direct wafer stepper technology. As a result, the non-self aligned implanted channel does not require a high temperature drive, such that fabrication of the transistor is compatible with VLSI and ULSI processes, and the transistor can be up-integrated onto logic integrated circuits. Accuracy of the placement of the non-self aligned implanted channel provides for a shorter channel length, which enables the device to be highly area efficient while also increasing the current capability of the device. Furthermore, the transistor is characterized by a large field-induced avalanche breakdown voltage, enhanced by a thick gate oxide, a lightly doped drain, a field oxide region between the gate and the drain, and known field plating techniques.