Static induction transistor

About: Static induction transistor is a research topic. Over the lifetime, 8155 publications have been published within this topic receiving 107058 citations. The topic is also known as: SIT.

Inverter circuits using insulated gate field effect transistors

Abstract: An inverter circuit comprises a pair of N- and P-channel insulated gate field effect transistors coupled in series. One of the transistors is used as a load transistor and the other is used as a drive transistor. A diode is connected between the source and gate electrodes of the load transistor in order to hold the gate voltage of the load transistor. A resistor and a capacitor (having a larger capcitance than the gate capacitance of the load transistor) is connected to the gate electrode of the load transistor. In operation, a high voltage is applied to the source electrode of the load transistor. A low-voltage pulse, having a period shorter than the RC time constant of the resistor and capacitor, is applied through the capacitor to the gate electrode of the load transistor. The gate electrode of the drive transistor is supplied with a low-voltage input signal (having a phase which is the same as and not longer than the period of the pulse applied to the capacitor). An input pulse signal may be used as the low-voltage pulse which is applied to the capacitor.

Memory circuit, method of driving the same, nonvolatile storage device using the same, and liquid crystal display device

Abstract: The present invention provides a memory circuit including a memory element to which writing can be performed with a small current and a low voltage, i.e., low power consumption, and provides a non-volatile storage device that can easily reduce a chip size by using this memory circuit. A memory element 1 is a memory transistor having a transistor structure including a source electrode 14 , a drain electrode 15 , a gate electrode 11 , and, a source region, a drain region, and a channel region made of a metal oxide semiconductor layer 13 . The resistance property between the source and the drain shows a low resistance, and the memory transistor is changed to have an ohmic resistance property, regardless of a voltage application state of the gate electrode, by allowing a writing current with a density not less than a predetermined value to flow in the channel region to generate Joule heat. The memory circuit stores information between a state indicating the ohmic resistance property after the writing and a state indicating a current-voltage characteristic as a transistor depending upon the voltage application state to the gate electrode before the writing.

Integrated bipolar-CMOS circuit isolation for providing different backgate and substrate bias

Abstract: Disclosed is a bipolar-CMOS circuit which includes a NMOS transistor site (18) electrically isolated from a bipolar transistor site (16). The NMOS transistor site (18) includes a semiconductor region (24) isolated from a bipolar transistor well (26) by deep diffusion ring (32). A buried layer (13) forms a bottom of the deep diffusion isolation ring (32). A backgate voltage can be applied to the isolated semiconductor region (24) of the NMOS device, which bias may be different than that applied to the substrate (10). Optimum performance of the NMOS transistor is thus assured irrespective of the magnitude of operating voltage of the bipolar transistor.

Two-dimensional simulation of polymer field-effect transistor

Abstract: A two-dimensional simulation of intrinsic top-contact field-effect transistor is presented. The simulated structure is unique to organic transistors and hence is most relevant. By time resolving the operation of such a transistor, the mechanisms underlying its operation are resolved. The effect of this device configuration on the measured “intrinsic” material properties is also discussed and shown to explain previously reported features.

Methods and apparatus for testing isfet arrays

Abstract: The invention provides testing of a chemically-sensitive transistor device, such as an ISFET device, without exposing the device to liquids. In one embodiment, the invention performs a first test to calculate a resistance of the transistor. Based on the resistance, the invention performs a second test to transition the testing transistor among a plurality of modes. Based on corresponding measurements, a floating gate voltage is then calculated with little or no circuitry overhead. In another embodiment, the parasitic capacitance of at least either the source or drain is used to bias the floating gate of an ISFET. A driving voltage and biasing current are applied to exploit the parasitic capacitance to test the functionality of the transistor.