Static induction transistor

About: Static induction transistor is a research topic. Over the lifetime, 8155 publications have been published within this topic receiving 107058 citations. The topic is also known as: SIT.

Non-volatile semiconductor memory device capable of high speed programming/erasure

Abstract: To a column line to which a selected memory cell is connected, a write bias voltage is supplied through a selection gate transistor having different channel conductivity type than the memory cell transistor. Current drivability of the selection gate transistor is adapted to be larger than a leak current of the memory cell and to supply a current smaller than the channel current when a channel is formed in one aspect. When a verifying voltage is applied to the selected word line, a large channel current flows when a channel is formed, potential of a subbit line is changed accordingly, and programming is suppressed. In another aspect, the selection gate transistor serves as a constant current source to make the programming speed of the memory cells constant. Thus distribution of threshold values after programming can be made narrow.

Output driver circuit with body bias control for multiple power supply operation

Abstract: A push-pull output driver including two transistors in series, one transistor having its body bias controlled by logic circuitry commanded by the driver input. The driver has a pair of transistors in series, the transistor inputs being complementary to create a push-pull amplifier. A switching transistor is controlled by the inverse of the driver input signal and acts as a switch at the pull-up transistor well-tie. When the driver input is high, the switching transistor is off allowing the well-tie to the pull-up transistor to be connected to the driver output. When the input is low, the switching transistor turns on, switching the well-tie of the pull-up transistor to ground. By controlling the body bias of the pull-up transistor in this way, the switching speed of the output driver is significantly increased. When the output driver is in a disabled tri-state mode, the series transistors, and the switching transistor, are turned off. A first deselect transistor provides a high voltage at the drain of a load transistor to force it into cutoff. A select transistor is turned off to isolate the pull-up transistor well-tie from the output node, and a second deselect transistor is switched on to connect it to ground. This embodiment isolates the well-tie from the driver output while in tri-state to prevent latch-up initiated by multiple power supply operation.

Mos semiconductor circuit

Abstract: An MOS semiconductor circuit includes cascade connected logical circuits. The MOS semiconductor circuit further includes an MOS transistor circuit having at least one first MOS transistor coupled between a source voltage terminal and the output node of the individual logical circuits, and a second MOS transistor, which has the same conductivity type as the first MOS transistor and has its gate and drain short-circuited, with this gate being coupled to the gate of the first MOS transistor. The MOS semiconductor circuit also includes a current control circuit, which is coupled to the drain of the second MOS transistor for providing a predetermined current between the source and drain of the second MOS transistor.

Semiconductor device with CMOS-field-effect transistors having improved drain current characteristics

Abstract: The present invention provides a semiconductor device including n-channel field effect transistors and p-channel field effect transistors all of which have excellent drain current characteristics. In a semiconductor device including an n-channel field effect transistor 10 and a p-channel field effect transistor 30 , a stress control film 19 covering a gate electrode 15 of the n-channel field effect transistor 10 undergoes film stress mainly composed of tensile stress. A stress control film 39 covering a gate electrode 15 of the p-channel field effect transistor 30 undergoes film stress mainly caused by compression stress compared to the film 19 of the n-channel field effect transistor 10 . Accordingly, drain current is expected to be improved in both the n-channel field effect transistor and the p-channel field effect transistor. Consequently, the characteristics can be generally improved.

Current-voltage characteristics of a graphene-nanoribbon field-effect transistor

Abstract: We present an analytical device model for a field-effect transistor based on a heterostructure, which consists of an array of nanoribbons clad between the highly conducting substrate (the back-gate) and the top gate controlling the source-drain current. The equations of the model of a grapheme-nanoribbon field-effect transistor (GNR-FET) include the Poisson equation in the weak nonlocality approximation. By using this model, we find explicit analytical formulas for the spatial distributions of the electric potential along the channel and for the GNR-FET current-voltage characteristics (the dependences of the source-drain current on the drain voltages as well as on the back-gate and top-gate voltages) for different geometric parameters of the device. It is shown that the shortening of the top gate can result in a substantial modification of the GNR-FET current-voltage characteristics.