Static induction transistor

About: Static induction transistor is a research topic. Over the lifetime, 8155 publications have been published within this topic receiving 107058 citations. The topic is also known as: SIT.

Driving circuit of current driven element, driving method and image display device

Abstract: PROBLEM TO BE SOLVED: To reduce the adverse effect caused by a parasitic capacitor connected to a signal line of a driving circuit which drives current driven elements such as organic EL (light emitting) being assembled into an active matrix type image display device or the like and to drive the elements with an appropriate current even though a signal current is minute. SOLUTION: An auxiliary transistor 12 having an n times current driving capability of a driving transistor 7 is connected to the transistor 7 in parallel. In a portion (an acceleration interval) of a selection interval, a drain current is made to flow in the transistor 12 also and a signal current itself, which flows in a signal line 3, is made to (n+1) times. COPYRIGHT: (C)2003,JPO

Semiconductor memory circuit with depletion data transfer transistor

Abstract: A read only memory (ROM) circuit (10) includes a memory storage transistor (16) which is fabricated to have one of a plurality of threshold voltages corresponding to predetermined data states. The source and drain terminals of the memory transistor (16) are connected between a column node (18) and a bit line (20). A lightly depleted data transfer transistor (30) is connected between the bit line (20) and a data line (14). The column node (18), bit line (20) and data line (14) are precharged. A memory address is decoded to drive a selected word line (12) and a selected column decode line (32) to a high voltage state. A transistor (34) discharges the column node (18). Depending upon the state of the memory storage transistor (16) the bit line (20) is discharged or maintained precharged. The state of bit line (20) is transmitted through the data transfer transistor (30) to the data line (14). The data transfer transistor ( 30) can be fabricated as a relatively small device due to the large turn on voltage applied thereto because the transistor (30) is a depletion device. The smaller size of a plurality of the transistors (30) results in a substantial saving in space and reduces capacitive loading on the data line (14) thereby speeding up the discharge rate of the data line (14).

Shared gate CMOS transistor

Abstract: A stacked shared-gate CMOS transistor and method of fabrication are disclosed. An improved CMOS transistor is fabricated by the formation of a bulk transistor and an overlying isolated (SOI) transistor wherein each transistor is adjoined to a portion of a shared gate having the same conductivity type as the related transistor. The differential conductivity of the shared gate is obtained by the fabrication of a conductive diffusion-barrier layer intermediate to conductive layers. Improved switching performance is obtained as a result of higher current levels produced by the isolated transistor.

EEPROM using a merged source and control gate

Abstract: A single layer of polycrystalline silicon (poly-Si) is used in an EEPROM structure, which obviates the need to form a separate control gate and floating gate. The EEPROM utilizes three separate NMOS transistors: a write transistor, a read transistor, and a sense transistor. A thin tunnel oxide layer separates the N+ source region of the write transistor from an N doped poly-Si layer and capacitively couples the source region to the poly-Si layer. The poly-Si layer extends over the N+ source region of the sense transistor and is capacitively coupled to the source region of the sense transistor via a thin gate oxide insulating layer which is thicker than the oxide layer comprising the tunnel oxide layer. This poly-Si layer continues to extend over a channel region separating the N+ source and N+ drain regions of the sense transistor, the poly-Si layer being separated from the channel via the thin gate oxide insulating layer. The drain of the sense transistor also acts as the source of the read transistor. In the above structure, the poly-Si layer acts as the floating gate over the channel of the sense transistor. Since the poly-Si floating gate is both capacitively coupled to the source of the sense transistor and to the source of the write transistor, no separate control gate or control gate electrode is needed (the source of the sense transistor acts as the control gate). The structure, inter alia, enables a higher coupling ratio during erasing, thus allowing faster erase times by coupling a higher voltage onto the poly-Si floating gate.

Monolithic microwave integrated circuit apparatus

Abstract: A monolithic microwave semiconductor integrated circuit including a bias stabilizing circuit of a current mirror type formed of a bias control transistor formed of an enhancement mode compound semiconductor field effect transistor and a biased transistor formed of an enhancement mode compound semiconductor field effect transistor.