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Static induction transistor

About: Static induction transistor is a research topic. Over the lifetime, 8155 publications have been published within this topic receiving 107058 citations. The topic is also known as: SIT.


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Journal ArticleDOI
H. Mikoshiba1, T. Horiuchi1, K. Hamano1
TL;DR: In this article, practical limitations in channel lengths for n-channel MOSFETs under 5-V operation are discussed for conventional arsenic-drain, phosphorus-drone, double diffused drain (DDD), and lightly doped drain (LDD) structures.
Abstract: Practical limitations in channel lengths for n-channel MOSFET'S under 5-V operation are discussed for conventional arsenic-drain, phosphorus-drain, phosphorus-arsenic double diffused drain (DDD), and lightly doped drain (LDD) structures. Process parameter dependence of device characteristics and optimal process conditions are also evaluated for each drain structure. It is clarified that the minimum usable channel length is about 0.7-µm, which is realized by the DDD and LDD devices. In these devices, the hot-carrier-induced device degradation is no longer a major restriction on minimum channel length, but the short-channel effect and the parasitic bipolar breakdown are dominant restrictions. The phosphorus drain with a shallow junction formed by rapid thermal annealing can expand the arsenic drain limitation.

53 citations

Patent
08 Oct 1996
TL;DR: In this paper, a multi-level fabrication process is presented for producing active and passive devices on various levels of a semiconductor topography. And the interconnect employs a via routed directly between a well of an upper level transistor to a lower transistor so as to effect direct coupling between the wells of the respective transistors.
Abstract: A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect employs a via routed directly between a well of an upper level transistor to a well of a lower transistor so as to effect direct coupling between the wells of the respective transistors. Direct coupling in this fashion affords consistent operation of transistors arranged on separate elevation levels. The via is made as short as possible so as to reduce any discrepancy in substrate/well voltage potential. This ensures predictable operation of transistors fashioned on separate elevation levels.

53 citations

Patent
12 Sep 1995
TL;DR: An insulated-gate field effect transistor utilizes local threshold-adjust doping to control the voltage at which the transistor turns on as mentioned in this paper, which is suitable for use in analog and high-voltage digital portions of a VLSI circuit.
Abstract: An insulated-gate field-effect transistor utilizes local threshold-adjust doping to control the voltage at which the transistor turns on. The local threshold-adjust doping is present along part, but not all, of the lateral extent of the channel. In the transistor structure, a channel zone laterally separates a pair of source/drain zones. The channel zone is formed with a main channel portion and a more heavily doped threshold channel portion that contains the local threshold-adjust doping. Gate dielectric material vertically separates the channel zone from an overlying gate electrode. The transistor is a long device in that the gate electrode is longer, preferably at least 50% longer, than the gate electrode of a minimum-sized transistor whose gate length is approximately the minimum feature size. The long-gate transistor is suitable for use in analog and high-voltage digital portions of a VLSI circuit.

53 citations

Patent
28 Mar 2001
TL;DR: In this article, a method for reading a first non-volatile memory transistor in an array of nonvolatile memories transistors is presented. But the method is restricted to the case where the first NVM transistors have a drain coupled to a source of a neighbor NVM transistor.
Abstract: A method is provided for reading a first non-volatile memory transistor in an array of non-volatile memory transistors, wherein the first non-volatile memory transistor has a drain coupled to a source of a neighbor non-volatile memory transistor. The method includes the steps of (1) applying a read voltage to the gates of the first and neighbor non-volatile memory transistors, (2) applying a source voltage (Vs) to a source of the first non-volatile memory transistor, (3) applying a drain voltage (Vd) to the drain of the first non-volatile memory transistor and the source of the neighbor non-volatile memory transistor, and (4) applying a forcing voltage (Vf) to a drain of the neighbor non-volatile memory transistor. In a particular embodiment, the drain voltage Vd is equal to the forcing voltage Vf. Another embodiment includes the step of applying a second forcing voltage (Vfs) to the source of another neighbor non-volatile memory transistor.

53 citations

Patent
26 Feb 2002
TL;DR: In this article, a self-light emitting OLED is used to obtain a threshold voltage (Vth) by an amorphous silicon TFT, and a branching transistor is formed by making a portion of the electrodes of the transistor independent and detecting the threshold voltage.
Abstract: PROBLEM TO BE SOLVED: To appropriately obtain a threshold voltage (Vth) by an amorphous silicon TFT. SOLUTION: The driving circuit is provided with a self light emitting OLED 21, a driving transistor 22 which drives the OLED 21, a branching transistor 23 which is formed by making a portion of the electrodes of the transistor 22 independent and detects the threshold voltage (Vth) of the transistor 22, a compensation capacitor 28 into which the voltage (Vth) detected by the transistor 23 is written, a signal capacitor 27 into which signal voltages for the transistor 22 are written, a first transistor 24 which is located between a data line and the capacitor 27, a second transistor 25 which is located between the capacitors 27 and 28 and a third transistor 26 which is located between the gate electrode of the transistor 23 and other electrode. COPYRIGHT: (C)2003,JPO

53 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20234
20225
20211
20203
20196
20189