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Static induction transistor

About: Static induction transistor is a research topic. Over the lifetime, 8155 publications have been published within this topic receiving 107058 citations. The topic is also known as: SIT.


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Patent
13 Aug 1981
TL;DR: In this article, a laser programmable logic switch (22) includes a fusible link (28), an output node (26), and a transistor (24) which is fabricated to be in the off state.
Abstract: A laser programmable logic switch (22) includes a fusible link (28), an output node (26) and a transistor (24) which is fabricated to be in the off state. When it is desired to have the output node (26) at a low logic state, the circuit (22) is left unchanged. But if it is determined that the output node (26) should be at a high logic level state, the fusible link (28) is opened by a first laser pulse. A second laser pulse is then applied to transistor (24) to cause damage to the structure of the transistor (24). The transistor (24) can be damaged in any of a number of modes which result in the formation of a conducting path between the output node (26) and the power terminal V cc . Unlike conventional laser switch circuits, the circuit (22) does not draw static power under any conditions thereby reducing power consumption by the integrated circuit utilizing such a laser switched gate. In a further embodiment a single transistor (90) fabricated in a nonconducting state is connected between first and second nodes (92, 94) but when damaged by a laser pulse the transistor (90) provides a low impedance connection between the nodes (92, 94). In a still further embodiment a transfer (110) is provided with a fusible link gate (110a), and is fabricated to be in an off state. A laser beam programs the transistor (110) by simultaneously opening the fusible link gate (110a) and altering the structure of the transistor to provide a low impedance path between the drain and source terminals thereof.

48 citations

Journal ArticleDOI
TL;DR: In this article, a multipeak negative-differential-resistance (NDRS) device with a single-electron transistor (SET) and a metal-oxide-semiconductor field effect transistor (MOSFET) was proposed.
Abstract: A multipeak negative-differential-resistance device is proposed. The device comprises a single-electron transistor (SET) and a metal–oxide–semiconductor field-effect transistor (MOSFET), and can, in principle, generate an infinite number of current peaks. Operation of the proposed device is verified at 27 K with a SET fabricated by the pattern-dependent oxidation process and a MOSFET on the same silicon-on-insulator wafer. Six current peaks and a peak-to-valley current ratio of 2.1 are obtained, and multiple-valued memory operation is successfully demonstrated.

48 citations

Patent
20 Feb 2002
TL;DR: In this paper, a display device capable of keeping the luminance constant irrespective of temperature change is provided as well as a method of driving the display device, where a current mirror circuit composed of transistors is placed in each pixel.
Abstract: A display device capable of keeping the luminance constant irrespective of temperature change is provided as well as a method of driving the display device. A current mirror circuit composed of transistors is placed in each pixel. A first transistor and a second transistor of the current mirror circuit are connected such that the drain current of the first transistor is kept in proportion to the drain current of the second transistor irrespective of the load resistance value. The drain current of the first transistor is controlled by a driving circuit in accordance with a video signal and the drain current of the second transistor is caused to flow into an OLED, thereby controlling the OLED drive current and the luminance of the OLED.

48 citations

Patent
Bernard L. Morris1
28 Oct 1993
TL;DR: In this paper, an integrated circuit is disclosed comprising a first field effect transistor having a source connected to a first node and a gate connected to the second node, and a second field-effect transistor for protecting the first transistor from voltages that are greater than a predetermined nominal voltage.
Abstract: An integrated circuit is disclosed comprising a first field effect transistor having a source connected to a first node and a gate connected to a second node, and a second field effect transistor for protecting the first transistor from voltages applied to the first node and greater than a predetermined nominal voltage. The second transistor includes a drain connected to the second node, a source connected to the first node, and a gate connected to a third node. A constant voltage source is coupled to the third node and supplies a gate voltage to the gate of the second transistor such that a drain-source path of the second transistor does not conduct while voltage applied to the first node is generally less than the gate voltage plus a threshold voltage of the second transistor. The constant voltage source comprises a third field effect transistor having a drain and a gate connected to the third node, and a source coupled to a first power supply voltage, such that the gate voltage is substantially equal to the first power supply voltage minus a threshold voltage of the third transistor.

48 citations

Patent
02 Jan 1998
TL;DR: In this paper, a bistable SCR-like switch is provided by a first and a second transistors (42 and 44) which are formed upon the insulator layer of the SOI circuit and are separated from one another by an insulating region.
Abstract: A bistable SCR-like switch (41) protects a signal line (65) of an SOI integrated circuit (40) against damage from ESD events. The bistable SCR-like switch (41) is provided by a first and a second transistors (42 and 44) which are formed upon the insulator layer (46) of the SOI circuit (40) and are separated from one another by an insulating region (60). Interconnections (62 and 64) extend between the two transistors (42 and 44) to connect a P region (62) of a first transistor (42) to a P region (54) of the second transistor (44) and an N region (50) of the first transistor (42) to an N region (58) of the second transistor (44). The transistors (42 and 44) may be either bipolar transistors or enhancement type MOSFET transistors. For bipolar transistors, the base of an NPN transistor (42) is connected to the collector of a PNP transistor (44) and the base of the PNP transistor (44) is connected to the collector of the NPN transistor (42). MOSFET transistors are similarity connected, with the intermediate portion of the P-well (43) forming channel region of the N-channel transistor (42) connected to the drain of the P-channel transistor (44), and the N-well (45) forming the channel region of the P-channel transistor (44) connected to the drain of the N-channel transistor (42). Resistors (72 and 74) can be connected between the two transistors (42 and 44) to determine the trigger and holding voltages for the bistable SCR-like switch (41).

48 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20234
20225
20211
20203
20196
20189