Static induction transistor

About: Static induction transistor is a research topic. Over the lifetime, 8155 publications have been published within this topic receiving 107058 citations. The topic is also known as: SIT.

Semiconductor memory with non-volatile memory transistor

Abstract: With a semiconductor memory cell (particularly but not exclusively in a thin-film device) having a non-volatile memory transistor (Tm) as a driver transistor, the invention permits an adequate difference in output signal (I) to be derived from the cell for the different states of the memory transistor (in spite of poor transistor characteristics) thereby permitting the assembly of a large number of such memory cells in an array (100). Each memory cell includes a load (Tl) driven by the non-volatile memory transistor (Tm). In the different memory states of the memory transistor (Tm), a difference in signal occurs at a node (30) between the memory transistor (Tm) and the load (Tl). Each cell also includes a switch (To) which is coupled to the node (30) and switched from one output state to another by the signal at the node (30). The output state of the switch (To) provides the output signal (l) from the cell. Such an arrangement in accordance with the invention permits the memory transistor (Tm) and the output switch (To) to be optimised for their respective memory function and output function. The memory transistor may be of the dielectric-storage type (MNOST) or of the floating-gate type. In a thin-film circuit memory, the output switch may be a thin-film transistor (To) or a thin-film diode.

Memory with ferroelectric capacitor connectable to transistor gate

Abstract: A ferroelectric memory includes a constant voltage source, a capacitor having first and second electrodes, and a transistor having a gate. A switch alternately connects the gate of the transistor to the first electrode and the constant voltage source. In another embodiment, there are two ferroelectric transistors, and the first electrode of each capacitor is connected both to the gate of the transistor and to a voltage source external of the memory.

Complementary MIS transistor and a fabrication process thereof

Abstract: A CMIS transistor suitable for device miniaturization, elimination of degradation of operational characteristics by hot carrier effect, and elimination of decrease of threshold voltage caused by short channel effect, includes a laterally spreading N-type diffusion region having an impurity concentration level higher than P-type and N-type wells but lower than source and drain regions, such that the N-type diffusion region extends laterally into a part located immediately below an edge of an insulating gate and has a depth smaller than a depth of the source and drain regions. The device is thereby capable of increasing the width of depletion layer at the bottom of the source and drain regions while maintaining effectiveness as a punch-through stopper. Thereby, the junction capacitance at the source and drain regions is reduced and the operational speed of the device improved in the P-channel transistor part in the device. In the N-channel transistor part, an effective suppression of punch-through is achieved because of the small diffusion depth of the N-type diffusion region. Thereby, the decrease of threshold voltage caused by the short channel effect is effectively eliminated even when the gate length of the transistor is reduced.

Apparatus for a two phase bootstrap charge pump

Abstract: An integrated circuit charge pump circuit including a plurality of stages, each stage including a first N type field effect switching transistor device having source and drain terminals connected in series with the source and drain terminals of all other stages, a second N type field effect control transistor device having drain and source terminals connecting the drain terminal and the gate terminal of the first switching transistor device, and a storage capacitor joined to the source terminal of the first device; a source of voltage to be pumped is connected to the drain terminal of the first device of the first stage. A first series of clock pulses is applied to the gate terminals of the first switching transistor devices in every other stage of the charge pump and to the gate terminals of the second control transistor devices in stages between; and a second series of clock pulses which do not overlap the first series of clock pulses is applied to the gate terminals of the first switching transistor devices in alternate stages of the charge pump and to the gate terminals of the second control transistor devices in stages between the alternate stages. These pulses cause the switching transistor to switch on and off in alternate stages in a manner that the gate terminal goes higher than the drain terminal so that charge is transferred without threshold drop between stages and high current as well as high voltage is pumped to the output terminal.

Semiconductor memory device comprising a plurality of static memory cells

Abstract: A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor.