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Static routing

About: Static routing is a research topic. Over the lifetime, 25733 publications have been published within this topic receiving 576732 citations.


Papers
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Journal ArticleDOI
TL;DR: This paper combines routing and cooperative diversity, with the consideration of a realistic channel model, on a multihop network with multiple relays at each hop, and three routing strategies are designed to achieve the full diversity gain provided by cooperation among the relays.
Abstract: The fading characteristics and broadcast nature of wireless channels are usually not fully considered in the design of routing protocols for wireless networks. In this paper, we combine routing and cooperative diversity, with the consideration of a realistic channel model. We focus on a multihop network with multiple relays at each hop, and three routing strategies are designed to achieve the full diversity gain provided by cooperation among the relays. In particular, an optimal routing strategy is proposed to minimize the end-to-end outage, which requires the channel information of all the links and serves as a performance bound. An ad-hoc routing strategy is then proposed based on a hop-by-hop relay selection, which can be easily implemented in a distributed way. As expected, ad-hoc routing performs worse than optimal routing, especially with a large number of hops. To achieve a good complexity-performance tradeoff, an N-hop routing strategy is further proposed, where a joint optimization is performed every N hops. Simulation results are provided which verify the outage analyses of the proposed routing strategies.

135 citations

Proceedings ArticleDOI
05 Nov 2006
TL;DR: An extremely fast and high-quality global router called FastRoute is presented that incorporates global routing directly into placement process without much runtime penalty and will fundamentally change the way the EDA community look at and make use of global routing in the whole design flow.
Abstract: Because of the increasing dominance of interconnect issues in advanced IC technology, placement has become a critical step in the IC design flow. To get accurate interconnect information during the placement process, it is desirable to incorporate global routing into it. However, previous global routers are computationally expensive. It is impractical to perform global routing repeatedly during placement. In this paper, we present an extremely fast and high-quality global router called FastRoute. In traditional global routing approaches, congestion is not considered during Steiner tree construction. So they have to rely on the time-consuming maze routing technique to eliminate routing congestion. Different from traditional approaches, we proposed a congestion-driven Steiner tree topology generation technique and an edge shifting technique to determine the good Steiner tree topologies and Steiner node positions. Based on the congestion-driven Steiner trees, we only need to apply maze routing to a small percentage of the two-pin nets once to obtain high quality global routing solutions. We also proposed a new cost function based on logistic function to direct the maze routing. Experimental results show that FastRoute generates less congested solutions in 132times and 64times faster runtimes than the state-of-the-art academic global routers Labyrinth (R. Kastner et al, 2000) and Chi Dispersion router (R. T. Hadsell and P. H. Madden, 2003), respectively. It is even faster than the highly-efficient congestion estimator FaDGloR (J. Westra and P. Groeneveld, 2005). The promising results make it possible to incorporate global routing directly into placement process without much runtime penalty. This could dramatically improve the placement solution quality. We believe this work will fundamentally change the way the EDA community look at and make use of global routing in the whole design flow

135 citations

Journal ArticleDOI
TL;DR: A detailed survey of various techniques for enhancing the performance and reliability of wormhole-routing schemes in directly connected networks and discusses several fault-tolerant wormhole routing algorithms along with their fault-handling capabilities.
Abstract: Wormhole routing has emerged as the most widely used switching technique in massively parallel computers. We present a detailed survey of various techniques for enhancing the performance and reliability of wormhole-routing schemes in directly connected networks. We start with an overview of the direct network topologies and a comparison of various switching techniques. Next, the characteristics of the wormhole routing mechanism are described in detail along with the theory behind deadlock-free routing. The performance of routing algorithms depends on the selection of the path between the source and the destination, the network traffic, and the router design. The routing algorithms are implemented in the router chips. We outline the router characteristics and describe the functionality of various elements of the router. Depending on the usage of paths between the source and the destination, routing algorithms are classified as deterministic, fully adaptive, and partially adaptive. We discuss several representative algorithms for all these categories. The algorithms within each category vary in terms of resource requirements and performance under various traffic conditions. The main difference among various adaptive routing schemes is the technique used to avoid deadlocks. We also discuss a few algorithms based on deadlock recovery techniques. Along with performance, fault tolerance is essential for message routing in multicomputers, and we thus discuss several fault-tolerant wormhole routing algorithms along with their fault-handling capabilities. These routing schemes enable a message to reach its destination even in the presence of faults in the network. The implementation details of wormhole routing algorithms in contemporary commercial systems are also discussed. We conclude by itemizing several future directions and open issues.

135 citations

Patent
08 Mar 2001
TL;DR: In this paper, a Steiner tree is generated without any of constraints such as layers, prohibition and a wiring capacity as an initial solution, and partial correction of the Steiner Tree is repeated so as not to increase a line length as far as possible in consideration of constraints.
Abstract: A global routing method acquiring global routing between net terminals of cells placed on a VLSI chip. First, a Steiner tree is generated without any of constraints such as layers, prohibition and a wiring capacity as an initial solution. Then, partial correction of the Steiner tree is repeated so as not to increase a line length as far as possible in consideration of constraints such as a prohibiting region, a wiring capacity and layers based on the initial solution of the Steiner tree to obtain the global routing. The Steiner tree is corrected generating a path collection obtained by dividing the Steiner tree into a plurality of paths each having at least a Steiner point, as a value, being an intersection of 3 or more branches.

134 citations

Journal ArticleDOI
TL;DR: The decomposition is demonstrated by implementing an overlay construction toolkit Overlay Weaver, which is the first feasibility proof of the layered model by supporting multiple algorithms and the higher-level services and the resulting algorithm implementations work on a real TCP/IP network as it is.

134 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202391
2022209
202130
202035
201962
2018132