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Showing papers on "Strained silicon published in 1971"


Journal ArticleDOI
TL;DR: In this article, the selective epitaxial growth of Si through the window in silicon nitride film is studied for the SiCl4-H2 system, and the experimental results are explained by the nucleation theory.
Abstract: The selective epitaxial growth of Si through the window in silicon nitride film is studied for the SiCl4-H2 system. Experiments prove that the silicon nitride film is extremely stable compared with the usual silicon dioxide film. To find out the necessary conditions for the selective epitaxial growth, the growth rates of Si on silicon nitride film and on silicon bare surface are obtained independently from the experiment. The critical SiCl4 pressure for the nucleation on silicon nitride film is determined as a function of growth temperature. The experimental results are explained by the nucleation theory.

19 citations


Journal ArticleDOI
TL;DR: In this article, a dependency of electrical characteristics of Si epitaxial junction on acceleration energy of silicon ions was measured, and a location of the interface and a distribution profile of defects were investigated by means of He+ back-scattering technique.
Abstract: Epitaxial n-type silicon layers were grown on p-type silicon substrates by vacuum deposition combined with silicon ion implantation (PIVD). A dependency of electrical characteristics of Si epitaxial junction on acceleration energy of silicon ions was measured. A location of the interface and a distribution profile of defects were investigated by means of He+ back-scattering technique, and some distance shift of the interface occurred in the case of PIVD.

17 citations


Patent
David Dewitt1
19 Feb 1971
TL;DR: In this article, an isolated gate field effect transistor with a thin layer of silicon nitride forming the insulation in the gate portion and a thicker layer of silicon dioxide forming insulation over the remainder of the device is described.
Abstract: A semiconductor structure in which a substrate having surface regions of opposite type conductivity is covered with two different insulating layers. In a specific structure, the regions in the substrate form an isolated gate field effect transistor with a thin layer of silicon nitride forming the insulation in the gate portion and a thicker layer of silicon dioxide forming the insulation over the remainder of the device.

7 citations


Journal ArticleDOI
TL;DR: In this paper, the effects of defect levels on the electrical properties of germanium and silicon are discussed, with some specific examples being chosen to demonstrate the various effects, including charge trapping centers and scattering centers.
Abstract: The electrical properties of thin films of germanium and silicon are heavily dependent on the crystalline perfection of the films. Defects in the thin films have strikingly different energy levels in germanium and in silicon. In germanium the defects introduce a relatively shallow acceptor, with activation energy less than 0.15 eV, and this level tends to lead to heteroepitaxial films that are P type and to limit the range of doping densities available in these films. The defects introduce scattering centers that lower the Hall mobilities. In silicon the defects introduce a donor-acceptor pair, both of which are far removed from the bandedges. These deep levels act as charge trapping centers and as scattering centers which can lower carrier concentration, Hall, mobilities, and minority carrier lifetimes. The effects of these defect levels on the electrical properties of germanium and silicon are discussed, with some specific examples being chosen to demonstrate the various effects.

7 citations


Patent
G Kamath1
04 Jan 1971
TL;DR: In this article, the production of electroluminescent silicon carbide junction diodes is described, where the silicon contains one or more p or n-type impurities so that a pn junction is formed on the crystal.
Abstract: The production of electroluminescent silicon carbide junction diodes is described. These diodes are preferably produced by growth from a silicon carbide or carbon solution in silicon formed between a surface of a p or n-type silicon carbide base crystal and a source of carbon atoms such as a block of solid carbon. The silicon contains one or more p or n-type impurities so that a p-n junction is formed on the crystal. A small quantity of a metal selected from the group consisting of niobium and hafnium is added to the silicon to provide a continued liquid phase despite rapid evaporation of the silicon during the high temperature portion of the growth step when temperatures in excess of 2,400*C are preferably used. This provides a relatively strain-free epitaxial layer (or layers) having optimum electroluminescent properties. When multilayers are grown, the initial layer can be very thin (less than 0.0005 inch) and transparent and the second layer can be opaque and of low resistance due to codoping with boron and aluminum.

7 citations


Patent
14 Jul 1971
TL;DR: In this paper, the top surface of a SILICON is exposed to a Chemical VAPOR ENVIRONMENT of NITRIC OXIDE, HYDROGEN FLUORIDE and WATER at about 35 degrees C.
Abstract: THE TOP SURFACE OF A SILICON SUBSTRATE HAVING A PARTICULAR IMPURITY PROFILE IS EXPOSED TO A CHEMICAL VAPOR ENVIRONMENT OF NITRIC OXIDE, HYDROGEN FLUORIDE AND WATER AT ABOUT 35 DEGREES C., AND FOR ABOUT 3 TO 5 MINUTES SIMULTANEOUSLY WITH THE EXPOSURE TO THE ABOVE-DESCRIBED VAPOR MIXTURE AN IMAGE IS PROJECTED INTO THE TOP SURFACE OF THE SILICON SUBSTRATE DURING THE ENTIRE TIME INTERVAL OF VAPOR EXPOSURE. FOR COMPLETION OF DEVICE FABRICATION, DOPANT ATOMS ARE THEN DIFFUSIONN INTO THE SILICON SURFACE WHERE THE IMAGE HAS BEEN PROJECTED.

6 citations


Patent
J Dunkley1, B Smith1
18 Mar 1971
TL;DR: In this article, a method of producing a transistor and a resistor on a chip is disclosed in which the thickness of the layers of silicon dioxide over the base and collector areas and over the resistor areas are more nearly equal prior to the emitter-collector photoresist operation, whereby overetching is greatly reduced when the holes are etched through the silicon dioxide layers in the production of emitter and collector contacts.
Abstract: When transistors and resistors are provided on a chip or a wafer to become the electrical components of a digital or linear circuit, the emitter and collector regions must be etched simultaneously utilizing conventional photoresist techniques. In accordance with the prior art, the silicon dioxide layer over the area where the collector-contact is to be provided is substantially thicker than the silicon dioxide layer over the area where the emitter is to be provided, whereby the total time of etch must be great enough to etch the thicker silicon dioxide layer over the collector contacts, whereby the thinner layer is overetched, resulting in undercutting of the silicon dioxide layer in an umpredictable manner. The resulting emitters are larger in area than desired, resulting in a transistor having an emitter that is larger and therefore slower than is desired. A method of producing a transistor and a resistor on a chip is disclosed in which the thickness of the layers of silicon dioxide over the base and collector areas and over the resistor areas are more nearly equal prior to the emitter-collector photoresist operation, whereby overetching is greatly reduced when the holes are etched through the silicon dioxide layers in the production of the emitter and collector contacts. Furthermore, the silicon dioxide layer is grown, rather than being chemically deposited, since the grown silicon dioxide layer is denser, purer, and less likely to have pinholes therein than deposited silicon dioxide layers that have been used in the prior art.

5 citations


Patent
W Muller1, Joachim Dathe1, Leo Grasser1
19 Feb 1971
TL;DR: In this paper, one side of a p-conducting silicon wafer is provided with a base zone through masked diffusion of phosphorus atoms, and a subsequent diffusion process increases the phosphorus concentration at the surface of the base zone to 1020 to 1021 phosphorous atoms/cm3.
Abstract: During the production of a pnp silicon transistor, one side of a p-conducting silicon wafer is provided with a base zone through masked diffusion of phosphorus atoms. A subsequent diffusion process increases the phosphorus concentration at the surface of the base zone to 1020 to 1021 phosphorous atoms/cm3. The same phosphorus concentration is produced at the opposite side of the silicon wafer. The emitter is produced in the region of the base zone through a masked diffusion of acceptor atoms. Finally, the phosphorus-doped layer is removed from the reverse or back side of the semiconductor wafer.

4 citations


Patent
12 Feb 1971
TL;DR: The OXIDE LAYER as mentioned in this paper was designed by a mechanized version of the SILICON SURFACE using a process of combining OXYGEN and an oxide of the DOPANT to ensure that during the production of the XIDE Llayer no dopant penetrates into the SEMICONDUCTOR DIFFUSION is carried out.
Abstract: THE OXIDE LAYER IS PRODUCED BY THERMAL OXIDATION OF THE SILICON SURFACE USING A PROCESSING GAS COMPRISING OXYGEN AND AN OXIDE OF THE DOPANT THIS INSURES THAT DURING THE PRODUCTION OF THE OXIDE LAYER NO DOPANT PENETRATES INTO THE SEMICONDUCTOR DIFFUSION IS CARRIED OUT BY A SUBSEQUENTLY EXECUTED THERMAL PROCESS

3 citations


Journal ArticleDOI
TL;DR: In this paper, it was shown that the lattice mobility of electrons in silicon is determined by high energy acoustic phonons (zero point scattering) rather than by optical phonons.

1 citations