Showing papers on "Strained silicon published in 1972"

Structure and electrical characteristics of epitaxial palladium silicide contacts on single crystal silicon and diffused P-N diodes

Abstract: Pd2Si contacts to single crystal silicon have been made by depositing Pd at room temperature and annealing at a succession of elevated temperatures. The silicide initially formed is a single crystal, even at room temperature. Its crystal structure is uniquely related to that of the underlying silicon with the basal plane of Pd2Si making an excellent match, with respect to silicon atom positions, with the (111) plane of silicon. Understanding this epitaxy leads to an appreciation of the excellent electrical characteristics of these contacts which are shown to be superior to alloyed aluminum. For comparison, barrier height measurements reproduce earlier results of Kircher on Pd2Si formed during a high temperature (200°C) deposition of Pd.

Growth mechanism of polycrystalline β‐SiC layers on silicon substrate

Abstract: The surface of monocrystalline silicon was chemically converted with hydrocarbon to polycrystalline β‐silicon carbide, and the growth mechanism was investigated by means of 14C tracer method. It is shown that the growth of the silicon carbide layer is due to diffusion of silicon through the SiC layer so that the Si–SiC conversion is taking place at the surface of the sample. Dependence of layer thickness on carbidizing time and on hydrocarbon concentration in the carrier gas hydrogen was measured.

Simulation of the atomic arrangements in amorphous silicon and germanium

Abstract: The atomic arrangements in amorphous germanium and silicon are simulated by means of a computer program. In this treatment a disordered system of 64 atoms in a cubic box with periodic boundary conditions is taken as the initial configuration. Each atom is considered in turn and the four nearest and twelve second-nearest neighbors are moved radially towards the nearest and next nearest neighbor distances. The resulting radial distribution function is in good agreement with experiment.

Multilevel conductor structure and method

Abstract: The present invention relates to a multilevel conductor structure and to a method of insulating an upper level of conductors from a lower level of conductors on a silicon substrate of an integrated circuit. An undoped silicon oxide insulator layer and a doped silicon oxide insulator layer are successively placed on the lower level of conductors and the structure is heated to a temperature which is sufficient to cause the doped oxide insulator layer to soften and to flow above the lower conductors to produce tapered steps over the edges of the lower level of conductors. An upper level of conductor is then formed on the tapered doped silicon oxide insulator layer. The undoped silicon oxide insulator layer formed between the doped silicon oxide insulator layer and the lower level of conductors prevents doping atoms of the doped silicon oxide insulator layer from penetrating into source or drain regions of the silicon substrate which are usually in the vicinity of the lower level of conductors to change their conductivity.

Shielded silicon gate complementary MOS integrated circuit

Abstract: An electrostatic shield for complementary MOS integrated circuits was developed to minimize the adverse effects of stray electric fields created by the potentials in the metal interconnections. The process is compatible with silicon gate technology. n-doped polycrystalline silicon was used for all the gates and the shield. The effectiveness of the shield was demonstrated by constructing a special field plate over certain transistors. The threshold voltages obtained on a oriented silicon substrate ranged from 1.5 to 3 V for either channel. Integrated inverters performed satisfactorily from 3 to 15 V, limited at the low end by the threshold voltages and at the high end by the drain breakdown voltage of the n-channel transistors. The stability of the new structure with an n-doped silicon gate as measured by the shift in C-V curve under 200°C ± 20 V temperature-bias conditions was better than conventional aluminum gate or p-doped silicon gate devices, presumably due to the doping of gate oxide with phosphorous. The advantages of the new structure are: avoidance of field inversion, elimination of guard rings, and thinner and more stable oxides.

Processes for the localized and deep diffusion of gallium into silicon

Abstract: Process for the localized and deep diffusion of gallium into silicon, and silicon nitride mask utilization; and semi-conductor devices obtained thereby. A process of this type comprises the following operations: a) preparation of the surface of a specimen of N-type silicon intended to receive the diffusion localization mask; b) deposition of a first oxide layer on this surface; c) deposition of a silicon nitride layer forming a mask on the first oxide layer; d) photoengraving of the mask by means of a photosensitive product and a transfer layer formed by a second oxide layer; and opening of windows of localized diffusion in the mask; e) prediffusion of gallium into the silicon by means of the windows, and through the first oxide layer; f) removal of the silicon nitride mask and of the first oxide layer; g) deposition of a new first oxide layer on the whole silicon surface, followed by a new silicon nitride layer on this oxide layer; h) thermal treatment for penetration diffusion of the gallium into the silicon; i) removal of the layer of oxide and silicon nitride deposited during operation g), in order to obtain a structure with a localized and deep P-N junction. The invention makes it possible, in particular, to obtain new combinations of structures having localized zones of diffused gallium, diodes or thyratrons having localized P-N junctions, with a silicon nitride mask whose use can reduce the contamination of the semi-conductor material by oxygen.

Method of providing polycrystalline layers of elementtary substances on substrates

Abstract: A method of providing a polycrystalline layer of silicon on a silicon substrate having a surface oxide layer. A carrier gas containing a decomposable hydrogen compound of carbon or silicon is passed over the substrate while the substrate is heated at the decomposition temperature of the hydrogen compound, with the result that a dense nucleation layer is deposited. A reducible silicon compound is then introduced into the carrier gas in the presence of hydrogen to cause the silicon compound to be reduced releasing silicon which is deposited on the nucleation layer as a layer polycrystalline silicon which is even and uniform.

The combination of silicon nitride and aluminum anodization for semiconductor device passivation

Abstract: The combination of silicon nitride and barrier anodization of the aluminum interconnects serves as excellent passivation for bipolar silicon devices, even under conditions of massive ionic contamination at temperatures as high as 400°C. This combination removes the restriction that silicon nitride positively overlap the edges of all contact cuts and thus results in savings in device area. In addition, the processing complexity is somewhat reduced in that the silicon nitride can be delineated by a self-aligning anodization technique.

Process for the formation of selfaligned silicon and aluminum gates

Abstract: A PROCESS FOR THE SIMULTANEOUS FORMATION OF SELFALIGNED SILICON GATES AND ALUMINUM GATES HAVING SELFALIGNED CHANNEL REGIONS ON THE SAME WAFER IS DISCLOSED. BASICALLY, THE PROCESS CONSISTS OF THE DEPOSITION OF SUCCESSIVE LAYERS OF SILICON NITRIDE AND POLYCRYSTALLINE SILICON OVER THICK AND THIN SILICON DIOXIDE REGIONS WHICH ARE DISPOSED ON THE SURFACE OF A SEMICONDUCTOR WAFER. POLYSILICON GATES ARE DELINEATED IN THE THIN OXIDE REGIONS. SUBSEQUENTLY, A CHEMICALLY VAPOR DEPOSITED SILICON DIOXIDE LAYER IS FORMED OVER THE SURFACE OF THE EXPOSED SILICON NITRIDE LAYER AND OVER THE POLYCRYSTALLINE SILICON GATE GEGIONS. AT THIS POINT, THE CVD OXIDE IS DELINEATED TO FORM AN OXIDE MASK WHICH WILL PERMIT THE REMOVAL OF SILICON NITRIDE DOWN TO THE THIN OXIDE AT CERTAIN REGIONS WHERE DIFFUSION WINDOWS ARE TO BE FORMED IN EXPOSED THIN OXIDE REGIONS WHICH ARE SUBSEQUENTLY REMOVED BY A DIP ETCH. WHILE THE EXPOSED THIN OXIDE REGIONS ARE MASKED BY EITHER SILICON NITRIDE PORTIONS OR POLYCRYSTALLINE SILICON GATE REGIONS, THE MASKING REGIONS OF CVD OXIDE WHICH PROTECTED THE SILICON NITRIDE LAYER ARE SIMULTANEOUSLY REMOVED BY THE DIP ETCH WHICH OPENS THE DIFFUSION WINDOWS IN THE THIN OXIDE REGIONS. AFTER A DIFFUSION STEP WHICH INCLUDES DEPOSITION OF A PHOSPHORUS DOPANT IN THE DIFFUSION WINDOWS FROM THE VAPOROUS PHASE AND A DRIVE-IN STEP, A THERMAL OXIDATION STEP IS CARRIED OUT WHICH COVERS THE DIFFUSED WINDOW REGIONS AND THE POLYSILICON GATES AND THICK OXIDE REGIONS LEAVING THE EXPOSED NITRIDE PORTIONS UNAFFECTED. IN A SUBSEQUENT MASKING STEP, DIFFUSION CONTACT WINDOWS AND SILICON GATES CONTACT WINDOWS ARE OPENED. THEN, METALLIZATION IS DEPOSITED EVERYWHERE AND DELINEATED TO FORM METAL GATES AND CONTACTS TO BOTH DIFFUSIONS AND SILICON GATES. METAL IS DELINEATED AND FORMED IN EACH OF THE EXPOSED SILICON NITRIDE REGIONS ONE OF WHICH IS A SELF-ALIGNED CHANNEL REGION FOR A METAL GATE FIELD-EFFECT TRANSISTOR. OTHER METAL GATES FOR A CHARGE COUPLED DEVICE ARE POSITIONED BY VIRTUE OF THE PRESENCE OF ADJACENT POLYSILICON GATES AND ARE INSULATED FROM THE SUBSTRATE BY A THIN OXIDE AND NITRIDE LAYER AND FROM THE SILICON GATES BY A LAYER OF THERMALLY GROWN SILICON DIOXIDE ON THE SURFACE OF THE SILICON GATES. THE RESULTING STRUCTURE INCLUDES A METAL GATE FIELD-EFFECT TRANSISTOR, A SELF-ALIGNED SILICON GATE FIELD-EFFECT TRANSISTOR, AND A CHARGE COUPLED DEVICE ON THE SAME WAFER. BY USING AN ADDITIONAL MASKING STEP OVER THAT REQUIRED FOR THE FORMATION OF SILICON SELF-ALIGNED GATES ALONE, METAL GATES WHICH ARE EITHER SELF-ALIGNED BY VIRTUE OF ADJACENT POLYSILICON GATES OR BY VIRTUE OF THE PRESENCE OF A SELF-ALIGNED CHANNEL ARE THUS OBTAINED. IN ADDITION, A RANDOM ACCESS CHARGE COUPLED DEVICE WHICH INCORPORATES A METAL TRANSFER GATE AND A POLYSILICON STORAGE PLATE IS ALSO DISCLOSED. THE STRUCTURE RESULTS FROM THE ABOVE DESCRIBED FABRICATION PROCESS AND IS STRUCTURALLY UNIQUE IN THAT THE METAL GATE IS DISPOSED IMMEDIATELY ADJACENT TO A DIFFUSION REGION WHICH ITSELF IS DISPOSED UNDER A THICK OXIDE LAYER. IN ADDITION, THE POLYCRYSTALLINE SILICON STORAGE PLATE IS SPACED FROM THE METAL GATE BY A LAYER OF THERMALLY GROWN SILICON DIOXIDE.

Electrical Charactristics of Polycrystalline Silicon-Silicon Nitride-Silicon Dioxide-Silicon Structures

Abstract: The influences of annealing at high temperatures and of impurity diffusion such as phosphorus and boron on fast surface states and instabilities under bias-temperature treatment were investigated. The fast surface states and instabilities increased by annealing in nitrogen, argon and oxygen. The instabilities were caused by the increase in conductivity of silicon nitride films. It was supposed that during annealing, localized strains under polycrystalline silicon electrodes were absorbed by silicon nitride films which in turn underwent large deformation and became filled with high density traps responsible for the increase of conductivity of silicon nitride films. Annealing in hydrogen reduced fast surface states and improved the instabilities. These phenomena are explained by the elimination of traps on SiO2–Si interface and in the bulk of silicon nitride.

Method to produce high concentrations of dopant in silicon

Abstract: A novel method for producing very high concentrations of semiconductor dopants in silicon by a diffusion process. The concentration of dopant achievable by the present invention approaches the solid solubility limit of the dopant material. First an undoped layer of material, typically silicon dioxide, is deposited over one or both of the planar surfaces of a silicon substrate of a particular conductivity type. Next a second layer of doped silicon dioxide is deposited over the first layer, the dopant therein being of a conductivity type opposite of that of the silicon wafer. A third layer of undoped silicon dioxide is then deposited over the second layer. Next, the substrate of silicon, with the three layers deposited thereon, is heated to a temperature which causes the diffusion of some dopant into the upper region of the silicon substrate. The three layers of silicon dioxide are then stripped off, and three fresh layers are deposited. The heating step is repeated, ''''pumping,'''' by diffusion, more dopant into the silicon substrate from the fresh source. The process can be repeated, thereby enabling the concentration of dopant in the silicon substrate to approach the solid solubility limit. This invention also contemplates growing the layers of silicon dioxide by controlled oxidation of the substrate, instead of by depositing them.

Silicon Contamination in Vapor-Grown Gallium Arsenide

Abstract: An analysis of silicon distribution in epitaxial gallium arsenide layers grown by halide synthesis transport is made using an Electron Probe Micro Analyzer. High concentration of silicon is detected not only in the sample grown on silicon doped substrate but on tellurium doped substrate. When high concentration silicon is detected at the interface between epitaxial layer and substrate, the sample shows high resistivity region at the interface. It is found that inclusions of silicon exist in the form of elemental silicon and silicon oxide. It is also observed that Pyramid or hillock formation is caused by silicon contamination.