Showing papers on "Strained silicon published in 1973"

Epitaxial silicon layers grown on ion‐implanted silicon nitride layers

Abstract: Buried layers of silicon nitride approximately 4000 A in width have been formed by ion implantation while retaining a relatively undamaged silicon surface region. Epitaxial silicon of 2‐μm thickness grown on these surfaces exhibits significantly lower defect concentrations than do silicon layers on spinel, as determined by optical microscopy and by proton channeling measurements. The breakdown voltage of the silicon nitride layers is approximately 7 × 105 V/cm, and the refractive index is 2.05 at 6328 A.

The diffusion of germanium in silicon

Abstract: The diffusion of germanium in single‐crystal silicon has been measured using the radioactive tracer 71Ge and a thin sectioning technique. The activation energy of 4.7 eV determined from the data is analyzed by considering the expected contribution due to the wrong‐sized impurity ions. It is concluded that the high activation energy observed is expected from analogy to silicon self‐diffusion.

Process for fabricating MNOS non-volatile memories

Abstract: The switching speed of an MNOS field effect transistor is increased by a heat treatment in an ammonia rich atmosphere during processing. The transistor has an insulated gate structure comprising a layer of silicon nitride deposited on a layer of silicon oxide. After the formation of the silicon oxide layer and immediately prior to the formation of the silicon nitride layer on a surface thereof, the surface of the silicon oxide layer is heat treated in an ammonia enriched atmosphere to remove substantially all remaining oxygen atoms and molecules absorbed on the surface.

Diffusion in Silicon and Germanium

Abstract: Silicon, and to a lesser extent germanium, provides the most important building foundation for modern electronic devices. Its preeminence derives both from the availability of the purest and most perfect crystals known, and from our ability to create electric potential profile structures and carrier concentrations to specifications in this material by controlled doping with impurity atoms. One of the most important methods of controlled doping is that of solid state diffusion. The high density and the high speed of devices in modern integrated circuits often require a vertical dimension of 1–3000 A and a lateral dimension of several microns. The complexity of vertical potential structures often requires several sequential diffusion steps. The net effect of various diffusion steps on an electric potential structure may be subtractive, and there may be interactions between sequential diffusion steps. The current state of the art of diffusion processes in the fabrication of integrated circuits relies on an empirical approach with trial and error. The difficulty of such an approach will increase exponentially with the increase of the number of diffusion steps, and a semiempirical approach incorporating an understanding of the details of diffusion processes may become essential.

Method of manufacturing semiconductor devices in which silicon oxide regions inset in silicon are formed by a masking oxidation, wherein an intermediate layer of polycrystalline silicon is provided between the substrate and the oxidation mask

Abstract: The manufacture of semiconductor devices, particularly silicon ICs, employing isolating inset oxides is described. To prevent formation of a projecting oxide beak under an oxidation masking layer, a layer of polycrystalline silicon is provided under the oxidation mask instead of the usual silicon oxide.

Ion-implantation and conventional epitaxy to produce dielectrically isolated silicon layers

Abstract: The disclosure relates to the formation of epitaxial silicon layers on insulating material. Buried layers of silicon nitride, oxide or carbide, approximately 4000 A in width, are formed by ion implantation while retaining a relatively undamaged layer of silicon near the surface. Epitaxial silicon of about 2 mu m thickness, for example, is grown on these surfaces and yields layers with significantly lower defect concentrations than for silicon layers on prior art substrates such as spinel.

Method for fabrication of integrated circuit structure with full dielectric isolation utilizing selective oxidation

Abstract: Structure: An integrated circuit structure with full dielectric isolation comprising a supporting substrate having a planar surface of dielectric material and a semiconductor layer on said dielectric surface which forms a planar interface with the surface Regions of oxidized silicon extend through the layer from said interface, surrounding and dielectrically isolating pockets of silicon in the layer; the oxidized silicon regions extend to the upper surface of the semiconductor layer where they are substantially co-planar with the silicon pockets The devices of the integrated circuit are formed in said silicon pockets Method: The structure is fabricated by a novel method wherein a lightly doped silicon layer is deposited on a highly doped silicon substrate; surrounding oxidized silicon regions are then formed by selectively thermally oxidizing portions of the silicon layer to form oxide regions which are co-extensive with the oxidized areas and, thus, are co-planar with the remaining silicon pockets at both surfaces of the layer; a member having a dielectric surface interfacing with the silicon layer is formed, and the silicon substrate is removed by preferential electrochemical anodic etching to leave the silicon layer having the oxidized regions surrounding spaced silicon pockets mounted on said member

Method for controlling dielectric isolation of a semiconductor device

Abstract: A dielectric isolation barrier is formed in a silicon substrate by oxidizing openings formed in an epitaxial layer on the substrate and a layer of silicon oxynitride (SiOxNy), which is on the surface of the epitaxial layer of the substrate. During this oxidation of the openings, the layer of silicon oxynitride is thermally oxidized to form an electrically insulating layer of silicon dioxide on the surface of the epitaxial layer and homogeneous with the silicon dioxide of the dielectric isolation barrier. The index of refraction of the layer of silicon oxynitride is selected in accordance with its thickness to produce a desired thickness of the layer of silicon dioxide after completion of oxidation of the openings in which the dielectric isolation barrier is formed. the index of refraction of silicon oxynitride is preferably between 1.55 and 1.70.

Properties of nonvolatile semiconductor memories by using silicon clusters in the gate insulator

Abstract: Nonvolatile memories are now focused by many people. One of the most popular structure of the memories is an MNOS (metal-silicon nitride-silicon oxide-semiconductor) structure. However the structure has poor memory retention when B-T (80°c,-10V) stress is applied to the sample. The developed structures are MNCOS and MNCNOS (metal-over silicon nitride-silicon clusters-under silicon nitride-semiconductor), in which the silicon clusters are the small polycrystalline silicon particles having a compressed hemisphere. As the clusters act as trap centers of both holes and electrons, the trapping efficiency of censers increases, and the thicker silicon oxide film (tox= 50 - 60 A) is able to use for the better memory retention. The memories can operate more than ten years under the BT (-10V, 80°c) stress condition.

Germanium bonded silicon substrate and method of manufacture

Abstract: A support member is affixed to a silicon wafer, either patterned or not patterned, forming a substrate, by providing at least the wafer with a first layer of polycrystalline silicon, followed by a second layer of polycrystalline germanium. The support member may be provided with a first layer of polycrystalline silicon followed by a second layer of polycrystalline germanium. However, in the alternative, the support member may be provided with a layer of polycrystalline germanium directly after having properly prepared the surface to which the polycrystalline germanium is to adhere. The germanium layers are placed in contact with each other and heat is applied causing an alloying or an alloy interface between the polycrystalline germanium and the polycrystalline silicon to occur. The result is a silicon substrate, either patterned or unpatterned, in appropriate condition for formation of semiconductive devices and for the attachment of beam leads.

Semiconductor light source on the basis of silicon carbide single crystal

Abstract: A semiconductor light source on the basis of n-type silicon carbide single crystal, wherein an epitaxial silicon carbide film of the same type is disposed on the basic single crystal, a p-n junction with a depth of 0.1-2 μm is arranged on the surface of this film, the basic silicon carbide single crystal having a concentration of uncompensated donor atoms of 5.sup.. 10 17 - 5.sup.. 10 18 cm - 3 and a concentration of atoms of secondary impurities not greater than 2.sup.. 10 18 cm - 3 , while the epitaxial film has a concentration of uncompensated donor atoms of 0.8.sup.. 10 18 -3.sup.. 10 18 cm - 3 , a concentration of atoms of secondary impurities of 0.4.sup.. 10 17 -1.5.sup.. 10 17 cm - 3 and a thickness of 5-100 μm.

Method of making silicon semiconductor devices utilizing enhanced thermal oxidation

Abstract: A silicon oxide layer is formed on a phosphorus doped surface region of a silicon semiconductor body by steam treatment, there being an enhanced growth rate of the silicon oxide on the phosphorus doped region enabling, for example, the provision of a low temperature steam treatment, and/or the production, possibly within an aperture in an already provided silicon oxide layer less than 3000A thick, of a thin silicon oxide layer, so that impurity concentration gradients within the semiconductor body are not caused to change by a significant extent and the surface concentration of phosphorus within the region is not significantly depleted.

Mnos memory matrix

Abstract: A semiconductor memory of a matrix of active devices each of which is metal-nitride-oxide-silicon (MNOS) field effect transistor device. Each of the active devices defines one bit of the memory. A polycrystalline silicon member defines the gate electrode for the active device and also the row conductor for the matrix. The source and drain electrodes of columns of the field effect transistors are interconnected in parallel with other source and drain electrodes of single crystal silicon of the field effect devices to define column conductors for the matrix. The matrix is manufactured by providing an insulating substrate having a layer of monocrystalline silicon thereon. The monocrystalline silicon is suitably masked and etched to define a plurality of parallel ladder-like structures wherein the side pieces of the ladder form the column conductors for the matrix while the cross pieces or the rungs of the ladder define the channel of the device. The shaped monocrystalline silicon material and the exposed substrate is then covered by a layer of silicon dioxide, a layer of silicon nitride and a layer of polycrystalline silicon utilizing suitable masking and etching steps. The polycrystalline silicon, the silicon-nitride and silicon-dioxide are removed to form the row conductors and gate electrodes for the active devices, while exposing portions of the side pieces of the ladders of semiconductor material. A single diffusion step is then required to create the source and drain junctions for the active devices; render conductive the column conductors; and render conductive the gate electrode and row conductors formed by the polycrystalline silicon, that portion of the monocrystalline silicon on the substrate underlying the gate electrode being masked by the gate electrode so as to define the channel in the originally deposited rung of the monocrystalline silicon.

Hydrogen annealing effect on silicon-insulator(s) interface states

Abstract: Interface states density for silicon dioxide-silicon, silicon nitride-silicon, and silicon nitride-silicon dioxide-silicon structures under hydrogen ambient at 500°C has been investigated. A relative measure of the interface states indicates that nascent hydrogen is an effective ambient for reducing the interface states for Si-SiO2. However, the presence of nitride layer over the oxide indicated a retardation in such a reduction.

Method for production of p-channel field effect transistors and product resulting therefrom

Abstract: A process for the production of a p-channel field effect transistor in a semiconductor layer of silicon disposed on a spinel substrate which includes the step of annealing the substrate as well as the silicon in a hydrogen atmosphere after the formation of the transistor has been completed. The formation of the electrodes and conductors for the field effect transistor may take place either before or after the annealing of the substrate and the silicon.

Boron silicide method for making thermally oxidized boron doped poly-crystalline silicon having minimum resistivity

Abstract: A method for the in-situ boron doping of polycrystalline silicon is disclosed wherein the boron-to-silicon ratio is increased beyond the limit of solubility of boron in silicon. Using appropriate flow rates of SiH4, B2H6, and H2, and deposition temperature, boron rich silicon is deposited upon a substrate. The boron is in solution in the silicon to the limit of its solubility and is present in excess amounts in boron-rich phases believed to be boron silicides. The deposited boron-rich polycrystalline silicon is subjected to a thermal oxidation step during which the dissolved boron is depleted into the growing oxide while the boron-rich phases decompose allowing the freed boron to go into solution in the silicon to replace the boron which is lost to the thermal oxide. By proper selection of parameter values, based upon experimentally determined silicon resistivity-to-B2H6 flow rate-to-thermal oxidation relationships, the boron-rich phases are substantially eliminated from the polycrystalline silicon at the same time that the thermal oxidation step is completed thereby yielding minimum resistivity doped silicon in the final structure.

Method for improving the radiation resistance of silicon transistors

Abstract: A method for improving the radiation resistance of silicon transistors of the type having silicon oxide cover layer in which a transistor or a silicon wafer with several transistor structures therein is exposed to electron radiation with an energy below 150 keV for a dose of between 109 and 1010 rad at the boundary layer between the silicon and the silicon oxide cover layer while being at a temperature of between 200 DEG and 300 DEG C. After the irradiation the transistor or silicon wafer is annealed for at least 10 hours at a temperature of between 200 DEG and 300 DEG C while a voltage of at least 0.3 V is applied in the forward direction between the emitter and the base terminal of the transistor or the transistor structures.

Method of doping a polycrystalline silicon layer

Abstract: An improved wafer type semiconductor may be fabricated by depositing an insulating film layer of predetermined thickness on a semiconductor substrate, preferably of silicon, depositing a substantially pure polycrystalline silicon layer of predetermined thickness on the insulating film layer, and thereafter depositing a doped oxide film layer of predetermined thickness on the substantially pure polycrystalline silicon layer, and effecting diffusion of the dopant into the pure polycrystalline silicon layer whereby a semiconductor wafer with a resistance of several meg-ohms.cm is provided.

Ambient Effect On Ionic Charges in Dielectric Films

Abstract: The effect of various annealing ambients on the ionic charges contained in the dielectric structures of silicon dioxide-silicon and silicon nitride-silicon dioxide-silicon was investigated. It has been observed that most effective ambients in making ionic species immobile are nitrogen and a mixture of nitrogen and hydrogen chloride gases. Further, silicon nitride used as passivating dielectric films over semiconductor devices has been observed to be an effective barrier for ionic impurities.

Some properties of mis structures with a double-layer dielectric

Abstract: The polarization properties of multilayer metal/silicon nitride/silicon dioxide/silicon structures have been studied. The dependence of the trapped charge in the double-layer dielectric on the magnitude and duration of the polarizing and depolarizing pulses and on the temperature is examined.

Thick silicon growth techniques

Abstract: Hall mobility measurements on a number of single crystal silicon ribbons grown from graphite dies have shown some ribbons to have mobilities consistent with their resistivities. The behavior of other ribbons appears to be explained by the introduction of impurities of the opposite sign. Growth of a small single crystal silicon ribbon has been achieved from a beryllia dia. Residual internal stresses of the order of 7 to 18,000 psi have been determined to exist in some silicon ribbon, particularly those grown at rates in excess of 1 in./min. Growth experiments have continued toward definition of a configuration and parameters to provide a reasonable yield of single crystal ribbons. High vacuum outgassing of graphite dies and evacuation and backfilling of growth chambers have provided significant improvements in surface quality of ribbons grown from graphite dies.