Showing papers on "Strained silicon published in 1977"

Silicon nitride films on silicon for optical waveguides

Abstract: Silicon nitride (Si(3)N(4)) thin film optical waveguides with propagation losses of less than 0.1 dB/cm for the TE(0) mode at lambda(0) = 6328 A have been successfully grown by low-pressure chemical vapor deposition. Silicon wafers 5 cm in diameter were used as substrates, and the Si(3)N(4) was separated from the substrate by a steamoxide SiO(2) buffer layer. Propagation losses are examined for the various waveguide modes, and their dependence on waveguide parameters and wavelength are discussed and compared with exact calculations. Leakage into the silicon substrate is shown to be a major loss mechanism, especially at longer wavelengths and for higher mode numbers.

Thin silicon devices

Abstract: This relates to a semiconductor device and method for making same. At least one semiconductor device is formed in a polished silicon slice, and the device is framed by a deep diffusion of boron. The surface of the slice is then coated with a layer of silicon nitride, and a glass ceramic body is bonded to the silicon nitride layer. The device is next isolated by isotropic etching, and the silicon from beneath the device is removed with a selective etch so that metal interconnections can be made to the underside of the device.

Method for manufacturing complementary insulated gate field effect transistors

Abstract: Method for manufacturing complementary insulated gate field effect transistors of LOCOS (local oxidation of silicon) structure wherein after the formation of a well layer, an impurity having higher doping level than and the same conductivity type as a semiconductor substrate (well layer) is ion implanted at an area in the semiconductor substrate on which a field oxide layer is to be formed using a silicon nitride layer as a mask, and the semiconductor substrate surface is selectively thermally oxidized using the silicon nitride layer as a mask.

Planar semiconductor devices and method of making the same

Abstract: A semiconductor device includes a region of polycrystalline silicon on a portion of the surface of a body of semiconductor material. A layer of oxidized polycrystalline silicon is also on the semiconductor material body and extends to the polycrystalline silicon region. The surface of the silicon oxide layer is substantially coplanar with the surface of the polycrystalline silicon region so that a metal film conductor can be easily provided over the semiconductor device. The polycrystalline silicon region may be the gate of an MOS transistor or a conductive region of any type of semiconductor device. The semiconductor device is made by forming a polycrystalline silicon layer over the semiconductor material body, forming a mask on a portion of the polycrystalline silicon layer, reducing the thickness of the unmasked portion of the polycrystalline silicon layer and then oxidizing the unmasked portion of the polycrystalline silicon layer to form the oxide layer.

Passivation of metallized semiconductor substrates

Abstract: Disclosed is a method and structure for protecting circuit components from the ambient and in particular for protecting the contact metal from the adverse effects of moisture. A first layer of amorphous silicon is deposited over the circuit including the metal contacts. A second layer which may be silicon nitride or silicon dioxide is then deposited over the amorphous silicon. The amorphous silicon layer reduces cracking in the second layer and prevents cracks in the second layer from propagating to the circuit components.

Method for fabricating semiconductor devices

Abstract: A method for fabricating microminiature, planar semiconductor devices in which the number of defects, in particular, pipes, is minimized. The thicknesses of the thermally grown silicon dioxide and of the silicon nitride masking layers which are used for the formation of limited impurity regions by high temperature diffusion processes within the semiconductor substrate have a specified, limited range. The thickness of the silicon dioxide is between 800A - 3000A and the thickness of the silicon nitride is between around 250A and 600A, preferably 500A. The method is particularly useful in forming extremely small emitter regions in bipolar transistors.

Method of manufacturing Si gate MOS integrated circuit

Abstract: An IC manufacturing method that eliminates the need for separate pad area and allows polysilicon MOS transistor gates to be contacted directly. Present silicon gate process techniques are utilized up to and including the formation of the gate oxide layer, with areas etched through to the substrate. Then polysilicon and silicon nitride are deposited preferably in the same deposition equipment. The polysilicon interconnect and gate pattern is selectively etched for both silicon nitride and polysilicon. Next, the gate oxide exposed by the previous step is removed and phosphorous is diffused into the exposed silicon substrate surfaces. The initial nitride thickness is chosen such that after phosphorous predeposition and subsequent removal of phosphorous glass, a thin layer of silicon nitride is left. A silicon oxide protective layer is then grown over the exposed silicon substrate surfaces. The remaining silicon nitride is removed and a phosphosilicate glass is deposited over the entire surface. Contact cuts are made through the phosphosilicate glass through which metal contacts are established.

Infrared Charge Transfer Devices: The Silicon Approach

Abstract: Possible system applications of Infrared Charge Transfer Devices are reviewed. It is found that this device technology can have a very significant systems impact. Analyses are performed to calculate the quantum efficiency, quantum yield, frequency response, photoconductive gain, operating temperature, noise and the distinction between longitudinal and transverse bias configurations of silicon detectors. Tables of silicon detector properties are included. Approaches to the interface circuitry which couples the detectors and the CTD multiplexer are examined. Examples of existing low background and high background IRCTD detector arrays are given.

MNOS Memory transistor

Abstract: A memory transistor includes a body of semiconductor material having therein a channel region of one conductivity type and source and drain regions of the opposite conductivity type. A channel insulation is on the surface of the semiconductor body and extends over the channel region. The channel insulation includes a first layer of silicon dioxide directly on the surface of the semiconductor body and a layer of silicon nitride on the silicon dioxide layer. A gate of conductive polycrystalline silicon is preferable provided on the channel insulation. The channel of the transistor is sufficiently narrow so that electrons can be avalanched into the interface between the silicon nitride layer and the silicon dioxide layer completely across the full width of the channel where the electrons can be stored.

Integrated circuit process utilizing lift-off techniques

Abstract: A method for making high density integrated circuits which utilizes lift-off techniques provides a structure having a single layer of insulating material for both the dielectric of a storage capacitor and the insulator for a gate or control electrode of a switching element. The steps of the method include forming a thin layer of silicon dioxide on a silicon substrate followed by a layer of first doped polysilicon and, optionally, a layer of silicon nitride and then a layer of photoresist. The layers are etched to the silicon dioxide surface with the exception of the portion of the layers overlying a region defined as the gate or control electrode of the switching element. A second layer of doped polysilicon is then deposited over the remaining structure to provide on the silicon dioxide layer a second conductive layer adjacent to but spaced from the first polysilicon layer forming the gate or control electrode. The silicon nitride, when used, is etched away and a strip of conductive metal is placed in contact with the first conductive polysilicon layer after the second doped polysilicon layer has been appropriately oxidized to form an insulating medium over this second polysilicon layer and between the first and second polysilicon layers. Any desired n+ regions may be formed in the silicon substrate by diffusing impurities into the substrate prior to forming the silicon dioxide layer, or the n+ regions may be formed after the silicon dioxide has been formed by using appropriate ion implantation techniques. By employing this method, high density one device memory arrays may be produced by using the first doped polysilicon layer for forming the gate electrode of a field effect transistor and the second doped polysilicon layer as an electrode of the storage capacitor.

Silicon-semiconductor-type thermal head

Abstract: A silicon-semiconductor type thermal head comprising a substrate of α-alumina ceramic of single crystalline sapphire a silicon layer of high electrical resistance formed on the upper surface of the substrate and exothermic dots of low electrical resistance silicon integrally formed on the high resistance silicon layer. The silicon semiconductor type thermal head is formed by forming a substrate of α-alumina ceramic of single crystalline and sapphire, forming a high resistance layer of silicon on the α-alumina ceramic, forming a layer of low resistance silicon on the high resistance layer of silicon and selectively etching the low and high resistance silicon layers to produce exothermic dots of low resistance silicon, separated from the substrate by high resistance silicon.

Germanium-containing silicon nitride film

Abstract: A germanium-containing silicon nitride film has a germanium content of 0.5 to 10 atomic-% that of the silicon content. Since the film has a much smaller stress than a conventional silicon nitride (Si3 N4) film, it is very suitable as a mask for fabricating a semiconductor device and an insulating or a protective film for a semiconductor device.

Radiation hardened drain-source protected mnos transistor

Abstract: A radiation hardened drain-source protected MNOS transistor is disclosed. A layer of silicon oxide overlies the channel and the junctions formed by the intersections of the drain and source regions with the channel. Drain and source protection is provided by relatively thick portions of the silicon oxide layer which overlie the junctions formed by the drain and source regions and the channel. The portion of the silicon oxide layer overlying the central section of the channel is thinner than the remainder of this layer. A silicon nitride layer and an electrically conductive layer forming the gate electrode overlie the thinner portion of the silicon oxide layer to complete the MNOS transistor. The conductive layer forming gate electrode of the transistor is in electrical contact with both the silicon nitride and the silicon oxide layers. This provides a convenient method for electrons generated at the interface of the silicon and the silicon-oxide layer during irradiation to be transported to the gate, thereby preventing charge build-up in the silicon oxide which causes shifts in the characteristics of the transistor.

Oxidation and epitaxy

Abstract: : The first order process models for silicon epitaxy and oxidation are described Epitaxial dopant inclusion, autodoping and transient effects are discussed, and experimental results are presented Silicon orientation, surface doping, and ambient effects are considered for silicon-oxidation rates (Author)

Ionization induced damage in crystalline silicon

Abstract: Close examination of the interaction of the energetic knock-on atoms with the local lattice environment reveals a damage mechanism which does satisfy the experimental data on proton irradiation of silicon. A proton-atom interaction with high energy transfer is considered where the proton path is delineated by a trail of ionization, and the silicon ion path is characterized by much heavier ionization terminating in a dense displacement cluster. At collision, many of the silicon electrons are stripped off, and the resulting energetic ion subsequently loses energy rapidly by Coulomb interaction with bound electrons. The rate of energy loss depends on the charge state and velocity of the knock-on ion. For ion energies in excess of 1 MeV, the intensity of ionization is sufficient to permit lattice atoms, stripped of their binding electrons, to reorient randomly before having an opportunity to recombine with electrons and re-establish the lattice. The path of a knock-on ion thus becomes a thin cylinder of amorphous material within the crystal. Amorphous silicon has a Fermi level closer to mid-band than does single crystal silicon, and a strong field therefore, results around this damaged region. The field produces a large depletion region, representing a very large capture cross section for minority carriers.