Showing papers on "Strained silicon published in 1978"

Method for making defect-free zone by laser-annealing of doped silicon

Abstract: This invention is a method for improving the electrical properties of silicon semiconductor material. The method comprises irradiating a selected surface layer of the semiconductor material with high-power laser pulses characterized by a special combination of wavelength, energy level, and duration. The combination effects melting of the layer without degrading electrical properties, such as minority-carrier diffusion length. The method is applicable to improving the electrical properties of n- and p-type silicon which is to be doped to form an electrical junction therein. Another important application of the method is the virtually complete removal of doping-induced defects from ion-implanted or diffusion-doped silicon substrates.

PROM electrically written by solid phase epitaxy

Abstract: A memory cell, having a doped amorphous silicon layer, is formed on a thin layer of silicon alloy which is on a single crystal silicon substrate. The cell is programmed by applying a voltage between a surface contact and the substrate to cause a crystal column to form in the amorphous layer between the substrate and the contact by solid-phase epitaxial growth. A diode is formed between the contact and the substrate by the selection of impurity levels and conductivity type of the amorphous layer and substrate and the selection of the silicon alloy. The cross-sectional area of the column is selectable to provide a multi storage level cell.

Negative-U States in the Gap in Hydrogenated Amorphous Silicon

Abstract: We propose that Si-H-Si three-center bonds exist in hydrogenated amorphous silicon. These centers give rise to states in the energy gap which have a negative effective electronic correlation energy, $U$. Our model can explain many of the known properties of this material. We make suggestions about how to obtain materials which may prove useful in electronic device applications.

Thermally grown silicon nitride films for high-performance MNS devices

Abstract: Amorphous and uniform silicon nitride films with thicknesses of less than 100 A have been thermally grown on silicon wafers by employing purified ammonia gas. The films are much denser than conventional CVD Si3N4 films. The MNS (metal‐thermal nitride‐silicon) structures have very low Nss in the order of 3×1010 cm−2 eV−1 and an effective electron mobility of larger than 800 cm2/V sec in the fabricated n‐channel MNSFFT.

Self-aligning double polycrystalline silicon etching process

Abstract: A process for fabricating a double layer polycrystalline silicon structure for a metal-oxide-semiconductor (MOS) integrated circuit. The upper polycrystalline silicon layer after being etched to form a predetermined pattern is used as a masking member for etching the lower polycrystalline silicon layer, thereby assuring alignment between the layers. A selective etchant which discriminates between the silicon layers is employed.

Method for producing a low defect layer of silicon-on-sapphire wafer

Abstract: A method is provided for producing a low-defect layer of silicon on a sapphire substrate. A silicon-on-sapphire (SOS) wafer is formed by initially epitaxially depositing silicon on the sapphire substrate to form a monocrystalline layer which is substantially free of lattice defects near its surface, but which exhibits a high defect density near the sapphire substrate. The wafer is subsequently subjected to an ion implantation to form an amorphous region in the silicon near the silicon-sapphire interface. The implanted ions are preferably "channeled" through the silicon layer to insure that the amorphous region will be localized in the imperfect region near the substrate, leaving the upper region of the silicon layer undamaged. During a subsequent high temperature anneal cycle, monocrystalline silicon is regrown from the residual upper regions of the silicon down to the silicon-sapphire interface, producing a silicon layer having a greatly reduced defect density throughout the layer.

Method of manufacturing a metal-insulator-semiconductor utilizing a multiple stage deposition of polycrystalline layers

Abstract: A method of making a metal-oxide-semiconductor device is disclosed. A thin silicon dioxide insulating layer is formed on the surface of a planar silicon wafer. A first layer of intrinsic polycrystalline silicon is deposited over the dioxide layer, and a second layer of doped polycrystalline silicon is deposited over the intrinsic layer, thereby forming the gate. Subsequent hot processing steps result in diffusion of a portion of the dopant from the doped polycrystalline layer into and throughout the intrinsic layer so as to dope the latter. A metal contact layer is then deposited onto the gate and in superimposed vertical alignment with respect to the thin silicon dioxide insulating layer. The instrinsic nature of the first polycrystalline layer reduces grain growth and void formation in the polycrystalline silicon and thereby prevents the silicon dioxide from being attacked by hydrofluoric acid seeping through voids in the polycrystalline layer during subsequent processing. The yield for the manufacture of devices having thin oxide gates is substantially improved.

CMOS SOS With narrow ring shaped P silicon gate common to both devices

Abstract: A layer of polycrystalline silicon is coated with a masking layer leaving at least one edge of the silicon layer exposed. A P-type dopant is diffused into the exposed edge of the silicon layer so that the dopant diffuses laterally along the silicon layer a desired distance. The masking layer is then removed and the undoped portion of the silicon layer is removed by an etchant which does not etch the doped portion of the silicon layer. This leaves the narrow strip of the doped silicon which can be used as the gate electrode of an MOS transistor and/or as an interconnection in an integrated circuit. Since the lateral diffusion of the dopant can be accurately controlled, narrow strips of the doped silicon can be achieved.

Method for forming semiconductor structure with improved isolation between two layers of polycrystalline silicon

Abstract: In a field effect device such as a charge coupled device or field effect transistor in which at least two levels of polycrystalline silicon conductors are used; these two levels of polycrystalline silicon are isolated from one another with a dielectric layer. Disclosed is a composite dielectric layer formed either by in situ oxidation of the first polycrystalline silicon layer plus chemical vapor deposited silicon dioxide or, in the alternative, the composite dielectric layer is formed by a phosphosilicate glass layer with thermal reoxidation of the first polycrystalline silicon layer.

A method for making a silicon mask and its utilisation

Abstract: 1. Method of making a silicon mask wherein on one surface of a wafer-shaped and planar silicon substrate (20) a thin silicon layer (22) is produced whose concentration of conductivity-determining impurities is higher than in the substrate (20), wherein recesses (28) are selectively etched into the surface of the substrate (20) opposite the silicon layer (22) of higher doping, and wherein from the surface of thin silicon layer (22) of higher doping, in accordance with the desired mask pattern, holes (14, 31) are selectively etched down to the recesses produced by the substrate etching, characterized in that prior to the etching of the mask pattern into the thin silicon layer (22) of higher doping the recesses (28) are produced with means which attacks silicon of low doping concentration quicker than highly doped silicon, the substrate material being etched fully through to the thin silicon layer (22) of higher doping.

Thermal migration-porous silicon technique for forming deep dielectric isolation

Abstract: A method for forming deep dielectric isolation regions of uniform porous silicon dioxide in silicon wafers having 100 face planes. Subcollector regions of one conductivity type are placed in a silicon substrate of opposite conductivity type. The substrate is covered by an epi layer of the opposite conductivity type. Isolation patterns of heavily doped impurity of the substrate conductivity type are thermally migrated along 110 and 110 crystallographic planes deeply and uniformly through the epi layer and into the substrate between the subcollector regions. The doped isolation patterns are converted to porous silicon by anodic treatment, and the porous silicon is converted into porous silicon dioxide by exposure to an appropriate oxidizing atmosphere.

Method of diffusing aluminum into silicon substrate for manufacturing semiconductor device

Abstract: An aluminum diffusion source layer is formed by vacuum evaporation on a major surface of a silicon substrate. The silicon substrate is heated to form an aluminum-silicon alloy layer, an aluminum doped silicon recrystallization layer and an aluminum diffusion layer. Thereafter, the aluminum-silicon alloy layer is removed from the major surface of the silicon substrate. Drive-in diffusion is performed so as to diffuse, aluminum included in the silicon recrystallization layer and the aluminum diffusion layer, into the silicon substrate. As a result, the aluminum diffusion concentration of 1016 -1019 atoms/cm3 can be obtained.

Processes for deposition of thin films of crystalline silicon on graphite

Abstract: Processes for the continuous deposition of crystalline silicon on graphite substrates, the silicon being undoped or N- or P-doped and the substrates being useful for photovoltaic cells and other electronic devices, the processes comprising placing crystalline silicon in at least one crucible having a capillary port with a vertical axis in its lower part; bringing the silicon to its melting point; bringing a graphite substrate into contact with the pendant drop formed at the lower mouth of the capillary; moving the substrate at a selected speed in a constant predetermined direction; and removing the substrate coated with the crystalline substance at chosen time intervals.

Vapor phase diffusion of aluminum with or without boron

Abstract: A method of fabricating a semiconductor device through selective diffusion of aluminum vapor into a silicon substrate by heating a sealed tube in which the silicon substrate and an aluminum source are disposed. The diffusion is effected with a low concentration of aluminum smaller than about 1017 atoms/cm3, thereby making it possible to use a silicon oxide film as a diffusion mask for the selective diffusion of aluminum at predetermined region of the silicon substrate.

Dopant diffusion method of making semiconductor products

Abstract: Arsenic or other dopant selected from Group III or Group V of the Periodic Table of Elements is diffused into a silicon substrate to form a semiconductor product having a buried region, such as a buried layer or channel, by providing the substrate with a layer of polycrystalline silicon doped with the selected dopant and heating the substrate and layer in an oxygen environment at a temperature and for a period of time sufficient to oxidize all or substantially all the polycrystalline silicon and simultaneously diffuse the dopant into the substrate. The substrate comprises single crystal silicon or other silicon form whose oxidation rate is comparable to or less than the polycrystalline silicon to permit complete oxidation of the polycrystalline silicon without excessive oxidation of the substrate.

Semiconductor device having a polycrystalline silicon diode

Abstract: A semiconductor device includes a substrate of one conductivity type and a polycrystalline silicon layer of the opposite conductivity type formed on a major surface of the substrate. A p-n junction establishing an effective diode is formed on the polycrystalline silicon layer as a result of the introduction of the impurities of the one conductivity type from the substrate into the polycrystalline silicon layer.

Silicon integrated circuit region containing implanted arsenic and germanium

Abstract: A method for forming N conductivity-type regions in a silicon substrate comprising ion implanting arsenic to form a region in said substrate having an arsenic atom concentration of at least 1 × 10 -2 As atoms/total atoms in substrate, and ion implanting germanium into said substrate region. Even though the atomic radius of arsenic is very close to that of silicon -- the arsenic radius is only 0.5% smaller -- when high arsenic atom concentrations of at least 1 × 10 -2 atoms/total atoms in the substrate are introduced in the substrate, and such high concentrations are only possible when arsenic is ion implanted, then atomic misfit dislocations will occur. The implanted germanium atoms compensate for the lattice strain in the silicon to minimize dislocations.

Layer of crystalline silicon having (111) orientation on (111) surface of lithium aluminum

Abstract: The formation of thin layers of crystalline silicon by heteroepitaxial growth on sodium thallium type substrates is known. The optimum system and orientation for producing such crystal growth has not previously been known. It is herein disclosed that the optimum system constitutes low strain heteroepitaxy of (111) silicon on (111) lithium aluminum between the reconstructed 7x7 surface of (111) silicon and a 6x6 array of aluminum atoms on the surface of the (111) lithium aluminum. The 7x7 reconstructed (111) silicon surface contains 36 silicon atoms and 13 vacancies for every 49 surface sites. The 36 silicon atoms on an area averaged basis match the 36 aluminum atoms in the 6x6 aluminum diamond structure (zero vacancies) present at the (111) surface of lithium aluminum to within about 1%. The composition as set out above is useful in solar cells for directly converting solar energy to electricity.

Barrier formation by glow-discharge induced centers on silicon surfaces

Abstract: Barrier formation of p-type silicon by sputtering of aluminium and titanium contacts are reported. A barrier height of 0.7 eV was found. A silicon wafer exposed to a r.f.-glow discharge during sputter-deposition is subjected to bombardment of neutral sputtered atoms, ions and electrons. This process will introduce charged centers at the surface of the silicon wafer. Such centers are shown to drastically change the properties of a Schottky-barrier, which is extremely surface-sensitive. The glow discharge bombardment of the surface will create donor-like states at the surface.

Method of making a planar semiconductor device.

Abstract: A semiconductor device (10) includes a region (32) of polycrystalline silicon on a portion of the surface (13) of a body (12) of semiconductor material. A layer (26) of oxidized polycrystalline silicon is also on the semiconductor material body and extends to the polycrystalline silicon region. The surface of the silicon oxide layer is substantially coplanar with the surface of the polycrystalline silicon region so that a metal film conductor (28) can be easily provided over the semiconductor device. The polycrystalline silicon region may be the gate of an MOS transistor or a conductive region of any type of semiconductor device. The semiconductor device is made by forming a polycrystalline silicon layer over the semiconductor material body, forming a mask on a portion of the polycrystalline silicon layer, reducing the thickness of the unmasked portion of the polycrystalline silicon layer and then oxidizing the unmasked portion of the polycrystalline silicon layer to form the oxide layer. In MOS transistors, both the contacts and gate of the device can be formed from one polycrystalline silicon layer by appropriate masking, thinning, and oxidizing steps.

Crystalline anodic silicon dioxide on silicon

Abstract: Multi-layer oxide film grows in anodic oxidation of silicon p-type in 0.1 N water diluted hydrofluoric acid. The inner layer of the oxide film on the silicon monocrystal substrate is of α-quartz, while the outer layer of the oxide film to the electrolyte interface is amorphous. By electron diffraction in transmission a orientation, [00.1], of α-quartz layer on the silicon [111] surface is identified. It is supposed that such structure of the oxide film is a result of existing high electric fields on the silicon anode surface in suitable electrolyte and that strong nonequilibrium condition of oxidation are possible. [Russian Text Ignored]

The Haynes-Shockley Experiment with Silicon Planar Structures

Abstract: A Haynes-Shockley experiment is described which is performed on silicon planar structures instead of on the usual germanium filaments. The drift field is realized by planar ohmic contacts, which are properly positioned to ensure a homogeneous field in the measuring area. The structures have been thoroughly tested, and the measurements yield the expected minority carrier drift mobility and lifetime. The silicon structures relieve the student of the laborious preparation of the normally used germanium filaments.