Showing papers on "Strained silicon published in 1979"

A silicon heterojunction transistor

Abstract: SIPOS (Semi‐insulating polycrystalline silicon) which is used as a surface passivation layer for highly reliable silicon devices constitutes a good heterojunction for silicon. P‐ or B‐doped SIPOS has been used as the emitter material of a heterojunction transistor with the base and collector of silicon. An npn SIPOS‐Si heterojunction transistor showing 50 times the current gain of an npn silicon homojunction transistor has been realized by high‐temperature treatments in nitrogen and low‐temperature annealing in hydrogen or forming gas.

Method for making single electrode U-MOSFET random access memory utilizing reactive ion etching and polycrystalline deposition

Abstract: A method for making highly dense, dielectrically isolated, U-shaped MOSFET. In a preferred method a monocrystalline silicon P substrate with a N+ layer thereon, a P layer on the N+ layer and a N+ layer on the P layer is provided. A pattern of U-shaped openings is formed in the body through to the P substrate by the reactively ion etching technique. This pattern of openings is filled with an insulator material, such as silicon dioxide. A conductive layer of N+ doped polycrystalline silicon is deposited on the bare surface of this silicon body. Openings are formed in the polycrystalline silicon over the silicon dioxide filled openings. A silicon dioxide layer is then grown by, for example, thermal oxidation over the polycrystalline silicon layer. Reactively ion etching is used to produce substantially U-shaped openings through the layers over the P substrate and into the P substrate to substantially bisect the regions of monocrystalline silicon. This etching step forms two storage cells in the monocrystalline silicon areas and a bit line for each column of cells in the polycrystalline silicon layer. A silicon dioxide gate insulator is grownon the monocrystalline silicon surfaces of the U-shaped openings by thermal oxidation in a suitable ambient. Conductively doped polycrystalline silicon is deposited in the U-shaped openings over the silicon dioxide gate insulator layer until the openings are filled and cover the surface of the body. The conductively doped polycrystalline silicon on the surface of the body is etched in a suitable pattern to produce the word lines of the random access memory device.

Process for producing a semiconductor device including an ion implantation step in combination with direct thermal nitridation of the silicon substrate

Abstract: Impurity ions implanted into a semiconductor silicon substrate are not redistributed during a heating of the substrate from the substrate to the film. Such redistribution does not occur due to the direct nitridation of the silicon substrate for forming the silicon nitride film.

Method of fabricating an SOS island edge passivation structure

Abstract: A silicon-on-sapphire semiconductor structure, and method of fabricating such structure, in which a silicon nitride layer is provided over the oxide layer. The silicon nitride layer is disposed over the upper edge of the silicon island, and acts to prevent gate oxide breakdown.

Josephson tunnel junction with polycrystalline silicon, germanium or silicon-germanium alloy tunneling barrier

Abstract: A Josephson tunnel junction device having niobium nitride superconductive electrodes includes a polycrystalline semiconductor tunnelling barrier therebetween comprised of silicon, germanium or an alloy thereof preferably deposited on the lower superconductive electrodes by chemical vapor deposition. The barrier height of the junction is precisely controlled by precision doping of the semiconductor material.

Method for fabricating a semiconductor device by controlled diffusion between adjacent layers

Abstract: A method for fabricating a semiconductor device is disclosed, which comprises forming a first polycrystalline silicon film containing an impurity such as phosphorus or boron on the surface of a silicon oxide film, forming an impurity-free second polycrystalline silicon film contiguous to the first polycrystalline silicon film, diffusing the impurity contained in the first polycrystalline silicon film into the second polycrystalline silicon film to form an impurity-containing region, and oxidizing the impurity-containing region to electrically separate the first and second polycrystalline silicon films from each other by the resulting oxide.

Laser‐annealing behavior of a phosphorus‐implanted silicon substrate covered with a SiO2 film

Abstract: Laser‐annealing behavior of phosphorus‐implanted silicon substrates is investigated as a function of the SiO2 film thickness formed on implanted surfaces. Surface‐carrier concentration after laser irradiation through the SiO2 layers shows periodic enhancement in relation to SiO2 thickness. Calculation of laser energy transferred into the silicon surface through various SiO2 film thicknesses is carried out and the results agree well with the experiments.

Cold substrate growth technique for silicon-on-ceramic

Abstract: The present invention is an improvement to the method of growing silicon films on a substrate by bringing the substrate in contact with molten silicon. The improved growth technique may be classified as an asymmetric mode of growth of silicon on the substrate and is characterized by the substrate being maintained at a lower temperature than the solidification of silicon in the area of the substrate where the silicon layer growth is taking place, that is in the area of the liquid-solid interface. The lower temperature of the substrate, say 5°-10° C. below the freezing temperature of silicon, causes the liquid-solid interface to be tilted to be nearly parallel to the substrate surface but inclined at a reentrant angle, so that the leading edge of the crystallization front is on the substrate. This provides an advantage of increased growth speed.

Method for fabricating a field effect transistor

Abstract: A field effect transistor is fabricated by forming a silicon dioxide film having a region where said silicon dioxide film becomes thinner at that area on one surface of a silicon semiconductor substrate of a first conductivity type at which the field effect transistor is to be formed. On said silicon dioxide film there is deposited a polycrystalline silicon layer which has an impurity concentration higher than that of the silicon semiconductor substrate. The polycrystalline silicon layer is removed by selective etching so as to leave only a part which becomes a gate of the field effect transistor. A surface part of the silicon dioxide film over the entire area is removed by employing as a mask the part of the polycrystalline silicon layer to become the gate and to the extent that the surface of the silicon semiconductor substrate is exposed at the other part in the region, a silicon dioxide film is grown by thermally oxidizing the whole surface of the polycrystalline silicon layer to become the gate and the exposed surface of the semiconductor substrate, the silicon dioxide film produced at the surface of the polycrystalline silicon layer being thicker than the silicon dioxide film produced at the exposed surface of the semiconductor substrate. Windows for a source and drain are formed by removing the silicon dioxide films over the entire area by such thickness that the surface of the silicon semiconductor substrate is exposed at the part in the region other than the part covered by the polycrystalline silicon layer to become the gate, but so that the polycrystalline silicon layer is not exposed; the source and the drain are formed by doping surface portions of the semiconductor substrate with an impurity of a second conductivity type opposite to the first conductivity type through the windows formed by the preceding step; removing a part of the silicon dioxide film is removed by selective etching so as to expose a part of the polycrystalline silicon layer. An electric conductor is deposited over the entire area, and finally the electric conductor is formed into a predetermined pattern by selective etching so as to obtain source, gate and drain electrodes.

Method for manufacturing semiconductor memory devices

Abstract: A method for producing semiconductor memory devices each including an MNOS-type transistor and an MNOS-type capacitor or an MOS-type transistor and an MNOS-type capacitor. A thick oxide layer is formed in predetermined patterns on the surface of the substrate so as to separate the memory cell areas. The surface of the wafer is then oxidized to form a thin oxide layer on which a layer of silicon nitride is deposited and over which a layer of polycrystalline silicon is formed. Portions of the layer of silicon nitride and layer of polycrystalline silicon are etched away in preferred patterns as are second portions of the layer of polycrystalline silicon to partially expose the layer of silicon nitride. Portions of the thin oxide layer are removed in areas where the second portions of the layer of polycrystalline silicon are etched away to thereby expose a first portion of the surface of the wafer. Following the diffusion of impurities into the wafer, a layer of thermal oxide is formed. Next, portions of the silicon nitride layer and the thin oxide layer are etched away to expose a second portion of the surface of the wafer. The wafer is again thermally oxidized to form a thin oxide film on the second portion of the surface through which contact holes are subsequently formed. A conductive interconnection pattern is then formed extending into the contact holes.

Integrated circuit structures with full dielectric isolation and a novel method for fabrication thereof

Abstract: Structure: An integrated circuit structure with full dielectric isolation comprising a supporting substrate having a planar surface of dielectric material and a semiconductor layer on said dielectric surface which forms a planar interface with the surface. Regions of oxidized silicon extend through the layer from said interface, surrounding and dielectrically isolating pockets of silicon in the layer; the oxidized silicon regions extend to the upper surface of the semiconductor layer where they are substantially co-planar with the silicon pockets. The devices of the integrated circuit are formed in said silicon pockets. Method: The structure is fabricated by a novel method wherein a lightly doped silicon layer is deposited on a highly doped silicon substrate; surrounding oxidized silicon regions are then formed by selectively thermally oxidizing portions of the silicon layer to form oxide regions which are co-extensive with the oxidized areas and, thus, are co-planar with the remaining silicon pockets at both surfaces of the layer; a member having a dielectric surface interfacing with the silicon layer is formed, and the silicon substrate is removed by preferential electrochemical anodic etching to leave the silicon layer having the oxidized regions surrounding spaced silicon pockets mounted on said member.

High frequency sputtering produces thin film amorphous silicon photoconductor

Abstract: In the course of producing a thin film of amorphous silicon by high frequency sputtering elemental silicon under an atmosphere containing at least hydrogen gas, the temperature of the base plate onto which the amorphous silicon is deposited is maintained at a temperature of about 50° C. to 150° C. The thus obtained silicon film possesses not only photoconductivity sufficient for use as a photoconductor but also a large difference between photoconductivity and dard conductivity. In addition, a photoconductor of an amorphous silicon thin film can be produced at low cost without environmental pollution problems.

The Influence of Noble Gas Atoms on the Epitaxial Growth of Implanted and Sputtered Amorphous Silicon

Abstract: We compared the epitaxital regrowth of amorphous silicon which had been implanted with Ne, Ar, or Kr at annealing temperatures below 600°C. The aim was to determine if silicon sputtered on single crystal silicon with an appropriate sputtering gas could grow epitaxially. We showed that this process is not possible because of the high concentration of gas included in sputtered films. We evaluated the maximum concentration of Ne, Ar, and Kr in silicon, above which the amorphous layer does not regrow epitaxially.

Planar epitaxial refill using liquid phase epitaxy

Abstract: Planar silicon device structures are fabricated by refilling grooves etched in an oxide-coated silicon substrate using liquid phase epitaxial growth from a tin melt. Since tin does not wet silicon dioxide, silicon nucleation on the oxide-covered areas of the substrate is precluded. Consequently, epitaxial growth selectively occurs in the grooves, without undesirable silicon growth over the oxide. This avoids the short-circuits and surface nonplanarity resulting from the growth of polycrystalline silicon on the oxide layer covering the unetched areas when vapor phase epitaxial growth is employed.

Growth technique for silicon-on-ceramic

Abstract: The present invention is an improvement to the method of growing silicon films on a substrate by bringing the substrate in contact with molten silicon. The improved growth technique may be classified as an asymmetric mode of growth of silicon on the substrate and is characterized by the substrate being maintained at a higher temperature than the solidification of silicon in the area of the substrate where the silicon layer growth is taking place, that is in the area of the liquid-solid interface. The higher temperature of the substrate causes the liquid-solid interface to be tilted to be nearly parallel to the substrate surface but inclined at a reentrant angle, so that the leading edge of the crystallization front is away from the substrate. This provides several advantages including increased growth speed, a nonhomogeneous doping of the silicon layer, that is an impurity concentration gradient and results in a high-low junction at the back surface and gives the back surface field effect.

Method of manufacturing a semiconductor device using different etch rates

Abstract: A method of manufacturing a semiconductor device is disclosed in which a surface of a silicon body is provided successively with a silicon oxide layer and silicon nitride layer. Parts of the surface are exposed and are subjected to an oxidation treatment so as to obtain a sunken oxide pattern, during which treatment an undesired small silicon nitride strip or "white ribbon" is formed, and remaining parts of the silicon nitride layer and the underlying silicon oxide layer are then etched away. In the etching treatment, silicon nitride is etched more rapidly than silicon oxide and silicon, while silicon nitride is etched at approximately the same rate as silicon, so that the undesired "white ribbon" is removed.

Laser annealing of indium-implanted silicon

Abstract: A single pulse from a ruby laser is shown to cause significant regrowth in the amorphous region of indium-implanted silicon. RBS measurements demonstrated that compared to thermal annealing, there is no loss of indium atoms from (111) silicon substrates, and at the same time, approximately 60% of implanted atoms occupy regular lattice positions in the crystal. There has been noticeable redistribution of the indium atoms, causing maximum concentration at the surface.

A Germanium Field-Effect Transistors Made from a High-Purity Substrate

Abstract: Field effect transistors have been fabricated on high-purity germanium substrates using low temperature technology. The aim of this work is to preserve the low density of trapping centers in high-quality starting material by low temperature (<350°C) processing. The use of germanium promises to eliminate some of the traps which cause generation-recombination noise in silicon field effect transistors (FET's) at low temperatures. Typically, the transconductance (gm) in the germanium FET's is 10 mA/V and the gate leakage can be less than 10-12 A. Our present devices exhibit a large 1/f noise component and most of this noise must be eliminated if they are to be competitive with silicon FET's commonly used in high-resolution nuclear spectrometers.

Highly insulating silicon nitride films

Abstract: Highly insulating silicon nitride films are obtained when the nitride is deposited on silicon wafers coated with tungsten. Current conduction in these films follows a high power law of the form I ∝ Vn with values of n greater than 10, as compared to silicon nitride films deposited on silicon which give log I — V1/2 behaviour. G- V curves and infra-rod absorption measurements indicate that in the tungsten-coated samples, either the tungsten layer has disappeared during the deposition process and has been incorporated in the nitride and ’ doped ’ it in the process, or the tungsten-layer might be in the island (three-dimensional growth) form which may transmit in the infra-red.