Showing papers on "Strained silicon published in 1981"

A new dielectric isolation method using porous silicon

Abstract: A new dielectric isolation technology is proposed. In the new structure, single crystalline Si islands are separated from the silicon substrate by oxidized porous silicon. It is based on the following characteristics of the porous silicon oxide formation: (1) p -type Si is more easily changed to porous silicon than n -type Si; (2) porous silicon is formed along the anodic reaction current flow line; (3) the change in volume of porous silicon after oxidation is relatively small; (4) thick porous silicon films (10 μm) can be obtained easily. In this method, a p -type isolated layer is obtained by proton implantation used for an n -type layer formation. Lateral p - n junctions fabricated in such isolated silicon layers show lower leakage current than those reported in SOS technology.

Optical Properties of Heavily Doped Silicon between 1.5 and 4.1 eV

Abstract: The optical constants of heavily doped silicon are determined between 1.5 and 4.1 eV with use of polarization modulation ellipsometry. For photon energies less than 3.4 eV it is found that there is a substantial increase in the optical absorption coefficient for As-doped silicon, but a much smaller increase for B-doped or P-doped silicon. It is believed that this is due to $d$-electron admixture into the conduction band when the dopant is As.

The electronic properties of silicon nitride

Abstract: The nature of bonding in silicon nitride is treated using simple bond-orbital models. A nitrogen pπ lone-pair valence band maximum is found. This is due to the planar nitrogen site, which is in turn due to the repulsions between non-bonded second-neighbour silicon atoms. The conduction minimum is found to have a relatively low effective mass and be formed of Si 3s states. The density of states (DOS) for β-Si3N4 is calculated for two Si–N–Si bond angles, 120° and 107°. The DOS at the former angle, which corresponds to a planar nitrogen, shows an upper pπ valence band which has merged into the lower bonding bands at 107°. The effects of non-bonded silicon–silicon repulsions on the planarity of the nitrogen site and likely structure of amorphous silicon nitride are discussed. Unlike vitreous SiO2, commercial silicon nitride contains an appreciable proportion of impurities which may determine electronic transport and low-energy optical properties. The local electronic structure of ≡Si–Si, ≡Si–H, =N–H...

Electron spin resonance in discharge-produced silicon nitride

Abstract: ESR signal from the defects in plasma-deposited silicon nitride has been observed, for the first time. The g-value (2.0055) is identical with that of silicon dangling bonds in amorphous Si:H, and the linewidth (14.5 G) is two times as large as that of amorphous Si:H for spin densities below 1018 cm-3, above which narrowing of the linewidth takes place as in the case of amorphous Si:H. It is suggested that most of dangling bonds of nitrogen atoms in the silicon nitride are passivated by bonded-hydrogen and silicon dangling bonds are mainly responsible for the ESR signal. A correlation between the spin density and leakage current through the film is also discussed.

Silicon nitride S/D ion implant mask in CMOS device fabrication

Abstract: A coplanar CMOS process for fabricating self-aligned gate FETs utilizing high energy, high dose rate ion implants to form the S/D regions In the course of coplanar processing, the gate electrodes and S/D regions are defined Selectively prescribed thicknesses of silicon dioxide are then formed over the top and sidewalls of the gate electrodes, as well as the exposed substrate in the S/D regions Thereafter, a first, silicon nitride layer of controlled thickness is evenly deposited, and is followed by a dry etch step to expose the thin layer of silicon dioxide covering the p-channel FET S/D regions The temperature stability of silicon nitride protects the n-channel FETs from the effects of the high energy levels and currents associated with the ion implant step used to form the S/D regions of the p-channel FETs In contrast, the implant ions readily penetrate the thin oxides over the S/D regions of the p-channel FETs Thereafter, a second, silicon nitride layer of controlled thickness is deposited Again, it is followed by a dry etch step, but now to expose the silicon dioxide covering the n-channel FET S/D regions The succeeding n-channel S/D implant similarly penetrates the silicon dioxide coverings, while the silicon nitride serves as a barrier for the remaining substrate surface After S/D implanting is completed, a highly preferential etchant is used to remove the remaining silicon nitride, while the areas protected by the relatively thin layers of silicon dioxide are substantially unaffected

Process for the manufacture of vertical P-N junctions in the pulling of silicon from a silicon melt

Abstract: The invention makes it possible to manufacture silicon wafers having vertical p-n junctions as the basic material for solar cells. As a result of simultaneously adding certain dopants that act in the silicon crystal as donors and certain dopants that develop acceptor properties and also as a result of measures that result in a periodic change in the crystal growth from a low rate v n to a high rate v n , p- and n-conductive zones are produced in the silicon, each having a total length of from 5 to 2000 μm.

Method of forming polycrystalline silicon lines and vias on a silicon substrate

Abstract: The method involves the formation of conductive, polycrystalline silicon lines and vias by the conversion of amorphous silicon in contact with the underlying silicon substrate through the use of a laser annealing process.

Process for fabricating a logic structure utilizing polycrystalline silicon Schottky diodes

Abstract: An integrated circuit structure and process for fabricating it are described which allow fabrication of a very compact high-speed logic gate. The structure utilizes a bipolar transistor formed in an epitaxial silicon pocket surrounded by silicon dioxide. A pair of Schottky diodes and a resistor are formed outside the epitaxial pocket on the silicon dioxide and connected to the pocket by doped polycrystalline silicon.

MOSFET Structure and process to form micrometer long source/drain spacing

Abstract: A method for fabricating a semiconductor integrated circuit structure having sub-micrometer gate length field effect transistor devices is described wherein a surface isolation pattern is formed in a semiconductor substrate which isolates regions of the semiconductor within the substrate from one another. Certain of these semiconductor regions are designated to contain field effect transistor devices. A first insulating layer such as silicon dioxide which is designated to be in part the gate dielectric layer of the field effect transistor devices is formed over the isolation pattern surface. Then a conductive layer, a second silicon dioxide layer, a first silicon nitride layer, a polycrystalline silicon layer and a second nitride layer are formed thereover. The multilayer structure is etched to result in a patterned polycrystalline silicon layer having substantially vertical sidewalls some of which sidewalls extend across certain of the device regions. A well controlled sub-micrometer thickness layer is formed on these vertical sidewalls by thermal oxidation of the polycrystalline silicon surfaces. The patterned layer is then removed which leaves the pattern of sub-micrometer thickness silicon dioxide sidewall layer portions of which extend across certain of the device regions. The sidewall layer is utilized as a mask in etching the first silicon nitride layer, the second silicon dioxide layer and the conductive layer to form the gate electrode of the field effect transistor devices in the conductive layer having the length of the sidewall coating. Ion implantation is then accomplished adjacent to the gate electrode to form the desired source/drain element for the field effect devices in the device regions. The conductive layer and resulting gate electrode may be composed of polycrystalline silicon metal silicide, polycide (a combination of layers of polycrystalline silicon and metal silicide) or the like.

Method of forming doped polycrystalline silicon pattern by selective implantation and plasma etching of undoped regions

Abstract: A process of forming a polycrystalline silicon pattern which is used for a semiconductor device, wherein the degree of side etching is low and the obtained pattern is of high precision. Firstly, a polycrystalline silicon layer is deposited on a semiconductor substrate or on an insulating film which is formed on a semiconductor substrate. An impurity is selectively ion-implanted with high concentration into the region in the layer which is to remain as a polycrystalline silicon pattern. Finally, whole of the polycrystalline silicon layer into which the impurity is thus selectively ion-implanted is plasma-etched to etch off the areas into which the impurity is not ion-implanted.

Fabrication method for high conductivity, void-free polysilicon-silicide integrated circuit electrodes

Abstract: A method of providing self-passivating interconnection electrodes for semiconductor devices which provides low resistivity composite polysiliconsilicide electrodes. In the method the formation of oxidation induced voids in polysilicon underlying the silicide is eliminated by deposition of polysilicon and stoichiometric proportions of silicon and a silicide-forming metal. These steps are followed by deposition of a silicon layer having a thickness determined to provide between 30 and 100 percent of the silicon required to form a silicon dioxide passivation layer. Subsequent thermal oxidation of the layered electrode structure provides a self-passivated structure useful for fabrication of silicon gate MOSFET devices as well as other integrated circuit structures.

Method of fabricating a highly conductive structure

Abstract: An improved method of fabricating a silicide structure includes depositing a metal, e.g., molybdenum or tungsten, directly onto a thin insulating layer of silicon dioxide and/or silicon nitride formed on a semiconductor substrate, co-depositing the metal and silicon onto the metal layer and then depositing silicon onto the co-deposited metal-silicon layer. This structure is annealed at a temperature sufficient to form a metal silicide between the thin insulating layer and the layer of silicon. The silicon layer serves as a source of silicon for the metal layer which is consumed during the annealing step to form, along with the co-deposited metal-silicon layer, a relatively thick metal silicide layer directly on the thin silicon dioxide layer. A sufficiently thick silicon layer is initially provided on the co-deposited metal-silicon layer so that a portion of the initial silicon layer remains after the annealing step has been completed. This excess silicon may be oxidized to form a passivating layer on top of the thick metal silicide layer. If all or a part of the silicon in the remaining silicon layer after annealing is removed, the thick metal silicide layer may be exposed to an oxidizing ambient for self-passivation. In this latter instance, the pure metal precipitates in the silicide resulting in a line with even greater conductivity than a pure silicide line, which is very desirable for interconnections.

Method of making Schottky barrier diode by selective beam-crystallized polycrystalline/amorphous layer

Abstract: Generally, a complicated process is required in manufacturing a semiconductor device containing a Schottky barrier diode and a polycrystalline silicon layer which prevents excessive reaction of the aluminum electrode and silicon material involved. Because of the inability of the aluminum electrode to provide a good Schottky barrier by its contact with the polycrystalline silicon layer, it is required to directly contact the electrode with a monocrystalline silicon semiconductor layer or substrate. According to the present invention, this process is simplified by monocrystallizing the polycrystalline silicon layer at least in the region in which a Schottky barrier diode is to be formed by annealing the silicon layer in said region by laser beam irradiation and applying an aluminum electrode thereto.

Solar cell structure incorporating a novel single crystal silicon material

Abstract: A novel hydrogen rich single crystal silicon material having a band gap energy greater than 1.1 eV can be fabricated by forming an amorphous region of graded crystallinity in a body of single crystalline silicon and thereafter contacting the region with atomic hydrogen followed by pulsed laser annealing at a sufficient power and for a sufficient duration to recrystallize the region into single crystal silicon without out-gassing the hydrogen. The new material can be used to fabricate semiconductor devices such as single crystal silicon solar cells with surface window regions having a greater band gap energy than that of single crystal silicon without hydrogen.

Low energy electron loss spectroscopy of Si–Ge interfaces

Abstract: We present energy loss spectra of Si–Ge heterojunctions. The early stage of formation of the interface has been studied by successive evaporations of small amounts of germanium on a silicon substrate heated at 350 °C. The results, compared with theoretical calculations, show that the interface is abrupt on a microscope scale and that germanium induces extrinsic interface states in the main and partial gaps of the projected bulk band structure of silicon on the (111) surface.

Method of manufacture of a pin amorphous silicon semi-conductor device

Abstract: An amorphous silicon PIN semi-conductor device is manufactured by (i) providing a substrate (10) with a layer (11) of an electroconductive material, for example molybdenum, which forms an ohmic contact with N+ amorphous silicon; (ii) sequentially sputtering a layer of N + doped amorphous silicon (12), a layer of intrinsic, I, amorphous silicon (14) and a layer of P + doped amorphous silicon (16). A layer (18) of an electroconductive material, for example semi-transparent indium tin oxide, is sputtered into layer (16) to form an ohmic contact therewith. A grid current- collection electrode (20) is optimally patterned on layer (18). The sputtering step parameters are controlled, and the steps can be performed in a single vacuum system and vacuum pump-down procedure. The semi-transparent layer (18) can thus be depointed on a thin P+ doped layer (16) without deterioration of the junction forming characteristics of the underlying amorphous silicon layers.

Discharging process by multiple tunnelings in MNOS structures

Abstract: Discharging process by multiple tunnelings is proposed and studied theoretically in thin-oxide MNOS structures. Traps at the silicon dioxide-silicon nitride interface and in silicon nitride layer are taken into account. Three tunneling processes are considered in the analysis. Those are (i) from the interface to silicon conduction band, (ii) from the silicon nitride layer to silicon conduction band, and (iii) from the silicon nitride layer to the interface (and then to silicon conduction band). From the analysis of these tunneling processes, physical interpretation for the maximum tunneling distance is derived.

Manufacture of micro-cantilever onto silicon wafer

Abstract: PURPOSE:To form the micro-cantilever, which has a metallic specular surface conducting switching operation and is made of silicon oxide, by using a silicon oxide layer in place of a conventional P layer and employing a polycrystal silicon layer shaped through a CVD method, etc. in place of a silicon layer. CONSTITUTION:A silicon wafer 11 mirror-ground is oxidized, and the silicon oxide layer 12 with approximately 1mum thickness is formed onto the wafer. The polycrystal silicon layer 13 is shaped onto the surface of the layer 12 by approximately 20mum thickness through the CVD method, etc., the surface is mirror-ground, and the polycrystal silicon layer 13 is changed into the polycrystal silicon layer with approximately 10mum thickness. A silicon oxide layer 14 with approximately 1mum thickness and a metallic thin-film 15 are shaped onto the surface of the polycrystal silicon layer 13 in succession. The silicon oxide layer 14 is romoved in concave form, and opening sections 16 are moded. The polycrystal silicon layer 13 is chemically etched. The silicon oxide layer 14 of a section surrounded by the opening sections 16 is used as the micro-cantilever 17.

Three level poly dynamic ram with poly bit lines

Abstract: First polycrystalline silicon layers are insulatively disposed over a p-type semiconductor substrate. Second polycrystalline silicon layers are formed on the substrate adjacent to the first polycrystalline silicon layers. Third polycrystalline silicon layers are insulatively disposed over the substrate between the first polycrystalline silicon layers and the second polycrystalline silicon layers. The third polycrystalline silicon layers function as gates of MOS transistors, and the first polycrystalline silicon layers function as capacitors in cooperation with the substrate. The second polycrystalline silicon layers function as the digit lines, and are so formed as to alternately contact substrate and pass over the first polycrystalline silicon layers insulated therefrom by thick insulative layers.

Silicon-based semiconductor devices

Abstract: of the Disclosure A new silicon based semiconductor device comprises a layer of amorphous silicon in which the density of energy states in the energy gap has been reduced by hydrogenation; this layer is associated with a layer of a hydrogen-containing substrate material that can supply hydrogen in atomic form to the amorphous silicon. In processes of the invention the silicon layer and a substrate layer are hydrogenated separately to permit optimum hydrogenation; the silicon layer may be deposited without hydrogenation and hydrogenated subsequently with hydrogen from the substrate material. A specific example consists of a layer of hydrogenated amorphous silicon of about 1 micrometer thickness deposited on a hydrogen-containing chromium layer which is itself deposited on a carrier, the silicon then forming the active element of a photovoltaic cell particularly functional as a solar cell.

Method for making an electrical contact to a silicon substrate through a relatively thin layer of silicon dioxide on the surface of the substrate and method for making a field effect transistor

Abstract: A buried electrical contact is made to a substrate (10) of monocrystalline silicon through a relatively thin layer (21) of silicon dioxide witout causing damage to the relatively thin layer (21) of silicon dioxide. This is accomplished through depositing a thin layer (22) of polycrystalline silicon over the relatively thin layer (21) of silicon dioxide prior to forming the opening (26) in the relatively thin layer (21) of silicon dioxide for the electrical contact to the substrate. After the thin layer (22) of polycrystalline silicon is deposited, an opening (25) is formed therein so that the thin layer (22) of polycrystalline silicon functions as a mask to etch a corresponding opening (26) in the relatively thin layer (21) of silicon dioxide. Then, a layer (28) of polycrystalline silicon is deposited over the - exposed surface (27) of the substrate (10) and the thin layer (22) of polycrystalline silicon to form the electrical contact through the opening (26) in the relatively thin layer (21) of silicon dioxide to the substrate.

Method for making a polysilicon conductor structure

Abstract: A method is described for eliminating abnormalities in a polycrystalline silicon integrated circuit structure, such as a silicon gate field effect transistor structure. The layer (30, 40) of polysilicon is deposited on an insulator coating (24, 38) which may be the thickness of the gate dielectric. The polycrystalline silicon is delineated by lithographic techniques and a reactive ion etching process to form the desired conductor structure. A thickness of the polycrystalline silicon of the order of tens of nanometers is left upon the insulator coating (24) where the masking layer has openings. This thin coating of polycrystalline silicon is then thermally oxidized together with the exposed sidewall of the polycrystalline silicon in the areas under the opaque parts of the masking layer to form silicon dioxide on the sidewall of the polycrystalline silicon structures. A directional reactive ion etching of the silicon dioxide removes all silicon dioxide formed by the thermal oxidation step from the horizontal silicon substrate while leaving the silicon dioxide on the vertical sidewall regions. The method prevents the formation of a poor grade of silicon dioxide under the edges of the polycrystalline silicon conductor structure.

Method for forming a self-aligned contact and a plasma especially applicable in performing said method

Abstract: The method is applied after the contact region (27a) has been covered by a silicon nitride oxidation blocking mask (28a) which subsequently was subjected to oxidation and/or doping processes causing the formation of various compounds in the silicon nitride (28a) and at the interface between the silicon nitride (28a) and the contact region (27a). A non-selective etching process is used to remove silicon nitride (28a) and the formed compounds. In particular it has been found that a plasma comprising a organo-halide and an excess of oxygen can be used to non-selectively etch the silicon dioxide, the silicon nitride, its associated compounds and the material of the contact region, like polysilicon. The method is useful e.g. for the formation of the polysilicon gate of a silicon field effect transistor.

Process of forming a polycrystalline silicon pattern

Abstract: A process of forming a polycrystalline silicon pattern which is used for a semiconductor device, wherein the degree of side etching is low and the obtained pattern is of high precision. Firstly, a polycrystalline silicon layer is deposited on a semiconductor substrate or on an insulating film (11) which is formed on a semiconductor substrate. An impurity is selectively ion-implanted with high concentration into the region (12') in the layer (12) which is to remain as a polycrystalline silicon pattern. Finally, whole of the polycrystalline silicon layer (11) into which the impurity is thus selectively ion-implanted is plasma-etched to etch off the areas into which the impurity is not ion-implanted.

Very High Charge Densities in Silicon Nitride Films on Silicon for Inversion Layer Solar Cells

Abstract: Different ways of achieving high positive charge densities in Si nitride films on Si for the creation of low resistivity inversion layers for solar cells are demonstrated: (i) optimization of the deposition parameters, (ii) utilizing the Si nitride charge storage effect and (iii) sodium incorporation into the nitride films. Both APCVD and PECVD Si nitride films were investigated. It was shown for the first time, that sodium can be obtained in a positively charged state in Si nitride, and, in contrast to CVD SiO2, the C-V curves were not distorted and only very small hysteresis was found after the sodium treatment. Very high charge densities up to 1.4x1013 cm-2 with stability at elevated temperatures could be achieved.

Solution Growth Of Thallium-Doped Silicon For 3-5 Micrometer Photoconductive Detectors

Abstract: A method for growth of single-crystal silicon doped heavily, with thallium has been developed to make use of the good match of the thallium acceptor cutoff wavelength (5.0μ) to the 3-5μ atmospheric window. The method involves recrystallization of silicon from a tin-thallium solution kept saturated by a silicon source wafer. Growth conditions used success fully to date range from 1100°C to 1370°C in growth temperature, and from 7% to 50% tin fraction in the tin-thallium solvent. The thallium doping increases monotonically with increas, ing growth temperature or thallium fraction in the solvent. A model of the dependence of the thallium doping on temperature and solvent composition is presented, as well as the estimated solubility limit of thallium in silicon. The most heavily doped crystal was grown at 1370°C from a Sn.14T1.86 solvent, and produced a maximum photoionization absorption of 2cm-1 at 3μ. This corresponds to a predicted quantum efficiency of 18% in a 1-mm thick detector. The Hall mobility of the grown material near liquid nitrogen temperature is found to approach 2000cm2/V-sec.