Showing papers on "Strained silicon published in 1987"

Gettering of gold in silicon: A tool for understanding the properties of silicon interstitials

Abstract: The movement of gold in silicon is controlled by the reaction of gold with silicon interstitials, not by the intrinsic diffusion coefficient of gold. This fact is used to understand the role silicon interstitials play during gettering in silicon. An analysis of gold profiles after gettering reveals that high concentration phosphorus diffusion, argon‐ion implantation, and mechanical damage of a silicon surface all act as sources of silicon interstitials. This finding is experimentally confirmed by studying the effect of an argon implanted surface layer on the diffusion of both phosphorus and antimony buried layers; only the phosphorus layer shows an enhancement, which is consistent with the injection of silicon interstitials. Studying the enhancement of the phosphorus diffusion versus temperature reveals that the phosphorus‐interstitial pair has a migration energy of 1.3 eV. Under the assumption of local equilibrium between silicon interstitials and phosphorus atoms, estimates of the diffusion coefficient ...

Semiconductor device using copper metallization

Abstract: A semiconductor device comprises a silicon substrate, an insulating film in which a contact hole is formed, a metallic layer deposited on said silicon substrate through the contact hole, for forming an ohmic contact to the silicon substrate, a barrier layer deposited on the metallic layer, for preventing reaction and interdiffusion between copper and silicon, and a metallization film including at least copper deposited on the barrier layer.

Method of making defect free silicon islands using SEG

Abstract: A method for forming epitaxial grown silicon structure having substantially defect free outer surfaces and resulting structure is provided. A silicon substrate is provided, on which an epitaxial silicon crystal is grown. The outer surface layer of the silicon epitaxially grown silicon crystal will contain defective material which is removed by oxidation of the outer layer to silicon dioxide. This removes the defect containing outer layer, creating a new outer layer which is substantially defect free.

Silicon-germanium base heterojunction bipolar transistors by molecular beam epitaxy

Abstract: We report the first SiGe base heterojunction Bipolar Transistors (HBT) The devices were fabricated using Molecular Beam Epitaxy (MBE), low temperature processing and different germanium contents. The transistors demonstrate current gain and show the expected increase in collector current as a result of reduced bandgap due to Ge incorporation in the base. A 6 times increase in collector current was measured for a 1000A base device containing 12% Ge, consistent with a bandgap shrinkage in the base of approximately 45 meV. For the homojunction transistors, base widths as thin as 800A were grown, corresponding to a neutral base width of only 500A. These devices have a 40% higher collector current than the equivalent devices with a 1000A base width.

Method for improved surface planarity in selective epitaxial silicon

Abstract: A method for growing selective epitaxial silicon by chemical vapor deposition resulting in a substantially planar surface by growing superimposed silicon layers at temperatures above and below a transition point.

Method for fabricating low loss crystalline silicon waveguides by dielectric implantation

Abstract: A method of fabricating low loss silicon optical waveguides by high energy ion implantation which converts a buried region into dielectric material. The top silicon surface can them be etched or formed into waveguides that are isolated by the buried dielectric. Annealing of the top silicon layer can be used to improve optical quality and additional silicon can be added to the top surface waveguides by epitaxial growth.

Process for making structures including e2prom nonvolatile memory cells with self-aligned layers of silicon and associated transistors

Abstract: The process provides for obtaining in the areas intended for the formation of the transistors windows in the intermediate oxide layer between the two silicon layers and, before final etching of the two silicon layers and the intermediate oxide, application of a mask formed in such a manner as to superimpose on the second silicon layer in the transistor areas coverings wider than the corresponding windows of the intermediate oxide layer.

Process for growing silicon-on-insulator wafers using lateral epitaxial growth with seed window oxidation

Abstract: A process for growing silicon on insulator in which complete isolation of the grown silicon of the substrate silicon by an intermediate oxide layer is obtained. A first epitaxial lateral overgrowth technique is used to grow a continuous layer of silicon through seed holes in a patterned oxide layer overlying the silicon substrate. Then the silicon layer is etched to expose the seed holes which are then oxidized to make the oxide layer aperture-free. This is followed by a second epitaxial lateral overgrowth step to replace the silicon etched in the silicon layer to make the layer substantially planar.

Method of gettering a semiconductor device and forming an isolation region therein

Abstract: In a method of manufacturing a semiconductor device according to the present invention, a given position of a thermal oxide film formed on a monocrystalline silicon layer is opened to expose a surface of the monocrystalline silicon layer to serve as a getter site, a polycrystalline silicon layer is deposited on the thermal oxide film and the surface of the monocrystalline silicon layer, and the polycrystalline silicon layer is oxidized to convert the surface of the monocrystalline silicon layer directly contacting the polycrystalline silicon layer into an oxide film by thermal oxidation. That is, the position of interface between the oxide film and the monocrystalline silicon layer is shifted into the original monocrystalline silicon layer. During thermal oxidation of the polycrystalline silicon layer, a plurality of crystal defects to serve as getter sites are generated deeper than those generated by a conventional implagetter method in the monocrystalline silicon layer. In addition, the crystal defects generated in the manner described above do not extend to the surrounding region by subsequent annealing so that a region of the crystal defects is limited.

Properties of ion beam synthesized buried silicon nitride layers with rectangular nitrogen profiles

Abstract: SOI (silicon on insulator)-structures were produced by implantation of 330 keV, 14N+-ions with doses ranging from 0.9 to 1.5 × 1018 cm−2 at a target temperature of 500°C into monocrystalline silicon to form buried silicon nitride layers. Post-implantation annealing was done at 1200°C up to 5 h. In this manner silicon nitride compounds with different stoichiometry and structure are produced. After implantation amorphous layers with Gaussian nitrogen profiles up to overstoichiometric concentrations are formed. Annealing leads to the transformation of the Gaussian profiles into rectangular ones if the maximum concentration of the as-implanted distribution does not exceed the value necessary for Si3N4 stoichiometry. In all cases the interfaces between the buried layer and the neighbouring silicon are steep and the structure of the silicon nitride is crystalline. For stoichiometric and overstoichiometric layers a high resistivity in the range of 1014 to 1016 Ω cm was found. After annealing monocrystalline silicon top layers of high quality are formed. A test is reported on the reamorphization of crystalline Si3N4. The results are promising.

Method of fabricating polycrystalline silicon resistors having desired temperature coefficients

Abstract: A method of fabricating polycrystalline silicon resistors having nearly zero or positive temperature coefficient includes the steps of depositing a layer of polycrystalline silicon, implanting the layer with silicon to make the layer substantially amorphous, introducing an impurity to dope the layer, and annealing the layer.

Signal, recombination effects and noise in amorphous silicon detectors

Abstract: Some properties of hydrogenated amorphous silicon diodes are described. Back biased diodes of the Schottky, p-i-n type, in thicknesses ranging from 5–15 μm, have been tested with 6 MeV alpha particles and with 1 and 2 MeV protons. Large signal saturation, due to electron-hole recombination, occurs for high LET particles. Diodes have been exposed to fast neutron fluences up to 10 13 cm −2 and shown to have better radiation resistance than similarly exposed crystalline silicon detectors. From our measurements we extrapolate that minimum ionizing particles can be detected with stacked layers 100–120 μm thick, with adequate signal/noise levels.

Heterojunction bipolar transistor having a base region of germanium

Abstract: The heterojunction bipolar transistor has a structure of wide band-gap transistor and comprises a collector region having an N-type GaAs layer, a base region having a P-type germanium layer formed on the N-type GaAs layer, and an emitter region having an N-type semiconductor layer of mixed crystal of silicon and germanium formed on the P-type germanium layer. The mixed crystal of the N-type semiconductor layer may have a uniform distribution of silicon or a graded distribution of silicon in which a content of silicon is zero at the surface facing the P-type germanium layer and is continuously increased with distance from the surface facing the P-type germanium layer.

Forming method for silicon thin film for thin film transistor

Abstract: PURPOSE:To obtain a silicon thin film transistor having a high carrier mobility and capable of controlling a threshold voltage to a low value by discharging in inert gas added with hydrogen gas of specific molar % to generate ions, colliding them to the surface of a target to deposit discharged silicon atoms on a substrate, and annealing it for a specific length of time. CONSTITUTION:One or more of inert gases, such as helium, neon, argon, xenon, krypton and the like are mixed, and 1-50mol% of hydrogen gas is further mixed as sputtering gas. When a negative DC voltage or high frequency voltage is applied to an electrode 22, a glow discharge is generated to generate ions from the inert atmospheric gas to collide with the surface of a target 23 made of silicon. As a result, the silicon atoms are expelled out from the target 23 to form a silicon thin film on an insulating substrate 26. Then, the silicon thin film is annealed for a short time, such as 10 sec or less of heating time by a light radiating method of a laser to form a polycrystalline state.

Process for the fabrication of integrated structures including nonvolatile memory cells with layers of self-aligned silicon and associated transistors

Abstract: After growth of gate oxide, deposit and separation of a first polycrystalline silicon layer, growth of dielectric oxide and removal thereof from the transistor area, and deposit of a second polycrystalline layer, a single mask makes possible first etching of the second silicon layer and of the dielectric oxide and then of the first silicon layer of the gate oxide at the sides of the cell and transistor areas.

Manufacture of nonvolatile storage device

Abstract: PURPOSE: To enhance the characteristic for storage retention by a method wherein a silicon nitride film with comparatively high electric conductivity and another silicon nitride film with comparatively low electric conductivity, whose chemical compositions differ from each other, are deposited in succession at a reduced pressure. CONSTITUTION: A source region 2 and a drain region 3 are formed on an N-type silicon substrate 1; a prescribed part at a silicon oxide film 4 is opened; after that, a silicon oxide film 5 is formed at the opened part. Then, silicon nitride films 6, 7 are formed in succession on the film 5. These films are formed in the following manner: the first silicon nitride film 6 with high electric conductivity is first grown at a reduced pressure; then, the chamber is evacuated to produce a sufficient vacuum; after that, a reactive gas in introduced; the second silicon nitride film with low electric conductivity is formed. Then, an aluminum thin film 8 acting as a gate electrode is coated. COPYRIGHT: (C)1988,JPO&Japio

Semiconductor body, and device formed therefrom, having grooves with silicon nitride on the groove surfaces

Abstract: A semiconductor integrated circuit device is provided with polycrystalline silicon filling U-grooves etched in a semiconductor substrate to form isolation regions which prevent any short-circuiting between the polycrystalline silicon and electrodes or wiring formed on the semiconductor substrate. A silicon dioxide film is formed within the U-grooves, and a silicon nitride film and a silicon dioxide film are further formed thereon. The silicon nitride film has a high hardness which suppresses the development of crystal defects in the peripheral active regions due to the expansion of the surface of the polycrystalline silicon when it is oxidized. When the surface of the polycrystalline silicon is oxidized, the oxidation proceeds along the oxide film over the nitride film, so that the whole of the oxide film is formed thickly. Therefore, the silicon nitride film and the silicon dioxide film are provided with an increased margin against the etching used for forming contact holes.

Charge trapping effects in amorphous silicon/silicon nitride thin film transistors

Abstract: We report simultaneous measurements of the threshold voltage shift under positive bias stress and transient discharge following such stressing, on amorphous silicon - silicon nitride thin film transistors (α-Si : H TFTs). The discharge transients exhibit two components which are both due to emission from deep states within the α-Si : H.

Method of increasing the thickness of a field oxide

Abstract: A method of manufacturing a semiconductor substrate, and, in particular, a technique of electrically isolating a semiconductor element formed on a semiconductor substrate. The method comprises the steps of depositing a silicon oxide layer on the surface of a silicon substrate, for its protection; forming a silicon nitride layer on the silicon oxide layer; selectively eliminating the silicon nitride layer; oxidizing the silicon substrate, with the retained silicon nitride layer being used as a mask, thereby providing an oxide layer; depositing a polycrystalline silicon layer on the oxide layer and the retained acid-resisting layer; oxidizing the polycrystalline silicon layer to provide an insulation layer; eliminating the insulation layer until the silicon nitride layer is exposed; and removing all the silicon nitride layer. The method is capable of enabling the formation of a thick semiconductor element-isolating oxide layer, with a high precision, in a narrow region from which the semiconductor element is to be isolated.

Analysis of the effect of thermal nitridation of silicon dioxide on silicon interstitial concentration

Abstract: The thermal nitridation of SiO2 has been analyzed in order to understand how the process results in large interstitial supersaturations in the silicon substrate as manifested by the greatly enhanced diffusivity of substitutional impurities such as phosphorus and boron and the growth of stacking faults. It is postulated that the interstitial injection is due to the growth of a thin oxygen‐rich layer at the dielectric/silicon interface and is magnified by the presence of a nitrogen‐rich layer near the interface which constrains the interstitials to the interface region. Because of the slow rate of growth of the oxide‐rich layer, an initial transient period exists during which many of the interstitials created at the interface are injected into the substrate, raising the concentration in the silicon. For long times, a steady‐state analysis shows that almost all of the interstitials generated at the interface diffuse back into the oxide. By extending a previous analysis for standard oxidation of silicon, a quantitative model was developed for interstitial supersaturation in the silicon which incorporates the transient regime and successfully predicts the diffusion enhancement of phosphorus with time. In addition, nitrogen incorporation in the bulk of the oxynitride and oxidation at the dielectric/silicon interface were modeled by an exponential decay to an equilibrium structure with a common time constant.

Method for manufacturing high-breakdown voltage semiconductor device

Abstract: A first silicon oxide film (11) is formed on the major surface of an n-type silicon substrate (10). A silicon nitride film is formed on the first silicon oxide film. The first silicon oxide film and the silicon nitride film are selectively etched to form an opening. Boron ions are implanted into the silicon substrate (10) using the first silicon oxide film (11) and the silicon nitride film as a mask. A second silicon oxide film (16) is formed on the silicon sub­strate (10) exposed by the opening. Gallium ions are implanted into the second silicon oxide film (16) using the silicon nitride film as a mask. Boron and gallium ions are simultaneously diffused in the silicon substrate. In this case, a diffusion rate of gallium in the silicon substrate is higher than that of boron in the silicon substrate (10), and the diffusion rate of gallium in the silicon oxide film (11) is higher than that in the silicon substrate (10). Therefore, a p-type second layer is formed in the substrate to surround a p⁺-type first layer in a self-aligned manner.

A method for producing thin conductive and semi-conductive layers in monocrystal silicon

Abstract: A method for producing thin conductive or semiconductive layers embedded in silicon in the manufacture of structures for integrated circuits and the like. The invention is characterized by implanting metal atoms (14) in a silicon substrate (15) to a pre-determined nominal depth, and subsequently causing the implanted metal atoms to be redistributed, to form a conductive or a semiconductive layer (16), by heat-treating the silicon substrate (15).

Process for joining molded silicon nitride parts

Abstract: For joining shaped bodies of silicon nitride together, silicon nitride surfaces to be joined are first polished and then put into an apparatus for applying sputtered layers where they are first cleaned by ion bombardment in argon, followed immediately by sputtering with silicon in a nitrogen atmosphere such that a layer is deposited having a nitrogen content exceeding the Si3 N4 stoichiometric ratio. This readily provides a layer of the composition Si3 N5.5. A complementary nitrogen deficient layer is also provided in the joint before hot pressing, either in the form of a silicon layer that goes between the nitrogen-rich silicon nitride layers or in the form of a nitrogen-deficient silicon nitride layer sputtered onto a polished silicon nitride surface at relatively low nitrogen pressure. The parts are isostatically hot pressed together at 1500° to 1750° C. in a nitrogen atmosphere. The layers which are usually thinner than 1 μm interact, with the disappearance of excess nitrogen and silicon, so that once the joint is produced all traces of jointure tend to disappear. The presence of a small amount of Y2 O3 at the joint has a favorable effect.

A method for fabricating a semiconductor device comprising simultaneous growing of epitaxial and polycristalline Si layers over a selectively oxydized Si substrate, by vapor deposition

Abstract: An epitaxial silicon layer (4) is formed on a surface of a silicon substrate (1) simultaneously with the forming of a polycrystalline silicon layer (5) on a silicon dioxide (SiO₂) layer (3), previously formed on the silicon substrate (1) using a low pressure silicon vapor deposition method, employing a silicon hydride gas, particularly disilane (Si₂H₆), as a silicon source gas. The crystal growing temperature is comprised between 780°C to 950°C and a reaction gas pressure ranging from 30 torrs to 300 torrs is preferred. An extended silicon epitaxial region (a) is achieved under a higher temperature and a higher gas pressure, and with a substrate (1) of (1 0 0) orientation. A polysilicon layer (5) having an even surface and joining smoothly to the epitaxial silicon layer (4) which is simultaneously formed, is obtained under a lower temperature and a lower gas pressure, and with a substrate (1) of a (1 1 1) orientation.

Methods for making neighboring wells for VLS1 CMOS components

Abstract: A method for the manufacture of neighboring wells 9, implanted with dopant ions of differing conductivity type in silicon substrates provided with an epitaxial layer. A lateral under-etching having high selectivity to specified layers is designationally introduced into a silicon nitride layer provided for masking the n-well regions in the implantation of the p-wells. Thus, the edge of a silicon oxide layer serving as a masking in the following oxidation shifts in the direction of the n-wells. As a result of this type of self-adjusted well production, the influence of the counter-doping in the region of the well boundaries is noticeably reduced. In addition, a polysilicon layer can also be employed under the silicon nitride layer as a masking layer, this layer eing co-oxidized after the under-etching of the silicon nitride layer. Thus a box-shaped course is produced in the masking oxide instead of the prior art bird's bill course, whereby a steeper diffusion front is achieved in the n-well. The method serves for the manufacture of VLS1 complementary MOS field effect transistor circuits.

Band offsets for the silicon nitride/amorphous silicon interface: Implications for charge transport and trapping in silicon nitride

Abstract: Threshold voltage shift measurements of silicon nitride/hydrogenated amorphous silicon devices demonstrate that electron accumulation primarily creates interface states while hole accumulation results in bulk trapped holes. This asymmetry in transport can readily be explained by the band structure as determined by recent electron spectroscopy measurements and band tailing within the nitride.

Reversible dangling-bond generation in amorphous-silicon thin-film transistors

Abstract: The field-induced degradation and thermal recovery of amorphous silicon thin-film transistors have been studied. Experimental evidence is given for the single carrier trapping-induced creation of dangling bonds in the amorphous silicon layer. It is suggested that the recovery is due to the re-formation of weak-bonds after a rate-limiting step of thermal electron-emission out of these defects with an activation energy of 0.77 eV and an attempt frequency of 4×10 6 Hz.

Layered amorphous silicon containing photoconductive element having surface layer with specified optical band gap

Abstract: A light-receiving member for electrophotography comprises a substrate and a light-receiving layer provided on the substrate comprising a photoconductive layer exhibiting photoconductivity comprising an amorphous material containing at least one of hydrogen atoms and halogen atoms as the constituent in a matrix of silicon atoms and a surface layer comprising an amorphous material containing silicon atoms, carbon atoms and hydrogen atoms and the constituents, said surface layer being changed in the distribution concentration in the layer thickness direction of the constituent elements such that matching optical gap is obtained at the interface with said photoconductive layer, and the maximum distribution concentration of the hydrogen atoms within said surface layer being 41 to 70 atomic percent.