Showing papers on "Strained silicon published in 1989"

Thin film semiconductor and process for producing the same

Abstract: A thin film semiconductor which comprises a substrate, a single crystalline silicone thin film layer and an intermediate layer disposed between the substrate and the single-crystalline silicon thin film layer. Coefficient of the thermal expansion of the intermediate layer is between those of the substrate and the single-crystalline silicon. The intermediate layer absorbs thermal stress and relaxes strain remaining in the silicon layer, which strain is generated due to difference of thermal expansion coefficient between the substrate and the silicon layer. Due to the arrangement of the intermediate layer, it becomes possible to use various material as the substrate without generating micro-cracks and produce a semiconductor device using a large sized substrate.

Method of forming a barrier layer between a silicon substrate and an aluminum electrode of a semiconductor device

Abstract: A titanium nitride barrier layer of 50 to 200 nm in thickness is fabricated between a silicon substrate and an aluminum electrode layer of an IC device by reactive sputtering performed in a mixed gas including oxygen in a proportion of 1 to 5% by volume relative to other gases, comprising an inert gas and a reactive gas, providing the temperature of the silicon substrate at 350° to 550° C. during the reactive sputtering, so that the product has a failure rate, indicating the property of preventing mutual diffusion of silicon and aluminum atoms from occurring, of less than 1% and a resistivity less than 100 μΩ.cm.

Microcantilever with integral self-aligned sharp tetrahedral tip

Abstract: Apparatus and method for forming a microfabricated cantilever with a single crystal, integral silicon tip on a nitride cantilever. A nitride-silicon-nitride sandwich structure is patterned and etched to form a cantilever structure, exposing sidewall portions of the silicon layer. The exposed sidewall portions of the silicon layer are oxidized to form oxide sidewalls. The top nitride layer is removed and the silicon layer is anisotropically etched and removed except fo a tetrahedral silicon tip formed on the rear nitride layer. The tetrahedral silicon tip has one exterior surface bounded by a (111) plane with two additional exterior surfaces bounded by the oxide sidewall. The oxide sidewall is removed to provide a tetrahedral silicon tip at the free end of the nitride cantilever. Alternative cantilever materials such as polysilicon and deposited oxide can be substituted for nitride. Doping the surface region of the cantilever form a P-N junction which provides a stop for electrochemical anisotropic etching of the silicon layer when an electrical potential is applied across the P-N position.

Passivation for integrated circuit structures

Abstract: A method is described for producing an integrated circuit structure, including EPROMS, having excellent resistance to penetration by moisture and ion contaminants and a substantial absence of voids in an underlying metal layer in the structure, and, in the case of EPROMS, maintaining sufficient UV light transmissity to permit erasure which comprises stress relieving the underlying metal layer from stresses induced by the compressive stress of a silicon nitride encapsulating layer to inhibit the formation of voids therein by implanting the metal layer with ions to change the grain structure adjacent the surface of the metal layer; forming an insulating intermediate layer between said the layer and the silicon nitride layer selected from the class consisting of an oxide of silicon and silicon oxynitride having a compressive/tensile stress which sufficiently compensates for the compressive stress of the silicon nitride layer; and controlling the compressive stress in the silicon nitride layer to provide resistance to moisture and ion penetration superior to silicon dioxide or silicon oxynitride layers of similar thickness while inhibiting formation of voids in the metal layer.

Process for elevated source/drain field effect structure

Abstract: A process for the fabrication of elevated source/drain IGFET devices is disclosed. In accordance with one embodiment of the process, a silicon substrate is provided which is divided into active and field regions by a field oxide. A gate oxide is formed over the active region and a thin layer of polycrystalline silicon and a thick layer of silicon nitride are deposited on the gate oxide. The polycrystalline silicon and the silicon nitride are etched to form a stacked structure, with the spacers having substantially the same height as the stacked structure, in the pattern of the gate electrode. Sidewall spacers are formed on the edges of the stacked structure and the silicon nitride is removed. Polycrystalline silicon is then deposited onto the polycrystalline silicon and the exposed portions of the source and drain regions to complete the gate electrode and to form the source and drain electrodes. The selectively deposited polycrystalline silicon extends upwardly from the source and drain regions onto the field oxide. The sidewall spacers provide physical and electrical isolation between the gate electrode and the adjacent source and drain electrodes.

Germanium channel silicon mosfet

Abstract: An alloy layer (2) comprising germanium and silicon is grown on top of a silicon substrate (1). The alloy layer (2) is kept thin enough for proper pseudo­morphic, dislocation free growth. A layer of silicon (3) is applied to the alloy layer (2). The initial silicon layer (3) is from two to three times as thick as the alloy layer (2). Approximately the upper two-thirds of the silicon layer (3) is oxidized, either thermally, anodically or by plasma anodization. The silicon layer (3) that remains between the silicon dioxide (4) and the alloy layer (2) is kept thin enough so that a parasitic channel does not form on the interface between the silicon and the silicon dioxide. The germanium alloyed channel (9) is thus suitably bounded by silicon crystalline structures on both of the channel layer (2) surfaces. The barrier heights between silicon dioxide and silicon are very large thus providing good carrier confinement. A suitably applied voltage will result in a region of high mobility charge carriers at the interface (5) between the alloy layer (2) and the upper silicon layer (3).

Quantum well optical device on silicon

Abstract: A semiconductor structure for use in forming optical devices, such as lasers and LEDs, is disclosed. The structure includes a silicon base on which is formed by epitaxial growth, a crystalline material (such as AlGaP) structure or region that is nearly lattice matched to silicon. One or more quantum wells are formed in the crystalline material structure. A quantum well can be made of a direct bandgap material or an indirect bandgap material with isoelectronic centers (IECs). The regions on either side of the quantum wells can be graded to form a graded index separate confinement heterostructure (GRINSCH). To reduce problems of warpage, the crystalline material can be epitaxially grown in windows formed in a layer of silicon nitride or silicon dioxide on the silicon substrate. A multi-color array of optical devices can be provided with this structure.

Vapor deposition method for simultaneously growing an epitaxial silicon layer and a polycrystalline silicone layer over a selectively oxidized silicon substrate

Abstract: A method for simultaneously forming an epitaxial silicon layer on a surface of a silicon substrate, and a polysilicon layer on a silicon dioxide (SiO 2 ) layer which is formed on the silicon substrate using a low pressure silicon vapor deposition method, employing silicon hydride gas, particularly disilane (Si 2 O 6 ), as a silicon source gas. A crystal growing temperature ranging from 780° C. to 950° C. and a reaction gas pressure ranging from 20 Torr to 300 Torr are desirable. An extended silicon epitaxial region is achieved under a higher temperature and a higher gas pressure, and with a substrate of a (100) orientation. A polysilicon layer having an even surface and joining smoothly to an epitaxial silicon layer which is simultaneously formed, is obtained under a lower temperature and a lower gas pressure, and with a substrate of a (111) orientation.

Polycrystalline silicon device electrode and method

Abstract: A polycrystalline silicon electrode and method for its fabrication are disclosed. The electrode includes a barrier layer formed by the implantation of carbon, nitrogen, or oxygen ions between two layers of polycrystalline silicon. The lower layer of polycrystalline silicon is lightly doped or undoped and the top layer is heavily doped to increase the conductivity of the electrode. The barrier layer impedes the diffusion of conductivity determining dopant impurities from one layer of polycrystalline silicon to the other.

Method of making cmos with shallow source and drain junctions

Abstract: A CMOS device having shallow source and drain regions is formed in a body of single crystalline silicon having a major surface by forming in the body adjacent well regions of opposite conductivity type having an isolation region of an insulating material extending into the body from the major surface along the junction of the well regions. Thin layers of silicon oxide are formed on the major surface over each of the well regions, and a gate line of conductive polycrystalline silicon is formed over each of the silicon oxide layers. The side walls of the gate lines are covered with a layer of silicon oxide. A layer of polycrystalline silicon is selectively deposited on the surface of the body at each side of each gate line and on the gate lines. A layer of a refractory metal is deposited on the polycrystalline silicon layer. The polycrystalline silicon layer is heated to cause the metal to react with the silicon and form a metal silicide region at least partially through the polycrystalline silicon layer. The silicide region over each of the well regions is doped with a conductivity modifier of a conductivity type opposite that of the well region. The device is then heated to diffuse the conductivity modifiers through the polycrystalline silicon layer into the silicon body to form shallow source and drain regions in each well at each side of the gate lines.

Heterostructures on silicon : one step further with silicon

Abstract: In the field of logic circuits in microelectronics, the leadership of silicon is now strongly established due to the achievement of its technology. Near unity yield of one million transistor chips on very large wafers (6 inches today, 8 inches tomorrow) are currently accomplished in industry. The superiority of silicon over other material can be summarized as follow: - The Si/Si0 interface is the most perfect passivating interface ever 2 obtained (less than 10" e y-I cm2 interface state density) - Silicon has a large thermal conductivity so that large crystals can be pulled. - Silicon is a hard material so that large wafers can be handled safely. - Silicon is thermally stable up to 1100 C so that numerous metallurgical operations (oxydation, diffusion, annealing ... ) can be achieved safely. - There is profusion of silicon on earth so that the base silicon wafer is cheap. Unfortunatly, there are fundamental limits that cannot be overcome in silicon due to material properties: laser action, infra-red detection, high mobility for instance. The development of new technologies of deposition and growth has opened new possibilities for silicon based structures. The well known properties of silicon can now be extended and properly used in mixed structures for areas such as opto-electronics, high-speed devices. This has been pioneered by the integration of a GaAs light emitting diode on a silicon based structure by an MIT group in 1985."

Masking technique for depositing gallium arsenide on silicon

Abstract: A process for forming GaAs on a silicon substrate with very low levels of unintended silicon doping. First, a dielectric layer of silicon dioxide, silicon nitride, or both is grown or deposited on the substrate. Next, a window is opened in the dielectric layer exposing the silicon substrate in the regions in which the GaAs is to be formed. The GaAs layer is then formed on the substrate using conventional techniques with the gas phase transfer of silicon contamination from the edges and back of the silicon substrate to the GaAs region inhibited by the dielectric layer or layers.

Semiconductor component with electrode(s) on substrate surface - has four-layer electrode assembly with top and bottom electrodes sandwiching amorphous silicon and silicon insulating film

Abstract: The semiconductor substrate (101) carries two electrodes (102, 106) to which voltage is applied and forms a transition from a high resistance to a low one between both electrodes. The electrode assembly contains a region of amorphous silicon (105). The electrode assembly is a four-layer lamination with a top electrode (106), the amorphous silicon region, a silicon insulating film (107), and a lower electrode. The lower electrode pref. consists of a dopant diffusion zone on the semiconductor substrate surface. Alternately, it is formed by a polycrystalline silicon. The amorphous silicon typically contains a dopant of the group III. USE/ADVANTAGE - For data memories, with resistance value equaling that of insulating material.

Conductivity modulation type mosfet

Abstract: PURPOSE: To reduce a resistance at the time of operation and to shorten a turning OFF time by forming the thicknesses of first and second conductivity type single crystal silicon layers at specific value or less. CONSTITUTION: A MOSFET which has a silicon substrate formed with a PNP transistor made of a P + type layer 5, an N - type layer 4, an N + type layer 9 and a P + type layer 7, N + -P-N - type single crystal silicon layers 14-16 laminated thereon and a gate polycrystalline silicon layer on a gate oxide film 11 is provided. The thicknesses of the layers 14-16 are set to 500Å or less. Thus, since an electric field intensity in a direction perpendicular to the surface of a channel of the MOSFET can be reduced, its surface mobility is set to 1000cm 2 /V.s in the same degree as the mobility of a bulk single crystal silicon. Thus, a resistance at the time of operation of an element can be reduced, and its turning OFF time can be shortened. COPYRIGHT: (C)1990,JPO&Japio

Differential etching of silicon nitride

Abstract: A method for differentially etching silicon nitride, preferably formed in a hydrogen free environment, wherein hydrogen is implanted into various regions of the silicon nitride. The silicon nitride may then be etched by a number of different etchants, some of which will etch the implanted regions appreciably faster and others which will etch the non-implanted regions more quickly. This method is especially useful in the fabrication of self-aligned gate devices.

Method of forming a self-aligned bipolar transistor using amorphous silicon

Abstract: A process for manufacturing a polysilicon-based bipolar semiconductor device, in particular an improved emitter contact configuration, eliminates native oxide anomalies at semiconductor interface regions, thus improving the characteristics of the emitter and its associated contact. Unwanted oxide is sputtered off the surface of a silicon substrate, so as to provide an effectively clean substrate surface. Next, a first amorphous silicon layer is formed on the surface of the substrate. Dopants are then implanted into the first amorphous silicon layer, to provide a source of diffusion impurities for forming an underlying (emitter) region. The resulting structure is then subjected to a rapid anneal which causes the impurities within the first amorphous silicon layer to diffuse into the substrate, forming the emitter region. Unwanted oxide that has been formed on the surface of the first amorphous silicon layer during the diffusion step is removed by sputtering. A titanium film and an overlying second amorphous silicon layer (ion-implanted with impurities) are formed atop the first amorphous silicon layer and the resulting structure is subjected to a further rapid anneal, so as to form a titanium-silicide layer that is intermediate and contiguous with the first and second amorphous layers.

Apparatus for coating of silicon semiconductor surface

Abstract: An apparatus for forming a film on the silicon surface of an intermediate semiconductor device, wherein a silicon oxide film on the intermediate semiconductor device is etched out with an active species without damage to the silicon surface, the difference between the etching speeds of the silicon and the silicon oxide film being 5 or less. Immediately after the etching, another film is formed on the surface of the silicon without the surface being exposed to the atmosphere. Thus, the etching of the silicon oxide film and the forming of another film can be performed in the same chamber or different chambers.

Amorphous-crystalline silicon heterojunction: Theoretical evaluation of the current terms

Abstract: In this paper, the current mechanisms and the theoretical performance as solar cell of an amorphous-crystalline silicon heterojunction are evaluated and their dependence with the amorphous silicon doping level, the interface state density, the amorphous silicon density of gap states and the amorphous silicon gap is studied. These current terms are compared among them and with the current terms of a crystalline silicon homojunction of identical doping levels. We have found that the dominant dark current mechanism is multitunnelling across localized states of the amorphous silicon gap.

Amorphous silicon switch with forming current controlled by contact region

Abstract: A method of making an electrical device comprising two electrodes and a body of a switching material formed by reacting amorphous silicon or silicon compound with a passivating agent to remove or reduce the number of unpaired electrons occuring therein. The method includes a forming step in which a forming current is passed through the amorphous silicon layer so as to form an n- or p- doped amorphous silicon layer adjacent to one of the electrodes. The doped silicon layer extends over part only of the device so that the forming current is at most 400 mA. The device exhibits a voltage controlled negative resistance (VCNR) and may be employed for example for transient protection.

Silicon wafer of excellent gettering capacity and its manufacture

Abstract: PURPOSE:To enhance a gettering capacity by forming a polycrystalline silicon layer on a single-crystal silicon substrate via a silicon oxide film having a specified thickness. CONSTITUTION:This silicon wafer is composed of the following: a single-crystal substrate; a silicon oxide film, with a thickness of 1 to 8Angstrom , formed on one surface of the substrate; a polycrystalline silicon layer formed on the silicon oxide film. In order to form the silicon oxide film on the surface of the singlecrystal silicon substrate, the substrate is heated in a gas containing molecular oxygen or in an atmosphere of steam. A thickness of the polycrystalline silicon layer formed on this silicon oxide film is 1000Angstrom to 5mum; its crystal particle is not amorphous and is 2mum or lower. When the single-crystal substrate is heated under a reduced pressure or under normal pressure in an atmosphere of gaseous silanes diluted by nitrogen gas or the like, the polycrystalline silicon layer of an excellent close contact force can be formed in a uniform thickness. By this setup, it is possible to obtain the silicon wafer whose gettering capacity is excellent.

Effect of back‐surface polycrystalline silicon layer on oxygen precipitation in Czochralski silicon wafers

Abstract: The depth profile of oxygen precipitates in silicon wafers has been investigated for a variety of back surface conditions and thermal treatments. The results clearly show localized enhancement of oxygen precipitation in the region close to back surface polycrystalline silicon layers. The depth profile of intentionally introduced stacking faults on cleaved planes has also been shown to vary and is attributed an enhancement in the absorption of silicon self‐interstitials by the back surface polysilicon layer. Consequently, the results observed in this study strongly support the enhancement effect of vacancies on oxygen precipitation in silicon crystals.

Method for forming a germanium layer and a heterojunction bipolar transistor

Abstract: A method for preparing a germanium layer (22) adjacent to a germanium silicon layer (20). Initially, a P-germanium silicon layer (16) is deposited on to an N-germanium silicon layer (14). The continuous germanium layer (22) is formed by heating the layers (14 and 16) in a steam oxidation step to approximately 1000 degrees Centigrade to transform the P-germanium silicon layer (16) into the P-germanium layer (18) and a SiO 2 layer (22). A method for forming a heterojunction bipolar transistor utilizing a P-germanium layer (50) is also disclosed.

Longitudinal electron drift mobility of hydrogenated amorphous silicon/silicon nitride multilayer structures revealed by time‐of‐flight measurements

Abstract: Electron drift mobility longitudinal to hydrogenated amorphous silicon/silicon nitride multilayer structures has been measured by the time‐of‐flight method. Transient photocurrent shows a clear kink corresponding to the transit time. The room‐temperature electron mobility in multilayer structures is smaller by three or four orders of magnitude than that observed in bulk a‐Si:H. The room‐temperature electron mobility decreases with decreasing well layer width at constant layer thickness of 13 A, while the activation energy of the mobility increases. The lifetime of electrons tends to increase when the well layer thickness is reduced.

Method for producing reverse staggered type silicon thin film transistor

Abstract: A method for producing a reverse staggered type silicon thin film transistor includes the steps of forming a gate insulating layer on a substrate having a gate electrode, the gate insulating layer having a transistor-forming portion; forming an intrinsic silicon film on the transistor-forming portion of the gate insulating layer; forming an n-type silicon layer on the intrinsic silicon layer; forming a source electrode on the n-type silicon layer; forming a drain electrode on the n-type silicon layer; forming a resist layer on the source electrode and drain electrode and having the same shape thereof; subsequently removing a portion of the n-type silicon layer by using the resist layer as a mask, such that there remains a predetermined thickness of the n-type silicon layer; and doping the predetermined thickness of the n-type silicon layer with p-type impurities by using the resist layer as a mask.

Method of fabricating junction field effect transistor

Abstract: A junction field effect transistor, specifically a static induction transistor. Prior to metallization a thin layer of germanium is placed over the exposed silicon of the source and gate regions. The germanium is intermixed with the underlying silicon to form a germanium-silicon composite. A rapid thermal anneal is performed to recrystallize the germanium-silicon composite. Alternatively, a single crystal epitaxial layer may be deposited on the silicon. Conventional metallization procedures are employed to produce ohmic source and gate contact members to the germanium-silicon composite or the epitaxial germanium of the source and gate regions. By virtue of the reduced bandgap provided by the presence of the germanium, the contact resistance of the device is reduced.

Reverse staggered type silicon thin film transistor

Abstract: A reverse staggered type silicon thin film transistor includes a substrate having a gate electrode; a gate insulating layer on the substrate and the gate electrode, the gate insulating layer having a transistor-forming portion; a lower layer silicon film on the transistor-forming portion of the gate insulating layer and in contact therewith, the lower layer silicon film being formed at a first temperature and with a first thickness; an upper layer silicon film formed on the transistor-forming portion of the gate insulating layer at a second temperature which is lower than the first temperature and with a second thickness greater than the first thickness; and n-type silicon layer on the upper layer silicon film and in contact therewith; a source electrode on the n-type silicon layer; and a drain electrode on the n-type silicon layer.