Showing papers on "Strained silicon published in 1992"

Electronic structure and optical properties of silicon crystallites: Application to porous silicon

Abstract: We have calculated the electronic structure of spherical silicon crystallites containing up to 2058 Si atoms. We predict a variation of the optical band gap with respect to the size of the crystallites in very good agreement with available experimental results. We also calculate the electron‐hole recombination time which is of the order of 10−4–10−6 s for crystallites with diameters of 2.0–3.0 nm. We conclude that small silicon crystallites can have interesting optical properties in the visible range. These results are applied to porous silicon for which we confirm that a possible origin of the luminescence is the quantum confinement.

NMOS and PMOS transistors fabricated in strained silicon/relaxed silicon-germanium structures

Abstract: N- and P-MOSFETs have been fabricated in various epitaxial layer structures containing relaxed Si/sub 1-x/Ge/sub x/, and strained Si active regions Theoretical calculations predict that the strain-splitting of the conduction bands should produce a higher bulk electron mobility in strained Si Enhanced electron mobilities have recently been observed in n-type modulation-doped structures employing strained Si In this work we demonstrate NMOS transistors with peak room temperature electron mobilities which are a factor of 22 larger than those measured in devices fabricated in CZ Si substrates By comparing the behavior of buried- and surface-channel structures, we have observed mobility enhancements associated with both the separation of the electrons from the semiconductor/oxide interface, and the strain-induced band splitting The room temperature performance of PMOS devices fabricated in such structures is not significantly different from that of the Si control devices >

Paramagnetic point defects in amorphous silicon dioxide and amorphous silicon nitride thin films

Abstract: In this paper the authors review paramagnetic point defects in amorphous silicon nitride thin films. We will discuss two intrinsic paramagnetic defects: a trivalent silicon center, named the K-center, and the recently observed nitrogen dangling-bond center. We examine the structural identification, and the electronic properties of the K-center, as well as consider why a SiN{sub x}:H is generally a very effective charge trapping dielectric. In addition, this paper compares and contrasts special features of the structure and electronic role of the paramagnetic point defects in both silicon dioxide and silicon nitride thin films; this may provide insight for further studies on the physics and chemistry of these dangling-bond centers in both materials.

High quality photovoltaic semiconductor material and laser ablation method of fabricating same

Abstract: A high quality, narrow band gap, hydrogenated amorphous germanium or amorphous silicon alloy material characterized by a host matrix in which all hydrogen is incorporated therein in germanium monohydride or silicon monohydride form, respectively; their mobility-lifetime product for non-equilibrium charge carriers is about 10-8 and about 10-7, respectively; their density of defect states in the band gap thereof is less than about 1 x 1017 and about 2 x 1016/cm3, respectively; and their band gap is about 1.5 and about 0.9 eV, respectively. There is also disclosed a structure formed from a plurality of very thin layer pairs of hydrogenated amorphous germanium and amorphous silicon alloy material, each layer pair of which cooperates to provide narrow band gap material. From about 3 to about 7 atomic percent fluorine is added to the germanium and/or silicon alloy material so as to provide a strong bond (as compared to hydrogen) so as to provide reduced sensitivity to Stabler/Wronski degradation. The preferred method of fabricating such improved narrow band gap materials is through a laser ablation process in which hydrogen or fluorine gas is introduced for incorporation into the germanium or silicon host matrix, thereby eliminating the reliance on the zoo of precursor species present in r.f. or microwave plasma process. The apparatus (10) employed includes an excimer laser (1) which produces pulsed UV light (2) which passes through a focusing lens (3) and a quartz window (4) in the vacuum chamber (5) and strikes a silicon or germanium target (6) which is mounted on an axle (7). A plasma zone (9) is created within which one or more heated substrates (8) are mounted.

Method of fabricating a polycrystalline silicon film having a reduced resistivity

Abstract: Disclosed is a method of forming a polycrystalline silicon film on a silicon oxide film in which the polycrystalline silicon film includes crystal grains having a large size, typically 4 micrometers, thereby permitting the resistivity of the polycrystalline silicon film to effectively be reduced. An amorphous silicon film is deposited on the silicon oxide film by using a chemical vapor deposition in which the flow rate of impurity gas remains at zero during an initial deposition, after which the flow rate is gradually increased from zero to a predetermined value during a final deposition. Thus, the amorphous silicon film comprises double layers, or an impurity unmixed region abutting the silicon oxide film and an impurity mixed region. After that, by a heat treatment, the amorphous silicon film is crystallized to form a polycrystalline silicon film. Concurrently, the impurity diffusion is accomplished.

Quantum confinement effects in strained silicon‐germanium alloy quantum wells

Abstract: We report the first detailed study of quantum confinement shifts of band‐edge photoluminescence energies in Si/strained Si1−xGex/Si single quantum wells. A quantum confinement energy of up to 45 meV has been observed for quantum wells as small as 33 A in width. The experimental results are in good agreement with a calculation of the hole confinement energies. The hole energy levels in quantum wells were obtained by numerically solving effective‐mass equations with proper matching boundary conditions at interfaces using a 6×6 Luttinger–Kohn Hamiltonian. Both strain and spin‐orbit interactions were included in the calculation.

Electron drift mobility model for devices based on unstrained and coherently strained Si/sub 1-x/Ge/sub x/ grown on silicon substrate

Abstract: The electron drift mobility for unstrained and coherently strained Si/sub 1-x/Ge/sub x/ grown on a silicon substrate is analytically obtained for Ge fractions less than 30%. The method is based on the following two assumptions: the conduction bands of the unstrained alloy are Si-like for Ge fraction less than 30%, and in the case of the coherently strained alloy, strain-induced energy shifts occur in the conduction band valleys. The shifts in energy yield two different mobility values: one corresponding to the growth plane with a value larger than the unstrained mobility, and the other parallel to the growth direction and correspondingly smaller in value. In comparison to silicon, the results show a degradation of both the unstrained mobilities for doping levels up to 10/sup 17/ cm/sup -3/. Beyond this doping level, the strained mobility component parallel to the growth direction becomes slightly larger than the mobility of silicon. >

Charge transfer and low‐temperature electron mobility in a strained Si layer in relaxed Si1−xGex

Abstract: Calculated results for charge transfer and low‐temperature electron mobility in strained silicon grown epitaxially on relaxed Si1−xGex are presented versus the thickness of an undoped spacer layer and other structural and materials parameters. The indicated conduction band offset for Si on relaxed Si0.7Ge0.3 is 180±15 meV. Scattering by the remote doping impurities that supply the carriers is found to be the dominant scattering mechanism in high‐mobility samples. Samples with enhanced interface scattering are expected to have a stronger temperature dependence of mobility.

Method for manufacturing a semiconductor device and a semiconductor memory device

Abstract: An improved method for manufacturing an insulated gate field effect transistor is provided. As a first step, a silicon oxide film is grown on a silicon substrate, and a first silicon nitride film is deposited thereon. The first silicon nitrite film, the silicon oxide film and the silicon substrate are then etched using a resist pattern as a mask to form a silicon island which includes at least a part of the silicon substrate. A second silicon oxide film is then grown on the surface of the silicon substrate exposed by the second step, as well as on the surface of the silicon island, and a second silicon nitrite film is deposited thereon. The second silicon nitrite film is then etched to leave a portion of the second silicon nitrite film deposited on a side wall of the silicon island. After this, a third silicon oxide film is grown by thermal oxidation of the surface of the silicon substrate to electrically separate the silicon island from the silicon substrate. Next a gate electrode is formed on silicon island, followed by forming source and drain regions in the silicon island employing the gate electrode as a mask.

Silicon on Insulator Structures Obtained by Epitaxial Growth of Silicon over Porous Silicon

Abstract: Epitaxial silicon films are obtained by low temperature chemical vapor deposition on porous silicon layers (PSL). The PSL are formed on lightly and highly boron doped silicon substrates. In the case of lightly doped substrates, the epitaxial films exhibit a large defect density (10 10 cm -2 ). It is shown that this defect density can be reduced by a 10 2 to 10 3 factor through the use of silicon channeled implantation and subsequent thermal annealing. On the other hand, when the epitaxial growth is performed on PSL formed from highly doped boron substrates, the epitaxial quality of the resulting films is equivalent to the homoepitaxy of silicon on bare silicon

Crucial issues in semiconductor materials and processing technologies

Abstract: *Defect Aspects of Advanced Device Technologies.- Field Effect Analysis in Low Voltage Operation a-Si:H Thin Film Transistors with Very Thin PECVD a-SiO2 Gate Dielectric.- *Silicon and Silicon: Germanium Alloy Growth Means and Applications.- *Preparation and Characterization of Silicon Ribbons.- Rapid Thermal Chemical Vapor Deposition of Six Ge1-x Alloys on Si and SiO2 and New Applications of Six Ge1-x Alloys in Advanced MOSFET Processes.- *Kinetics and Dynamics of MBE Growth.- Effects of Near-Interface Defects on the Optical Properties of MBE Grown GaAs/AlGaAs Layers.- *Optoelectric Materials.- Electrical Characteristics of PECVD Silicon Nitride/Compound Semiconductor Interfaces for Optoelectronic Device Passivation.- *Fundamentals of Semiconductor Processing.- Optical Analysis of Oxygen in Epitaxial Silicon.- Electrical Properties of "Clean" and Fe-Decorated Stacking Faults in p-type Si.- On the Dirty Contacts on n-type Silicon.- Moessbauer Study of the DX-Center in Te-Implanted Alx Ga1-x As.- *Surface Science and Semiconductor Processing.- *Lithography for Manufacturing at 0.25 Micrometer and Below.- *Basic Aspects of Ion Implantation.- *Trends in Ion Implantation for Semiconductor and Optical Materials Research.- Orientation Phenomena in MeV Implants of P in Si.- Deep Implants by Means of Channeling: Ion Distribution and Radiation Damage in Angle Controlled N+ Implantation in Silicon.- Dislocation Formation in Si Implanted at Elevated Temperature.- Preparation and Characterization of Thin Film Simox Materials.- The Effect of Electronic Energy Loss on Epitaxial YBa2Cu3O7 Thin Films After Heavy Ion Irradiation and Annealing up to Room Temperature.- Structural Study of The Epitaxial Realignment of Polycrystalline Si Films onto Si Substrates.- *Plasma Immersion Ion Implantation: A Perspective.- A Sheet Stress Measurement Technique Using Thin Films to Measure Stresses in Inert-Gas Implanted Silicon.- Plasma Etching Processes.- *Charge Trapping, Degradation and Wearout of Thin Dielectric Layers During Electrical Stressing.- Minority Carrier Lifetime Measurements After High Temperature Pretreatment.- *Copper-Based Metallization.- Thermal Stability of Ti-Mo and Ti-Cu Bilayer Thin Films on Alumina.- Hyperfine Fields in Epitaxially Grown Co on GaAs.- Titanium Nitride Process Development.- *Materials Aspects and Implementation of Silicides for ULSI.- Ion Beam Synthesis of Buried Iron Disilicide.- Diffusion in Cobalt Suicide During Silicide Formation.- Formation of Germanides by Rapid Thermal Annealing and Their Applications in Advanced MOSFET Processes.- *Diffusion in Crystalline Silicon and Germanium - The State of the Art in Brief.- Symmetry Methods in Diffusion.- Diffusion of Gold in Sputtered Amorphous Silicon.- Dopant Diffusion and Point Defects in Silicon During Silicidation.- Lateral Diffusion Couples and Their Contribution to Understanding Thin Film Reactions.- *Diffusion and Defects in Amorphous Silicon.- EPR Study of Defects Produced by MeV Ion Implantation into Silicon.- Vacancy Character of Damage Zones in Ion-Irradiated Silicon.- Multiple Amorphous States in Ion Implanted Semiconductors (Si and InP).- *The Mechanism of Solid Phase Epitaxy.- The Amorphous Side of Solid Phase Epitaxy.- *Metal-Enhanced Growth of Silicon.- *Ion-Assisted Phase Transitions in Silicon.- Ion-Assisted Nucleation in Amorphous Silicon.- List of Participants.

Single-crystal silicon on quartz

Abstract: A method for fabricating single crystal islands on a high temperature substrate, thereby allowing for the use of high temperature processes to further make devices incorporating the islands such as, for example, high mobility thin film transistor integrated drivers for active matrix displays. The method essentially includes depositing an etch stop layer on a single crystal silicon substrate, depositing a single crystal silicon device layer on the etch stop layer, bonding a quartz substrate to the single crystal silicon device layer at room temperature, sealing and securing with an adhesive the edges of the single crystal silicon substrate, the etch stop layer, the single crystal silicon device layer and the quartz substrate, grinding away a portion of the silicon substrate and a portion of the adhesive, etching away the remaining portion of the silicon substrate, removing the remaining portion of the adhesive, etching away the etch stop layer, applying a photoresist mask on the single crystal silicon device layer for defining the islands on the single crystal silicon device layer, etching single crystal silicon islands, and then the first non-room-temperature process of diffusion bonding the single crystal silicon islands to the quartz substrate.

Method for forming thin film transistor

Abstract: An amorphous semiconductor layer is deposited on an insulating substrate, and an excimer laser is radiated thereon, and thus the amorphous is crystallized. A silicon oxide layer is deposited on the semiconductor layer, and a silicon nitride layer is deposited on the silicon oxide layer to be thicker than the silicon oxide layer. Thereafter, a gate electrode is formed on the silicon nitride layer. Thus, there is provided a method for a thin film transistor having a good mobility of carriers and a good characteristic of a breakdown voltage in that a gate insulating film is formed of a double-layer structure having the silicon oxide and silicon nitride layers.

Type silicon material with enhanced surface mobility

Abstract: A new-type silicon material is produced by hydrogen ion implantation and subsequent annealing, the annealing being preferably in two steps. The present invention raises surface mobility of a silicon wafer and produces a buried high-resistivity layer beneath a silicon surface layer. The resulting products are particularly useful for the improvement of yield and speed and radiation hardness of very large scale integrated circuits.

Electron mobilities and high-field drift velocities in strained silicon on silicon-germanium substrates

Abstract: Summary form only given. The authors have performed a detailed analysis of the in-plane electron transport in strained Si on Si/sub 1-x/Ge/sub x/ with a Monte Carlo method. They present data on electron drift mobilities and velocities in the whole range from low to very high electric fields that can serve as a reference for the transport in modulation-doped channels. The results demonstrate significant improvements of the in-plane electron drift velocity in strained Si on Si/sub 1-x/Ge/sub x/ compared to bulk Si in the low-field and the high-field regions both at 300 and at 77 K. This advantage should contribute considerably to the high-performance potential of devices based on modulation-doped Si/SiGe heterostructures such as n-channel quantum-well MODFETs and MOSFETs. >

Silicon transistor device with silicon-germanium electron gas hetero structure channel

Abstract: A metal oxide semiconductor field effect transistor with heterostructure has a silicon substrate. Heavily-doped source and drain layers which are different in conductivity type from the substrate are spaced apart from each other in the surface portion of the substrate. A gate electrode of polycrystalline silicon is disposed above the substrate, and is electrically insulated from the substrate by a gate insulation layer made of thermal silicon oxide thin film. A silicon germanium layer is laterally provided in a preselected substrate surface section positioned between the source and drain layers. This layer partially overlaps the source and drain layers at both of its end portions, and is thus electrically in contact with these layers. The silicon germanium layer acts as a channel of the transistor.

Multilayered composition with a single crystal beta-silicon carbide layer

Abstract: Single-crystal silicon carbide can be obtained by being applied to a single-crystal substrate (e.g. silicon) provided with a buffer layer. It is known to generate the buffer layer by carbonising the surface of silicon. In order to obtain a single-crystal silicon carbide layer with as large an area as possible and as free of defects as possible and which can be fitted with integrated components, the buffer layer must ensure a match between the crystal lattice of the silicon carbide and that of the single-crystal substrate. Suitable buffer layers, for example on a silicon wafer, include, in particular, tantalum carbide, titanium carbide, titanium nitride or manganese oxide. On the surface of the single-crystal silicon carbide layer, electronic components can be integrated, especially for power electronics.

High-breakdown-voltage semiconductor element

Abstract: In a high-breakdown-voltage diode, a high-concentration p-type layer (2) is selectively formed in an n-type silicon layer (1), and a high-concentration n-type layer (3) is formed in the same separate from the layer (2) by a predetermined distance. An insulation film (8) having a dielectric constant larger than silicon is formed on that portion of the n-type silicon layer (1) which extends between the layers (2, 3), for relaxing concentration of an electric field caused in the surface of the substrate.

Method of manufacturing a semiconductor device having a semiconductor growth layer completely insulated from a substrate

Abstract: A silicon oxide layer is formed on a silicon substrate, and an opening whose wall is sloped inward is formed in the silicon oxide layer. A seed crystalline silicon layer is formed from the opening. The seed crystalline layer is selectively oxidized while leaving the seed crystalline layer required for crystal growth. An oxide formed at this time closes the opening. Consequently, the seed crystalline layer is insulated from the silicon substrate. The seed crystalline layer is epitaxially grown, to obtain a silicon growth layer on a field oxide layer. The growth layer is insulated from the silicon substrate, and is uniform in surface direction. Accordingly, there is no parasitic capacitance due to a p-n junction between the silicon substrate and the growth layer, thereby to make it possible to perform a high-speed operation. In addition, the growth layer is uniform in surface direction, thereby to make it easy to control the conditions set so as to obtain desired device characteristics in the manufacturing processes.

Field effect element utilizing resonant-tunneling and a method of manufacturing the same

Abstract: A field effect transistor according to the present invention uses a silicon monocrystalline substrate. At least two independent thin amorphous silicon layers are formed in a position for preventing movement of majority carriers in a channel region in the surface of the silicon substrate. Each amorphous silicon layer is between monocrystalline silicon layers. A gate electrode is formed on the surface of the channel region through a gate insulating layer. Thin potential barriers and a potential well are formed in the channel region by at least two amorphous silicon layers. Sharp potential barriers are formed by forming thin amorphous silicon layers, and a field effect transistor utilizing the resonant-tunneling effect with high tunneling efficiency is implemented.

Barrier metal contact architecture

Abstract: The interconnect system of the present invention is comprised of a TiW metal barrier layer as well as a Ti metal barrier layer deposited on the silicon surface. An anisotropic etch process for the Ti/TiW/Al metal sandwich has also been developed without corrosion and metal residue. The addition of the Ti layer between the TiW layer and the silicon surface reduces the contact resistance between the metal and P+ silicon contact. This Ti layer also effectively improves the blocking of aluminum migration to the silicon surface through TiW grain boundaries. In order to realize good ohmic metal-P+ contacts, the surface concentration of the silicon should be very high. Therefore, the present invention also employs a plasma mode etch which removes about 250 Å silicon since peak concentrations of P+ dopants (boron) are often found about 400 Å below the silicon surface. This plasma mode etch will also remove silicon damage caused by previous etching. A detailed etching process is also developed in the present invention so as to avoid any corrosion or metal residue.

Method of fabricating SOI substrate with uniform thin silicon film

Abstract: A thin Silicon film On Insulator (SOI) material fabricating method which is capable of providing a very high thickness uniformity of the silicon film, a process simplification and a considerable reduction of processing cost is disclosed, in which a silicon oxide film is formed on one or both of a p-type silicon bond wafer and a silicon base wafer, then the two wafers are bonded together through the silicon oxide film, subsequently a fixed positive charge is induced in the silicon oxide film to form a n-type inversion layer in the p-type silicon bond wafer adjacent to an interface between the p-type silicon bond wafer and the silicon oxide film layer, and thereafter a chemical etching is effected while applying a positive voltage to the p-type silicon bond wafer so that an etch-stop is made at an interface between a depletion layer including the n-type inversion layer and the p-type layer.

Formation of polycrystalline silicon layer and polycrystalline silicon thin film transistor using the same

Abstract: PURPOSE:To reduce a defect density in a polycrystalline silicon layer and improve electrical characteristics of a TFT, by thermally treating the polycrystalline silicon layer at a specific temperature after an annealing of a light beam. CONSTITUTION:A passivation film 2 such as silicon oxide is formed on a substrate 1 and further an amorphous silicon thin film 3 is formed on the passivation film 2. Then, a light beam 6 such as continuous oscillation laser light is applied to the amorphous silicon thin film 3, and an annealing of the light beam with a light beam scanning speed of 5000 per sec or longer the product of a beam spot diameter is performed and a polycrystalization is performed without resulting in a complete melting condition. After this, a formed polycrystalline silicon layer 30 is thermally treated at a temperature of 350 to 430 deg.C and a defect density in the polycrystalline silicon layer 30 is reduced. In this case, for example, a continuous oscillation argon ion laser having a high output is used as the light beam 6.

Multi-layer silicon carbide light emitting diode having a PN junction

Abstract: This invention is a multi-layer pn type silicon carbide light emitting diode. A first n-type silicon carbide layer is deposited on an n-type substrate. The first n-type silicon carbide layer has an electron concentration larger than 1×10 15 cm -3 and smaller than the electron concentration of the substrate and has a thickness of between 0.1 to 20 μm. A second n-type silicon carbide layer is disposed over the first n-type layer. A first p-type silicon carbide layer is disposed on the second n-type layer to form a PN junction layer.

Method for making a bipolar transistor having a silicon carbide layer

Abstract: A layer of silicon carbide (33, 38, 41) is utilized in forming a bipolar transistor (30, 40). The transistor (30, 40) is formed on a substrate (31, 32) that has a single crystal silicon surface. The layer of silicon carbide (33, 38, 41) is epitaxially formed on the single crystal silicon surface. Thereafter, a layer of silicon (34) is epitaxially formed on the layer of silicon carbide (33, 38, 41). The silicon carbide (33, 38, 41) functions as an active transistor layer or alternately is within the transistor's depletion region.

Molecular‐beam epitaxy of strained silicon germanium/silicon structures

Abstract: The growth of strained layer heterostructures is influenced by intentionally undesired phenomena as surface undulations, alloy clustering, defect generation, interface intermixing. The origin of these effects is explained and strategies to overcome them are discussed. Recently, in the silicon germanium (SiGe) system exciting progress toward layers controlled on a monolayer scale was obtained. The status will be demonstrated by doped and undoped heterostructures, multiple heterostructures, and superlattices. Special emphasis will be given to structures relevant for devices as heterobipolar transistors (HBT), modulation doped field effect transistors (MODFET), and novel optoelectronic devices. For all these structures the strain is explicitly utilized for band structure engineering. In several areas the progress in material preparation pushed an tremendous performance increase. Examples given are the low base sheet resistivity (1.6 kΩ/⧠) for high speed (42 GHz) SiGe–HBTs, the 4.2 K mobility increase in n‐MO...

Electroluminescent silicon device

Abstract: An electroluminescent silicon device (10) includes a silicon structure (12) which comprises a bulk silicon layer (14) and a porous silicon layer (16). The porous layer (16) has merged pores (20) which define silicon quantum wires (18). The quantum wires (18) have a surface passivation layer (22). The porous layer (16) exhibits photoluminescence under ultra-violet irradiation. The porous layer (16) is pervaded by a conductive material such as an electrolyte (24) or a metal (48). The conductive material (24) ensures that an electrically continuous current path extends through the porous layer (16); it does not degrade the quantum wire surface passivation (22) sufficiently to render the quantum wires (18) non-luminescent, and it injects minority carriers into the quantum wires. An electrode (26) contacts the conductive material (24) and the bulk silicon layer has an Ohmic contact (28). When biased the electrode (26) is the anode and the silicon structure (12) is the cathode. Electroluminescence is then observed in the visible region of the spectrum.

Semiconductor device silicon via fill formed in multiple dielectric layers

Abstract: A semiconductor device with an electrode wiring structure comprises at least one diffused region provided in a semiconductor substrate, a silicon oxide layer covering the substrate surface, a silicon nitride layer provided on the silicon oxide layer, a through-hole reaching the diffused region through the silicon oxide layer from an upper surface of the silicon nitride layer, a silicon semiconductor layer filled in the through-hole and serving as an electrode wiring layer, and an interconnection layer electrically connected to the diffused region through the silicon semiconductor layer. According to the structure, since the silicon oxide layer is covered with the silicon nitride layer, unwanted contaminations such as phosphorus, boron, etc., previously contained in the silicon oxide layer are not added to the silicon semiconductor layer during its growth process. Therefore, the electrode wiring layer of silicon semiconductor having controlled conductivity can be provided.