Showing papers on "Strained silicon published in 1994"

Luminescence of silicon materials : chains, sheets, nanocrystals, nanowires, microcrystals, and porous silicon

Abstract: Both nanocrystal silicon and porous silicon thin films show efficient visible luminescence at room temperature, thus suggesting the possibility of introducing some form of optically active, silicon-based material into integrated circuit processing. In this context, I discuss and analyze the responsible electronic quantum size effects and excited-state photophysics. In a broader context I discuss silicon optical and electronic properties as a function of dimensionality and surface chemistry. As one progresses from trans-polysilane (1D-Si) through puckered sheet polysilyne (2D-Si) to diamond lattice silicon (3D-Si), there is a systematic progression from direct to indirect gap behavior

Method of manufacturing multiple polysilicon TFTs with varying degrees of crystallinity

Abstract: Method of fabricating a semiconductor circuit is initiated with formation of an amorphous silicon film. Then, a second layer containing at least one catalytic element is so formed as to be in intimate contact with the amorphous silicon film, or the catalytic element is introduced into the amorphous silicon film. This amorphous silicon film is selectively irradiated with laser light or other equivalent intense light to crystallize the amorphous silicon film.

Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers

Abstract: A method and a layered planar heterostructure comprising one of or both n and p-channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate wherein one layer is silicon or silicon germanium under tensile strain and one layer is silicon germanium under compressive strain whereby n channel field effect transistors may be formed with a silicon or silicon germanium layer under tension and p-channel field effect transistors may be formed with a silicon germanium layer under compression. The plurality of layers may be common to both subsequently formed p and n-channel field effect transistors which may be interconnected to form CMOS circuits. The invention overcomes the problem of forming separate and different layered structures for p and n-channel field effect transistors for CMOS circuitry on ULSI chips.

Polycrystalline silicon thin films processed with silicon ion implantation and subsequent solid-phase crystallization: Theory, experiments, and thin-film transistor applications

Abstract: A review is presented of the self‐implantation method which has been developed to achieve high‐quality polycrystalline silicon thin films on insulators with enhanced grain sizes and its applications to thin‐film transistors (TFTs). In this method, silicon ions are implanted into an as‐deposited polycrystalline silicon thin film to amorphize most of the film structure. Depending on ion implantation conditions, some seeds with 〈110〉 orientation remain in the film structure due to channeling. The film is then thermally annealed at relatively low temperatures, typically in the range of 550–700 °C. With optimized process conditions, average grain sizes of 1 μm or greater can be obtained. First, an overview is given of the thin‐film transistor technology which has been the greatest motivation for the research and development of the self‐implantation method. Then the mechanism of selective amorphization by the silicon self‐implantation and the crystallization by thermal annealing is discussed. An analytical mode...

Method of obtaining high quality silicon dioxide passivation on silicon carbide and resulting passivated structures

Abstract: A method of obtaining high quality passivation layers on silicon carbide surfaces by oxidizing a sacrificial layer of a silicon-containing material on a silicon carbide portion of a device structure to substantially consume the sacrificial layer to produce an oxide passivation layer on the silicon carbide portion that is substantially free of dopants that would otherwise degrade the electrical integrity of the oxide layer.

Soi substrate fabrication

Abstract: A back-etch silicon-on-insulator SOI process that has a silicon handle wafer with an oxide layer bonded at room temperature to a silicon device wafer with an etch stop and silicon device layer. The surfaces that are bonded at room temperature are first conditioned to be hydrophilic. After bonding, the edges of the layers are sealed. The silicon device wafer, the etch-stop layer and the device layer are boron doped. Most of the silicon device wafer is ground away. Then, the remaining portion of the silicon device wafer and the etch stop layer are chemically etched away, thereby leaving a uniform layer of silicon device layer on the oxide layer of the silicon handle wafer. Because the bonding, grinding and selective etching are performed at room temperature, inter-diffusion of the boron between the various layers is prevented and thus permits the selective etching process to result in a nearly perfect silicon device layer in terms of an even-surfaced, defect-free and thin layer on the buried oxide layer of silicon handle wafer. The resulting SOI wafer is then annealed at a high temperature, prior to device processing.

Atomic hydrogen‐induced interface degradation of reoxidized‐nitrided silicon dioxide on silicon

Abstract: Remote hydrogen plasma exposure is used to study the transport of atomic hydrogen, H0, through reoxidized‐nitrided oxides and SiO2 and to quantify H0‐induced degradation of their interfaces with silicon. It is directly demonstrated that (1) H0 is extremely reactive and produces large numbers of interface states; (2) the transport of H0 to the silicon/oxide interface is strongly suppressed in reoxidized‐nitrided oxides; and (3) this suppression of the H0 transport is mainly responsible for the much slower interface degradation of reoxidized‐nitrided oxides during high‐field, hot‐electron stress as compared to thermal oxide.

Elevated source/drain junction metal oxide semiconductor field-effect transistor using blanket silicon deposition

Abstract: The described embodiments of the present invention provide a method for fabricating elevated source/drain junction metal oxide semiconductor field-effect transistors. The process does not require the use of selective or epitaxial silicon growth processes. In one embodiment, first a three layer gate stack is formed having a gate dielectric layer (20) beneath a polycrystalline silicon gate layer (22) and a disposable spacer layer (24), such as silicon nitride formed on top of the polycrystalline silicon gate. A conformal dielectric layer is formed overall and anisotropically etched to form sidewall spacers layers (26) on the sides of the gate, and spacer layer stack. The spacer layer (24) is then selectively removed and a layer of amorphous or polycrystalline silicon (30) is deposited overall. A layer of silicon nitride is then deposited on the surface of the polycrystalline silicon layer using chemical-vapor deposition techniques. The silicon nitride layer is etched anisotropically to leave sidewall silicon nitride layers (32) on the portion of the polycrystalline silicon layer over the sidewalls of the gate structure. The exposed layer portion of the polycrystalline silicon layer is then selectively oxidized and a selective silicon nitride etch is then used to remove the sidewall nitride oxidation mask layers, followed by a selective silicon etch to remove the sidewall portion of the polycrystalline silicon layer exposed by the removal of the silicon nitride sidewalls. This leaves elevated source and drain junction regions extending from the sidewalls of the gate on to the field isolation structures surrounding the field-effect transistor area. The silicon layer 40 and 42 extending over the field insulating layer (18) can be patterned and used for local interconnects. The microlithography patterning and silicon dioxide/silicon etch processes for definition of the local interconnect layers can be performed after the selective oxidation process step and prior or after the sidewall nitride and silicon removal.

Semiconductor device and method for its preparation

Abstract: A semiconductor device is disclosed. The semiconductor device has a crystalline silicon film as an active layer region. The crystalline silicon film has needle-like or columnar crystals oriented parallel to the substrate and having a crystal growth direction of (111) axis. A method for preparing the semiconductor device comprises steps of adding a catalytic element to an amorphous silicon film; and heating the amorphous silicon film containing the catalytic element at a low temperature to crystallize the silicon film.

Method for reducing micropipe formation in the epitaxial growth of silicon carbide and resulting silicon carbide structures

Abstract: A method is disclosed for producing epitaxial layers of silicon carbide that are substantially free of micropipe defects. The method comprises growing an epitaxial layer of silicon carbide on a silicon carbide substrate by liquid phase epitaxy from a melt of silicon carbide in silicon and an element that enhances the solubility of silicon carbide in the melt. The atomic percentage of that element predominates over the atomic percentage of silicon in the melt. Micropipe defects propagated by the substrate into the epitaxial layer are closed by continuing to grow the epitaxial layer under the proper conditions until the epitaxial layer has a thickness at which micropipe defects present in the substrate are substantially no longer reproduced in the epitaxial layer, and the number of micropipe defects in the epitaxial layer is substantially reduced.

Porous polycrystalline silicon: a new material for MEMS

Abstract: A new technique for the fabrication of thin patterned layers of porous polycrystalline silicon (polysilicon) and surface micromachined structures is presented. First, a multilayer structure of polysilicon between two layers of low-stress silicon nitride is prepared on a wafer of silicon. Electrochemical anodization with an external cathode takes place in an RF solution. A window in the outer nitride layer provides contact between the polysilicon and the HF solution; the polysilicon layer contacts the substrate through openings in the lower silicon nitride layer (remote from the upper windows). Porous polysilicon growth in the lateral direction is found at rates as high as 15 /spl mu/m min/sup -1/ in 12M (25%, wgt) HF to be controlled by surface-reaction kinetics. A change in morphology occurs when either the anodic potential is raised or the HF concentration is decreased, causing the polysilicon to be electropolished. The etch front advances proportionally to the square root of time as expected for a mass-transport-controlled process. Similar behavior is observed in HF anodic reactions of single-crystal silicon. Dissolution of the polysilicon layer is confirmed using profilometry and scanning electron microscopy. Enclosed cavities (chambers surrounded by porous plugs) are formed by alternating between pore formation and uniform dissolution. Porous polysilicon also forms over a broad-area layer of polycrystalline silicon that has been deposited without overcoating the silicon wafer with a thin film of silicon nitride. The resulting porous layer may be useful for gas-absorption purposes in ultrasonic sensors. >

SOI (silicon on insulator) substrate with enhanced gettering effects

Abstract: A silicon-on-insulator (SOI) substrate is arranged such that a polycrystalline silicon film which functions as a gettering site for heavy metals is provided on a first single crystal silicon substrate, a silicon oxide island film is partially provided in a polycrystalline silicon film, and a second single crystal silicon substrate is provided on an entire upper surface of the polycrystalline silicon film. An element isolation trench extends from an upper surface of the second single crystal silicon substrate to an upper surface of the first single crystal silicon substrate, and a silicon oxide film is buried in the element isolation trench. The SOI substrate thus constituted has a high gettering effect for heavy metals.

Process for producing Semiconductor silicon wafer

Abstract: Provided is a process for producing a semiconductor silicon wafer by which an intrinsic gettering effect can be improved and at the same time the top side can be made free from faults. A silicon ingot is produced and sliced to obtain silicon wafers. Then, a polycrystal silicon depositing film is formed on one side of a silicon wafer, which is subjected to a heat treatment in an inert gas, a reducing gas or a mixture thereof to discharge oxygen from the vicinity of the other side. Alternatively, after discharging oxygen from the silicon wafer by a heat treatment, a polycrystal silicon depositing film may be formed on one side of the silicon wafer.

Fabrication of a silicon quantum wire surrounded by silicon dioxide and its transport properties

Abstract: A novel fabrication method for ultrafine silicon wires is presented. To achieve electron physical confinement with a high potential SiO2 barrier, the SIMOX (separation by implanted oxygen) technique, electron beam lithography, anisotropic chemical etching, and thermal oxidation are used. The size of the wires is controlled by the lithography, the thickness of the top silicon layer and the thermal oxidation for narrowing the patterned silicon wire. The steplike structure in the conductance versus gate voltage curve, which remains up to higher temperatures for a smaller wire, suggests that a strong one‐dimensional transport effect occurs in this silicon wire.

Mechanism of leakage current through the nanoscale SiO2 layer

Abstract: We clarify the mechanism of leakage current through the nanoscale ultrathin silicon dioxide (SiO2) layer in a metal‐insulator‐semiconductor structure based on the multiple scattering theory when technologically important phosphorus doped polycrystalline silicon is adopted as the gate electrode. We also derive an analytic expression for the direct tunneling current, and show that its measurement presents an excellent opportunity to determine the effective mass of an electron in the SiO2.

Semiconductor device with monocrystalline gate insulating film

Abstract: A semiconductor device includes a monocrystalline silicon substrate, an insulating film consisting of a monocrystalline silicon oxide formed on the surface of the monocrystalline silicon substrate, and a conductive film formed on the insulating film. The monocrystalline silicon substrate has a (100) plane orientation, the insulating film essentially consists of β-cristobalite having a unit structure in a P4 1 2 1 2 structural expression in such a manner that every other silicon atoms of four silicon atoms aligned about a C-axis are arranged on two adjacent silicon atoms aligned in a 110! direction on an Si (100) plane, and that a plane including the C-axis of the β-cristobalite and the 110! direction is set perpendicular to the (100) plane.

Lateral photovoltaic effect in porous silicon

Abstract: Porous silicon has received considerable attention for its potential as a silicon‐based visible light emitter In this letter we introduce the lateral photovoltaic effect in porous silicon and show its origin in amphoteric dangling bond traps at the porous silicon surface, which also play a role in the light‐induced photoluminescence degradation The use of the lateral photoeffect for a wide area position‐sensitive visible light detector is demonstrated The lateral photoeffect also provides a new electrical technique to study the atmospheric interactions of porous silicon, with possible applications for vapor detection

Method for fabricating a semiconductor device using a porous silicon region

Abstract: A method for fabricating a silicon diaphragm comprises the steps of preparing an n-type silicon substrate; diffusing n+ impurities in the silicon substrate to form an n+ diffusion region in a part of the upper wall thereof; growing an n-type silicon epitaxial layer thereon; forming a through-hole in the n-type silicon epitaxial layer to expose a part of the n+ diffusion region; performing an anodic reaction in an HF solution to make the n+ diffusion region a porous silicon layer; etching the porous silicon layer to form an air-gap;and, sealing the through-hole.

Nitride cap sidewell oxide protection from BOE etch

Abstract: A new method of forming a self-aligned contact is achieved. A pattern of polysilicon gate electrode stack including a silicon oxide gate dielectric, a polysilicon gate electrode, a first thermal polyoxide layer over the top of said polysilicon gate electrode layer, a first silicon nitride layer over said first thermal polyoxide layer, and a TEOS layer over said silicon nitride layer is provided on a silicon substrate. Each of the layers has its side open to the ambient. Inert ions are implanted into the substrate which is not covered by the polysilicon gate electrode stack in such a manner as to reduce the possibility of the oxidation of the surface of the substrate. The pattern of polysilicon gate electrode stack and the surface of the said substrate are subjected to a thermal oxidizing ambient which causes oxidation of the sides open to the ambient of the polysilicon layer to form a second polyoxide layer on the sides of the polysilicon layer. A second silicon nitride layer is formed over the pattern of stack and the surface of the substrate. The second silicon nitride layer is anisotropically etched to remove the second silicon nitride from the top of the stack and from over the surface of the substrate while leaving the second silicon nitride layer remaining upon the sides of the stack to form a self-aligned opening to regions within the silicon substrate. A self-aligning contact to the regions is formed through said opening.

Method for fabricating a vertical bipolar transistor with reduced parasitic capacitance between base and collector regions

Abstract: A method of fabricating a vertical bipolar semiconductor device includes a step of forming an N - -type silicon epitaxial layer which constitutes a part of a collector region and a P + -type polycrystalline silicon film which functions as a base lead-out electrode. The silicon epitaxial layer and the polycrystalline silicon film are insulated by a silicon oxide film which is a sufficiently thick insulating film, covers the silicon epitaxial layer and has an opening. In this opening, by selective growth of a first and a second semiconductor film and ion implantation using a first insulating film spacer, there are formed a P - -type single crystal silicon layer, a P + -type polycrystalline silicon film, a P + type single crystal silicon layer (intrinsic base region), a P + -type polycrystalline silicon film, and an N-type single crystal silicon layer. It is possible to reduce the parasitic capacitance between the base region and the collector region without sacrificing the enhancement of the cut-off frequency f T .

Silicon carbide semiconductor devices having buried silicon carbide conduction barrier layers therein

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, an active layer in the substrate and a silicon carbide buried layer which provides a conduction barrier between the substrate and at least a portion of the active layer. The buried layer is preferably formed by implanting second conductivity type dopants into the substrate so that a P-N junction barrier is provided between the active layer and the substrate. The buried layer may also be formed by implanting electrically inactive ions into the substrate so that a relatively high resistance barrier is provided between the active layer and the substrate. The electrically inactive ions are preferably selected from the group consisting of argon, neon, carbon and silicon, although other ions which are electrically inactive in silicon carbide may be used. The implantation of the electrically inactive ions is designed to cause the formation of a large number of electrically active deep level defects in the buried layer, particularly near the peak of the implant profile which is Gaussian in shape. These steps can be utilized in the formation of a variety of silicon carbide semiconductor devices such as lateral field effect devices and devices having both vertical and lateral active regions which are designed for high power applications. In particular, lateral silicon carbide-on-insulator enhancement and depletion mode field effect transistors (FFTs) can be formed in accordance with the present invention. Vertical silicon carbide power MESFET devices can also be formed by incorporating a silicon carbide source region in the active layer at the first face of a silicon carbide substrate and a drain region at the second face and by providing a Schottky barrier gate electrode on the first face.

Influence of surface defects on the electrical behavior of aluminum-porous silicon junctions

Abstract: Using transient‐current measurements on porous silicon layers made on p+ silicon substrate, we characterize the surface defects of the porous silicon material, i.e., the defects located at the interface between porous silicon and a thin layer of native oxide. An energy location near midgap (these defects can be efficient radiative lifetime killers) and a trap concentration in close agreement with the number of trivalent silicon defects—as measured by electron spin resonance—are deduced.

Process for forming field isolation and a structure over a semiconductor substrate

Abstract: An annealed amorphous silicon layer is formed prior to forming field isolation regions when using in a LOCOS field isolation process. The annealed amorphous silicon layer helps to reduce encroachment compared to conventional LOCOS field isolation process and helps to reduce the likelihood of forming pits within a substrate compared to a PBL field isolation process. The annealed amorphous silicon layer may be used in forming field isolation regions that defines the active regions between transistors including MOSFETs and bipolar transistors. Doped silicon or a silicon-rich silicon nitride layer may be used in place of conventional materials. The anneal of the amorphous silicon layer may be performed after forming a silicon nitride layer if the silicon nitride layer is deposited at a temperature no higher than 600 degrees Celsius.

Growth and Processing of Relaxed-Si1-xGex/Strained-Si Structures for Metal-Oxide Semiconductor Applications.

Abstract: Epitaxial growth and processing issues related to strained-Si metal-oxide semiconductor field effect transistor (MOSFET) fabrication are discussed. The material quality of the graded Ge composition, relaxed- Si1-x Gex buffer layers is analyzed. The ion implants used to form complementary metal-oxide semiconductor (CMOS) "wells" prior to epitaxy are found to degrade the quality of these layers by introducing a high density of misfit dislocation nucleation sites. Rough surface morphology, short misfit dislocation line lengths, and high threading defect densities are correlated with the increased nucleation site density. In addition, the oxidation of strained Si is investigated by Rutherford backscattering and Raman spectroscopy. No measurable strain relaxation is found as a result of thermal oxidation at temperatures up to 850° C.

SOI by large angle oxygen implant

Abstract: A new method of forming a silicon-on-insulator device using large tilt-angle implant is described. A first silicon oxide layer is formed on the surface of a semiconductor substrate. A first layer of tungsten is deposited over the silicon oxide layer and patterned. The semiconductor substrate is etched where it is not covered by the patterned tungsten layer to provide a silicon pillar underlying the patterned tungsten layer. A second silicon oxide layer is formed on all exposed surfaces of the silicon pillar and the silicon semiconductor substrate. A second tungsten layer is deposited over all surfaces of the substrate and anisotropically etched to form spacers on the sidewalls of the silicon pillar. An oxygen ion implantation is performed at a tilt angle to form implanted regions within the semiconductor substrate wherein the implanted regions extend and intersect under the silicon pillar. The tungsten layers are removed and the substrate is annealed wherein the implanted regions are transformed into silicon dioxide regions. The silicon oxide layers are removed to complete formation of the silicon-on-insulator device in the manufacture of an integrated circuit.

Method for forming a silicide using ion beam mixing

Abstract: An improved method is provided for fabricating a metal silicide upon a semiconductor substrate. The method utilizes ion beam mixing by implanting germanium to a specific elevation level within a metal layer overlying a silicon contact region. The implanted germanium atoms impact upon and move a plurality of metal atoms through the metal-silicon interface and into a region residing immediately below the silicon (or polysilicon) surface. The metal atoms can therefore bond with silicon atoms to cause a pre-mixing of metal with silicon near the interface in order to enhance silicidation. Germanium is advantageously chosen as the irradiating species to ensure proper placement of the germanium and ensuing movement of dislodged metal atoms necessary for minimizing oxides left in the contact windows and lattice damage within the underlying silicon (or polysilicon).

Phototransistor with quantum well base structure.

Abstract: A long wavelength (6 to 20 μm) phototransistor is described which has n-doped silicon as emitter and collector regions bracketing a base region having a quantum well structure made up of alternating layers of p-doped silicon germanium and undoped silicon, The silicon germanium layer adjacent to the emitter region is thicker and has a higher percentage of germanium in order to provide a quantum well that is wider and deeper than the other quantum wells in the base region thereby resulting in a larger current and optical gain. The silicon barrier layer of the quantum well closest to the collector region is p-doped in order to reduce the leakage current of the base-collector junction.

Method for forming silicon nitride film having low leakage current and high break down voltage

Abstract: The present invention provides a method for forming a silicon nitride film used for a capacitor dielectric film on a silicon substrate and a poly-silicon layer which comprises steps of forming a first thin silicon nitride film by a rapid thermal nitrogen process and forming a second silicon nitride film on the first thin silicon nitride film to a required thickness by LPCVD. In the LPCVD, a gas which reduces surface reactions is introduced to a growing surface of the silicon nitride film by a means different from a means supplying starting material gases of the silicon nitride film, so as to improve a break down voltage and leakage current of the capacitor silicon nitride film.