Showing papers on "Strained silicon published in 1997"

Bulk and strained silicon on insulator using local selective oxidation

Abstract: A method for forming buried oxide regions below a single crystal semiconductor layer incorporating the steps of forming epitaxial layers having different rates of oxidation with the lower layer having a faster rate of oxidation and oxidizing the layers through an opening in a mask. A plurality of oxide isolated FET's may be formed. The invention reduces the problem of source/drain parasitic capacitance and short channel effects while isolating FET's and eliminating floating body effects of an FET by selectively oxidizing semiconductor layers.

Microwave monolithic integrated circuit with coplaner waveguide having silicon-on-insulator composite substrate

Abstract: A microwave monolithic integrated circuit includes a coplanar waveguide (CPW) formed by a composite silicon structure constituted by a relatively high resistivity substrate, a first oxide layer on the upper surface thereof, a relatively thin silicon layer formed on the surface of the first oxide layer, and a very thin second oxide layer formed on the surface of the thin silicon layer. The silicon layer and the first oxide layer on which it is formed constitutes a silicon-on-insulator or SOI structure. A metallic signal line and ground planes are bonded to the surface of the second oxide layer. The zone of the thin silicon layer which extends between the ground planes is doped with an active impurity to produce high conductivity therein. As a result, the electric component of a quasi-TEM wave traversing the waveguide is substantially restricted to the thin silicon layer and does not penetrate to the underlying bulk silicon substrate. This achieves significantly reduced transmission loss and a quality factor Q in the vicinity of 17 for the CPW. Passive and active circuits may be formed in regions of the thin silicon layer other than those used for the CPW.

Fabrication of nanoelectromechanical systems in single crystal silicon using silicon on insulator substrates and electron beam lithography

Abstract: We have demonstrated a process for fabricating nanometer-scale electromechanical structures of diverse geometries in single crystal silicon, using silicon on insulator substrates. We pattern the substrate using high resolution electron beam lithography with 100 keV electrons followed by Al evaporation and liftoff. The Al is used as an etch mask in CF4 reactive ion etching to pattern the top silicon layer. We then undercut structures using a buffered oxide etch. The structures were made from substrates having a top silicon thickness of 200 or 50 nm, and a buried oxide thickness of 400 nm. With this process we have made a variety of movable structures. We describe the performance of an electrostatically driven Fabry–Perot interferometer that consists of a μm sized pad suspended by wires that are 100–200 nm wide. We have also made much smaller mechanical structures such as suspended silicon beams as narrow as 30 nm.

Accurate method for the determination of bulk minority-carrier lifetimes of mono- and multicrystalline silicon wafers

Abstract: An accurate method for the determination of the bulk minority-carrier recombination lifetime of crystalline silicon wafers of typical thickness (<0.5 mm) is presented. The method consists of two main steps: first, both wafer surfaces are passivated with silicon nitride films fabricated at low temperature (<400 °C) in a remote plasma-enhanced chemical vapor deposition system. Second, the effective minority-carrier lifetime of the wafer is measured by means of the contactless microwave-detected photoconductance decay technique. Due to the outstanding degree of surface passivation provided by remote-plasma silicon nitride films, the bulk minority-carrier lifetime can be very accurately determined from the measured effective minority-carrier lifetime. The method is suited for the bulk minority-carrier lifetime determination of p-type and n-type silicon wafers with doping concentrations in the 1014–1017 cm-3 range. We demonstrate the potential of the method for commercially available float-zone, Czochralski, a...

Low resistance power MOSFET or other device containing silicon-germanium layer

Abstract: A power MOSFET or other semiconductor device contains a layer of silicon combined with germanium to reduce the on-resistance of the device. The proportion of germanium in the layer is typically in the range of 1-40%. To achieve desired characteristics the concentration of germanium in the Si-Ge layer can be uniform, stepped or graded. In many embodiments it is desirable to keep the germanium below the surface of the semiconductor material to prevent germanium atoms from being incorporated into a gate oxide layer. This technique can be used in vertical DMOS and trench-gated MOSFETs, quasi-vertical MOSFETs and lateral MOSFETs, as well as insulated gate bipolar transistors, thyristors, Schottky diodes and conventional bipolar transistors.

Method and apparatus for reducing isolation stress in integrated circuits

Abstract: Stress resulting from silicon nitride is diminished by forming an oxidation mask with silicon nitride having a graded silicon concentration. Grading is accomplished by changing the silicon content in the silicon nitride by varying the amount of hydride, such as dichlorosilane (DCS), mixed with ammonia. The silicon nitride can be graded in a substantially linear or non-linear fashion. Silicon nitride formed with higher levels of DCS mixed with ammonia is referred to as silicon rich nitride because of its relatively higher silicon content. In one embodiment, the graded silicon nitride may be formed with one type of non-linear silicon grading, an abrupt junction. In other embodiments, the silicon nitride is formed in a variety of shapes fashioned during or after silicon nitride growth. In one embodiment, the stress from the silicon nitride is reduced by forming a polysilicon buffer layer between two silicon nitride layers. In another embodiment, the stress from the silicon nitride is reduced by forming the silicon nitride on a pad layer, which in turn is formed on a base layer.

Assessment and parameterisation of Coulomb-enhanced Auger recombination coefficients in lowly injected crystalline silicon

Abstract: In traditional band-to-band Auger recombination theory, the low-injection carrier lifetime is an inverse quadratic function of the doping density. However, for doping densities below about 3 ×1018 cm−3, the low-injection Auger lifetimes measured in the past on silicon were significantly smaller than predicted by this theory. Recently, a new theory has been developed [A. Hangleiter and R. Hacker, Phys. Rev. Lett. 65, 215 (1990)] that attributes these deviations to Coulombic interactions between mobile charge carriers. This theory has been supported experimentally to a high degree of accuracy in n-type silicon; however, no satisfactory support for it has been found in p-type silicon for doping densities below 3×1017 cm−3. In this work, we investigate the most recent lifetime measurements of crystalline silicon and support experimentally the Coulomb-enhanced Auger theory in p-type silicon in the doping range down to 1×1016 cm−3. Based on the experimental data, we present an empirical parameterisation of the low-injection Auger lifetime. This parameterisation is valid in n- and p-type silicon with arbitrary doping concentrations and for temperatures between 70 and 400 K. We implement this parameterisation into a numerical device simulator to demonstrate how the new Auger limit influences the open-circuit voltage capability of silicon solar cells. Further, we briefly discuss why the Auger recombination rates are less enhanced under high-injection conditions than under low-injection conditions.

Si nanowire growth with ultrahigh vacuum scanning tunneling microscopy

Abstract: Using a scanning tunneling microscope (STM), Si nanowires were grown by applying a voltage at a constant current between a Si substrate and a gold STM tip. Silicon atoms were deposited onto a gold tip by field evaporation. The field evaporation rate of silicon atoms was activated by heating the substrate. Silicon nanowire was grown on the gold tip at a substrate temperature of 700 °C. Nanowires could not be grown on a clean tungsten tip when using a gold-free Si substrate. The presence of gold atoms is important for the growth of silicon. Apparently, gold atoms deposited on the silicon substrate by field evaporation reduce the activation energy of field evaporation by attacking Si–Si bonds.

Silicon carbide semiconductor device with trench

Abstract: A silicon carbide semiconductor device having a high blocking voltage, low loss, and a low threshold voltage is provided. An n+ type silicon carbide semiconductor substrate 1, an n- type silicon carbide semiconductor substrate 2, and a p type silicon carbide semiconductor layer 3 are successively laminated on top of one another. An n+ type source region 6 is formed in a predetermined region of the surface in the p type silicon carbide semiconductor layer 3, and a trench 9 is formed so as to extend through the n+ type source region 6 and the p type silicon carbide semiconductor layer 3 into the n- type silicon carbide semiconductor layer 2. A thin-film semiconductor layer (n type or p type) 11a is extendedly provided on the surface of the n+ type source region 6, the p type silicon carbide semiconductor layer 3, and the n- type silicon carbide semiconductor layer 2 in the side face of the trench 9. A gate electrode layer 13 is disposed through a gate insulating layer 12 within the trench 9. A source electrode layer 15 is provided on the surface of the p type silicon carbide semiconductor layer 3 and on the surface of the n+ type source region 6, and a drain electrode layer 16 is provided on the surface of the n+ type silicon carbide semiconductor substrate 1.

Process for producing quantum fine wire

Abstract: A process of producing quantum fine wires, it is called silicon nanowires, too, which allows silicon quantum fine wires to grow into desirable shapes. In this process, gold is deposited on a silicon substrate to a thickness of 5 nm or less, and the silicon substrate is heated at a temperature of 450° C. to 650° C. in an atmosphere containing silane gas at a pressure less than 0.5 Torr, whereby drops of a molten alloy of silicon and gold are formed on the surface of the silicon substrate and the silane gas is decomposed by the action of the molten alloy drops as catalyst, to allow silicon quantum fine wires to grow into such desirable shapes as to be uniform in diameter without any bending.

Fabrication of planar silicon nanowires on silicon-on-insulator using stress limited oxidation

Abstract: A new method is proposed for the fabrication of planar single crystal silicon nanowires down to 8 nm in diameter. In this method silicon lines are defined on silicon-on-insulator with electron beam lithography followed by a metal liftoff process and a silicon plasma etch. Low temperature oxidation is then used to shrink these lines to a sub-10 nm diameter. Normal stress generated by the expansion of the viscous oxide during oxidation eventually stops the reaction, leaving a small silicon core at the center of the line. The effect of the crystallographic orientation of the line and the stress complications caused by the substrate are investigated.

Method for operating a non-volatile memory cell arrangement

Abstract: In order to increase the storage density, in a memory cell arrangement having MOS transistors as memory cells which has as gate dielectric, a dielectric triple layer having a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer, the silicon oxide layers each having a thickness of at least 3 nm, the information is stored using multi-value logic with up to 26 values. In this case, use is made of the fact that these memory cells have a time period greater than 1000 years for data retention and their threshold voltage has a very small drift.

Manufacturing method of semiconductor integrated circuit

Abstract: A manufacturing method of a semiconductor integrated circuit utilizing a trench isolated region to control the occurrence of parasitic transistors without narrowing the element region by forming first and second openings 4A, 4B on a silicon substrate for the purpose of element isolation, forming an amorphous silicon film thereon, then leaving the amorphous silicon film behind only a surface of a side wall of the opening by performing anisotropy etching. After oxidizing the surface of the amorphous silicon film and inside base, the opening is filled with a silicon oxide film.

Hole mobility improvement in silicon-on-insulator and bulk silicon transistors using local strain

Abstract: Summary form only given Improvements in transport properties through strain have been demonstrated in the operating characteristics of field-effect transistors in the Ga/sub 1-x/In/sub x/As/GaAs and the SiGe/Si system For CMOS, an improvement in p-channel device characteristics is desirable, and the hole mobility is an appropriate tool for attaining it Si on relaxed SiGe is one system where such an improvement occurs and has been observed Here, we discuss how changes in mobility and p-channel device properties can be deliberately made in silicon and silicon-on-insulator (SOI) structures through the introduction of local strain and without a major change in the underlying isolation techniques Effective mobility changes of up to 40% have been observed for device widths of 1 /spl mu/m in silicon-on-insulator structures

MOSFET with self-aligned silicidation and gate-side air-gap structure

Abstract: The method of the present invention includes forming a silicon dioxide layer. A polysilicon layer is then deposited on the silicon dioxide layer. Next, a gate structure is formed by etching. A silicon oxynitride layer is formed on the substrate and covers the gate structure. Silicon nitride side-wall spacers are formed on the side walls of the gate. An amorphous silicon layer is formed on the substrate, the side-wall spacers, and top of the polysilicon gate. Then, the source and the drain are formed. A wet oxidation is subsequently carried out to convert the amorphous silicon into a doped oxide layer. An etching process is then utilized to etch the oxide layer. Therefore, oxide side-wall spacers are formed on the silicon nitride side-wall spacers. Then, a metal silicide layer is formed on top of the gate, and on the source and the drain. The silicon nitride side-wall spacers are removed to form air gaps between the gate and the side-wall spacers. Then, a low energy pocket ion implantation is performed to doped ions into the substrate via the air gaps. Next, an oxide is formed on the substrate, spacers and over the gate. Then, a rapid thermal process (RTP) is carried out for annealing.

Interpoly dielectric process

Abstract: A process is provided for fabricating a nonvolatile memory cell. According to the process, source and drain regions are formed on a first conductivity-type semiconductor substrate; and insulating layer is formed on the source and drain regions; a floating gate is formed on the insulating layer; a dielectric composite is formed on the floating gate; and a control gate is formed on the dielectric composite. The dielectric composite includes a bottom layer of silicon dioxide formed on the floating gate; a layer of silicon nitride formed on the bottom silicon dioxide layer; and a top layer of silicon dioxide formed on the nitride layer such that the silicon nitride layer of the composite is thinner than the top or the bottom silicon dioxide layer.

Silicon carbide formation by annealing C60 films on silicon

Abstract: Silicon carbide films were grown on (100) silicon substrates by deposition of 200-nm-thick C60 films, followed by annealing. The predeposited C60 is progressively destroyed by annealing, and carbon reacts with silicon to produce SiC. The reaction starts at the interface and continues by diffusion of silicon through the already formed SiC. At the lower temperatures (700 °C), the reaction is localized at the interface. Diffusion of silicon and formation of stoichiometric SiC requires annealing at 800 °C for t⩾100 min and at 900 °C for t⩾25 min. The stoichiometric films are uniform with a grain size of 20–40 nm. A diffusion coefficient of silicon in SiC of 4×10−15 cm2/s at 900 °C was determined. Because the diffusion of silicon is faster through preferential paths in the SiC film, such as grain boundaries and other crystalline defects, pits and voids are produced in the silicon substrate when the C60 predeposited film covers larger areas.

Multi-layer silicon nitride deposition method for forming low oxidation temperature thermally oxidized silicon nitride/silicon oxide (no) layer

Abstract: A method for forming a silicon nitride/silicon oxide (NO) layer within a microelectronics fabrication, and the microelectronics fabrication having the silicon nitride/silicon oxide (NO) layer formed therein. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a first silicon nitride layer through a first deposition method. There is then formed upon the first silicon nitride layer a second silicon nitride layer through a second deposition method. Finally, there is annealed thermally in an oxidizing environment the first silicon nitride layer and the second silicon nitride layer to form therefrom a silicon nitride/silicon oxide (NO) layer. The silicon nitride/silicon oxide (NO) layer may be formed with optimized resistivity properties at a reduced thermal annealing temperature and/or a reduced thermal annealing exposure time in comparison with an otherwise equivalent silicon nitride/silicon oxide (NO) layer formed through thermal annealing a single silicon nitride layer of thickness equivalent to the thickness of the first silicon nitride layer plus the thickness of the second silicon nitride layer. When formed upon a silicon oxide dielectric layer in turn formed upon a first capacitor plate within a capacitor within an integrated circuit, there may be formed employing the silicon nitride/silicon oxide (NO) layer a silicon oxide/silicon nitride/silicon oxide (ONO) capacitive dielectric layer.

Semiconductor device organic insulator film

Abstract: An interlayer insulating film of a semiconductor device is made of a material in which silicon atoms are main elements, and each of the silicon atoms has an oxygen bond and a carbon bond, and further at least some of the silicon atoms have a hydrogen bond. The interlayer insulating film is formed by chemical vapor deposition employing a mixed gas of hydrogen peroxide and a reactive gas having a gas molecular structure in which silicon atoms have a hydrogen bond and a carbon bond.

Fabrication process of semiconductor device

Abstract: After forming an isolation layer and a well region on and in a silicon substrate, a gate oxide layer, a gate electrode of polycrystalline silicon and an oxide layer on the gate electrode are formed. Subsequently, a side wall of a nitride layer is formed. Then, the oxide layer on the gate electrode is removed. Next, selective growth of impurity doped silicon is performed at a temperature lower than or equal to 800° C. to form an elevated source-drain region in a source-drain region. Also, a polycrystalline silicon layer is formed on the gate electrode. Thereafter, by performing heat treatment, the impurity is diffused from the source-drain region to the surface of the silicon substrate to form a source-drain diffusion layer. Simultaneously, conductivity is provided to the entire gate electrode by diffusing impurity from the polycrystalline silicon layer to the gate electrode.

Multilayer ONO structure

Abstract: Dielectric structures of the type that might be used in DRAMs, other memory devices, and integrated thin film transistors include repeated silicon oxide/silicon nitride layers. For example, the dielectric structure may have a silicon oxide/silicon nitride/silicon oxide/silicon nitride/silicon oxide or "ONONO" layer structure. Such repeated layer structures exhibit higher levels of breakdown voltage than more conventional "ONO" structures. Most of the growth of the five layer ONONO or more complicated dielectric structure can be accomplished in a single furnace through a series of temperature steps performed under different gas ambients. A substrate having a polysilicon lower electrode is introduced to a furnace and a lowest layer of silicon oxide is grown on the polysilicon electrode in an ammonia ambient. A first silicon nitride layer is grown in NH 3 and SiH 2 Cl 2 and then growth of the first silicon nitride layer is interrupted by first altering or stopping the flow of reaction gases and then growing an intermediate silicon oxide layer on the first silicon nitride layer, again in an ammonia ambient. A second silicon nitride layer is then formed by reintroducing the same combination of processing gases. Growth of the second silicon nitride layer is then interrupted, and either additional repetitions of the silicon oxide/silicon nitride layer structure are formed or a surface layer of silicon oxide is grown in a steam or wet oxygen ambient.

Method of implanting silicon through a polysilicon gate for punchthrough control of a semiconductor device

Abstract: A region of damaged silicon is exploited as a gettering region for gettering impurities in a silicon substrate. The region of damaged silicon is formed between source and drain regions of a device by implanting silicon atoms into the silicon substrate after the formation of a gate electrode of the device. The damaged region is subsequently annealed and, during the annealing process, dopant atoms such as boron segregate to the region, locally increasing the dopant concentration in the region. The previously damaged region is in a location that determine the punchthrough characteristics of the device. The silicon implant for creating a gettering effect is performed after gate formation so that the region immediately beneath the junction is maintained at a lower dopant concentration to reduce junction capacitance. Silicon is implanted in the vicinity of a polysilicon gate to induce transient-enhanced diffusion (TED) of dopant atoms such as boron or phosphorus for control of punchthrough characteristics of a device. A punchthrough control implant is performed following formation of gate electrodes on a substrate using a self-aligned gettering implant.

Silicon carbide power MESFET with surface effect supressive layer

Abstract: A silicon carbide metal semiconductor field effect transitor fabricated on silicon carbide substrate with a layer which suppresses surface effects, and method for producing same. The surface-effect-suppressive layer may be formed on exposed portions of the transistor channel and at least a portion of each contact degenerate region. The surface-effect-suppressive layer may be made of undoped silicon carbide or of an insulator, such as silicon dioxide or silicon nitride. If the surface-effect-suppressive layer is made of silicon dioxide, it is preferred that the layer be fabricated of a combination of thermally-grown and chemical vapor deposition deposited silicon dioxide.

Diffusion barrier for polysilicon gate electrode of MOS device in integrated circuit structure, and method of making same

Abstract: A uniformly doped polysilicon gate electrode of an MOS device forming a part of an integrated circuit structure on a semiconductor substrate is formed by first depositing a very thin layer of amorphous or polycrystalline silicon, e.g., from about 2 nm to about 10 nm, over a gate oxide layer. The thin layer of silicon layer is then exposed to a nitrogen plasma formed from N2 at a power level sufficient to break the silicon--silicon bonds in the thin layer of silicon, but insufficient to cause sputtering of the silicon to cause a barrier layer of silicon and nitrogen to form at the surface of the thin silicon layer. Further silicon, e.g., polysilicon, is then deposited over the barrier layer to the desired thickness of the polysilicon gate electrode. The gate electrode is then conventionally doped, i.e., by implantation followed by furnace annealing, to diffuse and activate the dopant in the polysilicon gate electrode without, however, resulting in penetration of the dopant through the barrier layer into the underlying gate oxide layer or the semiconductor substrate.

Method of manufacturing a crystalline semiconductor

Abstract: A silicon oxide film is used as a mask covering an amorphous silicon film. A film having a catalyst element such as nickel for promoting crystallization is formed. When heat annealing is applied, the catalyst element diffuses from the aperture into the amorphous silicon film to obtain a crystalline silicon film. The silicon film has uniformly orientated crystals. Then, a halogen-containing gas (for example, hydrogen chloride) is introduced while the mask in place. In this step, the atmosphere and the temperature are controlled to form, on the silicon film in the portion of the aperture, an oxide film of such a thickness as allowing the catalyst element to pass but not etching the silicon film. The catalyst element in the silicon film is removed by halogen through the aperture, but the crystallinity of silicon does not change. Thus, a silicon film of good crystallinity can be obtained.

The role of extra-atomic relaxation in determining Si 2p binding energy shifts at silicon/silicon oxide interfaces

Abstract: The observed binding energy shift for silicon oxide films grown on crystalline silicon varies as a function of film thickness. The physical basis of this shift has previously been ascribed to a variety of initial state effects (Si–O ring size, strain, stoichiometry, and crystallinity), final state effects (a variety of screening mechanisms), and extrinsic effects (charging). By constructing a structurally homogeneous silicon oxide film on silicon, initial state effects have been minimized and the magnitude of final state stabilization as a function of film thickness has been directly measured. In addition, questions regarding the charging of thin silicon oxide films on silicon have been addressed. From these studies, it is concluded that initial state effects play a negligible role in the thickness-dependent binding energy shift. For the first ∼30 A of oxide film, the thickness-dependent binding energy shift can be attributed to final state effects in the form of image charge induced stabilization. Beyond...

Clathrate structure for electronic and electro-optic applications

Abstract: A method including the steps of (a) depositing a metal layer on a selected portion of a silicon substrate under a first set of predetermined conditions to form an metal silicide layer and an intermediate n-type silicon layer; and (b) exposing the metal silicide layer and the n-type silicon layer to a second set of predetermined conditions to form a silicon clathrate film on the selected portion of the silicon substrate, where the intermediate n-type silicon layer acts to bond the silicon clathrate to the silicon substrate to form a silicon clathrate structure.

Analysis of electrical characteristics of polycrystalline silicon thin-film transistors under static and dynamic conditions

Abstract: Polycrystalline silicon TFT technology is rapidly emerging for large-area electronic applications, because of the relatively large mobility values of charge carriers with respect to the corresponding values in amorphous silicon. In contrast, because of the complex energy distribution of localized states within the energy gap, and the resulting space-charge effects, the TFT electrical characteristics are difficult to model, and a numerical approach is needed in order to better understand the physical effects which influence the device performances. In this article we perform numerical simulations of TFTs at different temperatures under static and dynamic conditions and, by fitting experimental data, extract the energy distribution and the capture cross-section of the grain-boundary traps and the parameters of the impact-ionization model. As opposed to single-crystal silicon SOI devices, we find that the TFT current and transconductance increase as temperature increases.

Method of making a field effect transistor having an elevated source and an elevated drain

Abstract: A method of forming a field effect transistor relative to a monocrystalline silicon substrate, where the transistor has an elevated source and an elevated drain, includes: a) providing a transistor gate over the monocrystalline silicon substrate, the gate being encapsulated in electrically insulative material; b) providing outer exposed monocrystalline silicon substrate surfaces adjacent the transistor gate; c) cleaning the outer exposed substrate surfaces to remove oxide and impurities therefrom; d) within a rapid thermal chemical vapor deposition reactor and after the cleaning step, chemical vapor depositing a conductively doped non-polycrystalline silicon layer over the cleaned substrate surfaces adjacent the transistor gate, the non-polycrystalline silicon layer having an outer surface, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing; and e) after chemical vapor depositing, exposing the doped non-polycrystalline silicon layer to high temperature annealing conditions effective to, i) produce doped monocrystalline silicon extending outwardly from the substrate surface, and ii) produce doped polycrystalline silicon extending inwardly from the outer surface; the doped monocrystalline silicon and doped polycrystalline silicon joining at an interface which is displaced elevationally outward of the substrate surfaces. A field effect transistor is also claimed.