Showing papers on "Strained silicon published in 2003"

High Performance Silicon Nanowire Field Effect Transistors

Abstract: Silicon nanowires can be prepared with single-crystal structures, diameters as small as several nanometers and controllable hole and electron doping, and thus represent powerful building blocks for nanoelectronics devices such as field effect transistors. To explore the potential limits of silicon nanowire transistors, we have examined the influence of source-drain contact thermal annealing and surface passivation on key transistor properties. Thermal annealing and passivation of oxide defects using chemical modification were found to increase the average transconductance from 45 to 800 nS and average mobility from 30 to 560 cm 2 /V‚s with peak values of 2000 nS and 1350 cm 2 /V‚s, respectively. The comparison of these results and other key parameters with state-of-the-art planar silicon devices shows substantial advantages for silicon nanowires. The uses of nanowires as building blocks for future nanoelectronics are discussed.

A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors

Abstract: This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions Dramatic performance enhancement relative to unstrained devices are reported These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 12nm physical gate oxide and Ni salicide World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/) and 800/spl mu/A//spl mu/m (low V/sub T/) at 12V are demonstrated NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region High NMOS drive currents of 126mA//spl mu/m (high VT) and 145mA//spl mu/m (low VT) at 12V are reported The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families

Semiconductor transistor having a stressed channel

Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

Fabrication and mobility characteristics of ultra-thin strained Si directly on insulator (SSDOI) MOSFETs

Abstract: A tensile-strained Si layer was transferred to form an ultra-thin (<20 nm) strained Si directly on insulator (SSDOI) structure. MOSFETs were fabricated, and for the first time, electron and hole mobility enhancements were demonstrated on strained Si directly on insulator structures with no SiGe layer present under the strained Si channel.

Method for forming a double-gated semiconductor device

Abstract: A method for forming a polysilicon FinFET (10) or other thin film transistor structure includes forming an insulative layer (12) over a semiconductor substrate (14). An amorphous silicon layer (32) forms over the insulative layer (12). A silicon germanium seed layer (44) forms in association with the amorphous silicon layer (32) for controlling silicon grain growth. The polysilicon layer arises from annealing the amorphous silicon layer (32). During the annealing step, silicon germanium seed layer (44), together with silicon germanium layer (34), catalyzes silicon recrystallization to promote growing larger crystalline grains, as well as fewer grain boundaries within the resulting polysilicon layer. Source (16), drain (18), and channel (20) regions are formed within the polysilicon layer. A double-gated region (24) forms in association with source (16), drain (18), and channel (20) to produce polysilicon FinFET (10).

Pmos transistor strain optimization with raised junction regions

Abstract: Optimal strain in the channel region of a PMOS transistor is provided by silicon alloy material in the junction regions of the device in a non-planar relationship with the surface of the substrate. The silicon alloy material, the dimensions of the silicon alloy material, as well as the non-planar relationship of the silicon alloy material with the surface of the substrate are selected so that the difference between the lattice spacing of the silicon alloy material and of the substrate causes strains in the silicon alloy material below the substrate surface, as well as above the substrate surface, to affect an optimal silicon alloy induced strain in the substrate channel. In addition, the non-planar relationship may be selected so that any strains caused by different lattice spaced layers formed over the silicon alloy material have a reduced effect on the strain in the channel region.

Strained silicon finFET device

Abstract: Disclosing is a strained silicon finFET device having a strained silicon fin channel in a double gate finFET structure. The disclosed finFET device is a double gate MOSFET consisting of a silicon fin channel controlled by a self-aligned double gate for suppressing short channel effect and enhancing drive current. The silicon fin channel of the disclosed finFET device is a strained silicon fin channel, comprising a strained silicon layer deposited on a seed fin having different lattice constant, for example, a silicon layer deposited on a silicon germanium seed fin, or a carbon doped silicon layer deposited on a silicon seed fin. The lattice mismatch between the silicon layer and the seed fin generates the strained silicon fin channel in the disclosed finFET device to improve hole and electron mobility enhancement, in addition to short channel effect reduction characteristic inherently in a finFET device.

Ballistic transport in high electron mobility transistors

Abstract: A general ballistic FET model that was previously used for ballistic MOSFETs is applied to ballistic high electron mobility transistors (HEMTs), and the results are compared with experimental data for a sub-50 nm InAlAs-InGaAs HEMT. The results show that nanoscale HEMTs can be modeled as an intrinsic ballistic transistor with extrinsic source/drain series resistances. We also examine the "ballistic mobility" concept, a technique proposed for extending the drift-diffusion model to the quasi-ballistic regime. Comparison with a rigorous ballistic model shows that under low drain bias the ballistic mobility concept, although nonphysical, can be used to understand the experimental phenomena related to quasi-ballistic transport, such as the degradation of the apparent carrier mobility in short channel devices. We also point out that the ballistic mobility concept loses validity under high drain bias. The conclusions of this paper should be also applicable to other nanoscale transistors with high carrier mobility, such as carbon nanotube FETs and strained silicon MOSFETs.

Semiconductor devices having strained dual channel layers

Abstract: A semiconductor structure includes a strain-inducing substrate layer having a germanium concentration of at least 10 atomic %. The semiconductor structure also includes a compressively strained layer on the strain-inducing substrate layer. The compressively strained layer has a germanium concentration at least approximately 30 percentage points greater than the germanium concentration of the strain-inducing substrate layer, and has a thickness less than its critical thickness. The semiconductor structure also includes a tensilely strained layer on the compressively strained layer. The tensilely strained layer may be formed from silicon having a thickness less than its critical thickness. A method for fabricating a semiconductor structure includes providing a substrate, providing a compressively strained semiconductor on the substrate, depositing a tensilely strained semiconductor adjacent the substrate until a thickness of a first region of the tensilely strained semiconductor is greater than a thickness of a second region of the tensilely strained semiconductor, forming a n-channel device on the first region, and forming a p-channel device on the second region.

Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel mosfets

Abstract: A method of fabricating a circuit comprising an nMOSFET includes providing a substrate, depositing a strain-inducing material comprising germanium over the substrate, and integrating a pMOSFET on the substrate, the pMOSFET comprising a strained channel having a surface roughness of less than 1 nm. The strain-inducing material is proximate to and in contact with the pMOSFET channel, the strain in the pMOSFET channel is induced by the strain-inducing material, and a source and a drain of the pMOSFET are at least partially formed in the strain-inducing material.

Method of forming strained silicon on insulator substrate

Abstract: A method of forming a strained-silicon-on-insulator substrate is disclosed. A target wafer includes an insulator layer on a substrate. A donor wafer includes a bulk semiconductor substrate having a lattice constant different from a lattice constant of silicon and a strained silicon layer formed on the bulk semiconductor substrate. The top surface of the donor wafer is bonded to the top surface of the target wafer. The strained silicon layer is then separated from the donor wafer so that the strained silicon layer adheres to the target wafer. The bond between the strained silicon layer and the target wafer can then be strengthened.

Gallium nitride-based devices and manufacturing process

Abstract: A nitride semiconductor (34, 234) is grown on a silicon substrate (10, 210) by depositing a few mono-layers of aluminum (14,214) to protect the silicon substrate from ammonia used during the growth process, and then forming a nucleation layer (16, 216) from aluminum nitride and a buffer structure (32, 232) including multiple superlattices (18, 26, 218) of AlRGa(llR)N semiconductors having different compositions and having an intermediate layer (24, 224) of GaN or other Ga­rich nitride semiconductor. The resulting structure has superior crystal quality. The silicon substrate used in epitaxial growth may be removed before completion of the device so as to provide superior electrical properties in devices such as high-electron mobility transistors.

Room temperature nanocrystalline silicon single-electron transistors

Abstract: Single-electron transistors operating at room temperature have been fabricated in 20-nm-thick nanocrystalline silicon thin films. These films contain crystalline silicon grains 4 – 8 nm in size, embedded in an amorphous silicon matrix. Our single-electron transistor consists of a side-gated 20 nm×20 nm point contact between source and drain electrodes. By selectively oxidizing the grain boundaries using a low-temperature oxidation and high-temperature argon annealing process, we are able to engineer tunnel barriers and increase the potential energy of these barriers. This forms a “natural” system of tunnel barriers consisting of silicon oxide tissues that encapsulate sub-10 nm size grains, which are small enough to observe room-temperature single-electron charging effects. The device characteristics are dominated by the grains at the point contact. The material growth and device fabrication process are compatible with silicon technology, raising the possibility of large-scale integrated nanoelectronic sys...

Insulated-gate field-effect transistor, method of fabricating same, and semiconductor device employing same

Abstract: With the invention, it is possible to avoid deterioration in short-channel characteristics, caused by a silicon germanium layer coming into contact with the channel of a strained SOI transistor. Further, it is possible to fabricate a double-gate type of strained SOI transistor or to implement mixedly mounting the strained SOI transistor and a conventional silicon or SOI transistor on the same wafer. According to the invention, for example, a strained silicon layer is grown on a strain-relaxed silicon germanium layer, and subsequently, portions of the silicon germanium layer are removed, thereby constituting a channel layer in the strained silicon layer.

Removal of dangling bonds and surface states on silicon (001) with a monolayer of selenium

Abstract: Dangling bonds and surface states are inherent to semiconductor surfaces. By passivating dangling bonds on the silicon (001) surface with a monolayer of selenium, surface states are removed from the band gap. Magnesium contacts on selenium-passivated silicon (001) behave ohmically, as expected from the work function of magnesium and the electron affinity of silicon. After rapid thermal annealing and hot-plate annealing, magnesium contacts on selenium-passivated silicon (001) show better thermal stability than on hydrogen-passivated silicon (001), which is attributed to the suppression of silicide formation by selenium passivation.

Hetero integration of semiconductor materials on silicon

Abstract: High quality gallium arsenide (GaAs) (38) is grown over a thin germanium layer (26) and co-exists with silicon (40) for hetero-integration of devices. A bonded germanium wafer of silicon (22), oxide (24), and germanium (26) is formed and capped (30). The cap (30) and germanium layer (26) are partially removed so as to expose a silicon region (32) and leave a stack (31) of oxide, germanium, and capping layer on the silicon. Selective silicon is grown over the exposed silicon region. Silicon devices (36) are made in the selectively grown region of silicon (34). The remaining capping layer (30) is etched away to expose the thin layer of germanium (26). GaAs (38) is grown on the thin germanium layer (26), and GaAs devices (39) are built which can interoperate with the silicon devices (36).

A silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide

Abstract: A silicon-on-insulator (SOI) device with a strained silicon film (14) has a substrate (10), and a buried oxide layer (12) on the substrate (10). Silicon islands (18) are formed on the buried oxide layer (12), the silicon islands (18) being separated from each other by gaps (16). The buried oxide layer (12) has recesses (22) directly under the gaps (16). A material (24) fills the recesses and the gaps (16), this material (24) being different from the material forming the buried oxide layer (12). The material (24) induces a net amount of strain in the silicon islands (18), thereby modifying the electrical properties of carriers in the silicon film (14) and improving device performance.

Characterization of low-temperature processed single-crystalline silicon thin-film transistor on glass

Abstract: Single-crystalline silicon thin film on glass (cSOG) has been prepared using an "ion-cutting" based "layer-transfer" technique. Low-temperature processed thin-film transistors, fabricated both on cSOG and metal-induced laterally crystallized polycrystalline silicon, have been characterized and compared. The cSOG-based transistors performed comparatively better, exhibiting a significantly higher electron field-effect mobility (/spl sim/430 cm/sup 2//Vs), a steeper subthreshold slope and a lower leakage current that was also relatively insensitive to gate bias.

Epitaxial silicon and germanium on buried insulator heterostructures and devices

Abstract: Future microelectronics will be based upon silicon or germanium-on-insulator technologies and will require an ultrathin (<10 nm), flat silicon or germanium device layer to reside upon an insulating oxide grown on a silicon wafer. The most convenient means of accomplishing this is by epitaxially growing the entire structure on a silicon substrate. This requires a high quality crystalline oxide and the ability to epitaxially grow two dimensional, single crystal films of silicon or germanium on top of this oxide. We describe a method based upon molecular beam epitaxy and solid-phase epitaxy to make such structures and demonstrate working field-effect transistors on germanium-on-insulator layers.

Nonvolatile silicon/oxide/nitride/silicon/nitride/oxide/silicon memory

Abstract: A nonvolatile silicon/oxide/nitride/silicon/nitride/oxide/silicon (SONSNOS) structure memory device includes a first insulating layer and a second insulating layer stacked on a channel of a substrate, a first dielectric layer and a second dielectric layer formed on the first insulating layer and under the second insulating layer, respectively, and a group IV semiconductor layer, silicon quantum dots, or metal quantum dots interposed between the first dielectric layer and the second dielectric layer. The provided SONSNOS structure memory device improves a programming rate and the capacity of the memory.

Strained transistor integration for cmos

Abstract: Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.

Fabrication and quantum properties of nanostructured silicon

Abstract: Physical properties of nanostructured silicon are reviewed in comparison to those of single-crystalline silicon (c-Si) and amorphous silicon (a-Si). Particular emphases are placed on low-dimensional silicon chains (e.g. polysilane) and nanocrystalline silicon (nc-Si) particles (e.g. porous silicon (PS)). These materials can be obtained by nanofabrication technology based on chemical, electrochemical, or dry-processing techniques. Due to induced strong quantum confinement effects, the optical and related properties of nanostructured silicon become free from direct- and indirect-transition regime. Then various functions appear as a novel semiconducting system. Polysilane consisting of a linear silicon backbone chain and capped organo-substituents acts as a self-assembled quantum wire. Nanocrystalline porous silicon composed of highly packed isolated or interconnected silicon nanocrystallites with an average diameter of 2–3 nm efficiently luminesces visible light. Highly efficient electroluminescent nc-Si diodes have been fabricated based on silicon substrates. In addition, nc-Si devices operate as a negative-resistance diode with an electroluminescent behavior, a light-emissive nonvolatile memory, a ballistic electron emitter, and an ultrasound generator. Scientific significance and technological potential of silicon nanostructuring are discussed from viewpoints of exploring advanced materials and developing functional integration.

Low Schottky barriers on n-type silicon (001)

Abstract: It has been reported that no metal shows a Schottky barrier of less than 0.4 eV on n-type silicon (001). This is attributed to interface states between metal and silicon (001), which pin the interface Fermi level and make the Schottky barrier more or less independent of the metal work function. We demonstrate that, by terminating dangling bonds and relaxing strained bonds on the silicon (001) surface with a monolayer of selenium, low Schottky barriers can be obtained on n-type silicon (001). Aluminum and chromium show barrier heights of 0.08 and 0.26 eV on n-type silicon (001), respectively. These results agree well with the ideal Schottky barrier heights for aluminum and chromium on n-type silicon (001), but are significantly different from the experimental barrier heights known for four decades for these metals on n-type silicon (001).

Strained Si/strained Ge dual-channel heterostructures on relaxed Si0.5Ge0.5 for symmetric mobility p-type and n-type metal-oxide-semiconductor field-effect transistors

Abstract: By growing heterostructures that combine a surface strained Si layer with a buried strained Ge layer on Si0.5Ge0.5, we have fabricated metal-oxide-semiconductor field-effect transistors with mobility enhancement factors over bulk Si of 1.7–1.9 for electrons and 10–12 for holes. While high hole mobility can be attained in strained Si/strained Ge heterostructures grown on Si0.3Ge0.7, we have found the electron mobility in similarly grown heterostructures to be limited by defect scattering in the Si cap. Reducing the Ge content of the virtual substrate to Si0.5Ge0.5 and optimizing the strained Si and strained Ge layer thicknesses allowed the realization of devices where the p-channel mobility as a function of inversion density actually matches or exceeds the n-channel mobility.

Mechanically induced strain enhancement of metal-oxide-semiconductor field effect transistors

Abstract: Device characteristics and analysis are reported for strained silicon n- and p- channel partially depleted metal oxide semiconductor field effect transistors (MOSFETs) at 300 K. The devices were fabricated commercially on standard silicon-based silicon-on-insulator substrates and strain was applied mechanically after fabrication. Uniaxial tensile strain was applied within the elastic region using a back-end process and the relaxed structures were characterized under steady state conditions. Characterization was performed before and after straining. At ultralow strain levels (0.031%), pMOSFETs showed an increase in effective mobility μeff of 14.35% and an enhanced saturation current, Isat of 14.56%. An improvement in μeff of 15.19% and in Isat of 15.34% was observed for nMOSFETs strained by 0.039%. The latter die was debonded, released, and restressed at an elevated level of 0.052%. We observed an increased effective mobility μeff of 18.49% and Isat of 18.05%. Elastic uniaxial strain was fixed and characte...

Implementation of both high-hole and electron mobility in strained Si/strained Si 1-y Ge y on relaxed Si 1-x Ge x (x<y) virtual substrate

Abstract: High-hole and electron mobility in complementary channels in strained silicon (Si) on top of strained Si/sub 0.4/Ge/sub 0.6/, both grown on a relaxed Si/sub 0.7/Ge/sub 0.3/ virtual substrate is shown for the first time. The buried Si/sub 0.4/Ge/sub 0.6/ serves as a high-mobility p-channel, and the strained-Si cap serves as a high-mobility n-channel. The effective mobility, measured in devices with a 20-/spl mu/m gate length and 3.8-nm gate oxide, shows about 2.2/spl sim/2.5 and 2.0 times enhancement in hole and electron mobility, respectively, across a wide vertical field range. In addition, it is found that as the Si cap thickness decreased, PMOS transistors exhibited increased mobility especially at medium- and high-hole density in this heterostructure.

Influence of high channel doping on the inversion layer electron mobility in strained silicon n-MOSFETs

Abstract: In this letter, we investigate the dependence of electron inversion layer mobility on high-channel doping required for sub-50-nm MOSFETs in strained silicon (Si), and we compare it to co-processed unstrained Si. For high vertical effective electric field E/sub eff/, the electron mobility in strained Si displays universal behavior and shows enhancement of 1.5-1.7/spl times/ compared to unstrained Si. For low E/sub eff/, the mobility for strained Si devices decreases toward the unstrained Si data due to Coulomb scattering by channel dopants.

Group-IV Nanocluster Formation by Ion-Beam Synthesis

Abstract: A short review of our investigations devoted to the use of ion-beam-synthesized nanoclusters for silicon-based light emission and nonvolatile memory effects is presented. Blue-violet light emission is demonstrated based on Ge-implanted silicon dioxide layers thermally grown on silicon substrates. This version of silicon-based light emission relies on Ge-related defects in the amorphous ≡Si–O–Si≡ network. The photoluminescence and electroluminescence are excited by a singlet S0–S1 transition of a neutral oxygen vacancy and by electron injection from the silicon substrate into the silicon dioxide layer, respectively. Whereas the photoluminescence excitation is a well-known mechanism, for the case of electroluminescence an interpretation was performed for the first time in the course of our studies. It was found that the most probable way to excite luminescence centers is the impact excitation by hot electrons. Whereas the injection is explained by trap-assisted tunneling of electrons from the substrate into the oxide, the electrons will be transported via traps or in the SiO2 conduction band. The application of the silicon-based light-emitting devices for an integrated optocoupler arrangement is described. Another application of nanoclusters is based on the investigation of thin Si-implanted silicon dioxide layers for nonvolatile memory devices. First promising results demonstrate that the observed programming window can reach several volts and the devices exhibit excellent retention behavior. A 256 K-nv-SRAM is demonstrated showing a programming window of >1 V for write pulses of 12 V/8 ms.