Showing papers on "Strained silicon published in 2004"

A 90-nm logic technology featuring strained-silicon

Abstract: A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/ CDO for high-performance dense logic is presented. Strained silicon is used to increase saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10% and 25%, respectively. Using selective epitaxial Si/sub 1-x/Ge/sub x/ in the source and drain regions, longitudinal uniaxial compressive stress is introduced into the p-type MOSEFT to increase hole mobility by >50%. A tensile silicon nitride-capping layer is used to introduce tensile strain into the n-type MOSFET and enhance electron mobility by 20%. Unlike all past strained-Si work, the hole mobility enhancement in this paper is present at large vertical electric fields in nanoscale transistors making this strain technique useful for advanced logic technologies. Furthermore, using piezoresistance coefficients it is shown that significantly less strain (/spl sim/5 /spl times/) is needed for a given PMOS mobility enhancement when applied via longitudinal uniaxial compression versus in-plane biaxial tension using the conventional Si/sub 1-x/Ge/sub x/ substrate approach.

A logic nanotechnology featuring strained-silicon

Abstract: Strained-silicon (Si) is incorporated into a leading edge 90-nm logic technology . Strained-Si increases saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10 and 25%, respectively. The process flow consists of selective epitaxial Si/sub 1-x/Ge/sub x/ in the source/drain regions to create longitudinal uniaxial compressive strain in the p-type MOSFET. A tensile Si nitride-capping layer is used to introduce tensile uniaxial strain into the n-type MOSFET and enhance electron mobility. Unlike past strained-Si work: 1) the amount of strain for the n-type and p-type MOSFET can be controlled independently on the same wafer and 2) the hole mobility enhancement in this letter is present at large vertical electric fields, thus, making this flow useful for nanoscale transistors in advanced logic technologies.

The interface between silicon and a high- k oxide

Abstract: The ability of the semiconductor industry to continue scaling microelectronic devices to ever smaller dimensions (a trend known as Moore's Law) is limited by quantum mechanical effects: as the thickness of conventional silicon dioxide (SiO(2)) gate insulators is reduced to just a few atomic layers, electrons can tunnel directly through the films. Continued device scaling will therefore probably require the replacement of the insulator with high-dielectric-constant (high-k) oxides, to increase its thickness, thus preventing tunnelling currents while retaining the electronic properties of an ultrathin SiO(2) film. Ultimately, such insulators will require an atomically defined interface with silicon without an interfacial SiO(2) layer for optimal performance. Following the first reports of epitaxial growth of AO and ABO(3) compounds on silicon, the formation of an atomically abrupt crystalline interface between strontium titanate and silicon was demonstrated. However, the atomic structure proposed for this interface is questionable because it requires silicon atoms that have coordinations rarely found elsewhere in nature. Here we describe first-principles calculations of the formation of the interface between silicon and strontium titanate and its atomic structure. Our study shows that atomic control of the interfacial structure by altering the chemical environment can dramatically improve the electronic properties of the interface to meet technological requirements. The interface structure and its chemistry may provide guidance for the selection process of other high-k gate oxides and for controlling their growth.

Fet channel having a strained lattice structure along multiple surfaces

Abstract: A channel (16) of a FinFET (10) has a channel core (24) and a channel envelope (32), each made from a semiconductor material defining a different lattice structure to exploit strained silicon properties. A gate is coupled to the channel envelope through a gate dielectric. Exemplary materials are Si and SixGe1-x, wherein 78

Ultrahigh-density silicon nanobridges formed between two vertical silicon surfaces

Abstract: We report simultaneous lateral growth of a high density of highly oriented, metal-catalyzed silicon nanowires on a patterned silicon substrate and bridging of nanowires between two vertical silicon sidewalls, which can be developed into electrodes of an electronic device. After angled deposition of catalytic metal nanoparticles on one of two opposing vertical silicon surfaces, we used a metal-catalyzed chemical vapour deposition process to grow nanowires and eventually form mechanically robust 'nanobridges'. The growth and bridging of these nanowire arrays can be integrated with existing silicon processes. This method of connecting multiple nanowires between two electrodes offers the high surface-to-volume ratio needed for nanosensor applications.

Analytic band Monte Carlo model for electron transport in Si including acoustic and optical phonon dispersion

Abstract: We describe the implementation of a Monte Carlo model for electron transport in silicon. The model uses analytic, nonparabolic electron energy bands, which are computationally efficient and sufficiently accurate for future low-voltage s, 1V d nanoscale device applications. The electron-lattice scattering is incorporated using an isotropic, analytic phonon-dispersion model, which distinguishes between the optical/acoustic and the longitudinal/transverse phonon branches. We show that this approach avoids introducing unphysical thresholds in the electron distribution function, and that it has further applications in computing detailed phonon generation spectra from Joule heating. A set of deformation potentials for electron-phonon scattering is introduced and shown to yield accurate transport simulations in bulk silicon across a wide range of electric fields and temperatures. The shear deformation potential is empirically determined at Ju= 6.8 eV, and consequently, the isotropically averaged scattering potentials with longitudinal and transverse acoustic phonons are DLA= 6.39 eV and DTA= 3.01 eV, respectively, in reasonable agreement with previous studies. The room-temperature electron mobility in strained silicon is also computed and shown to be in better agreement with the most recent phonon-limited data available. As a result, we find that electron coupling with g-type phonons is about 40% lower, and the coupling with f-type phonons is almost twice as strong as previously reported. © 2004 American Institute of Physics . [DOI: 10.1063/1.1788838]

Method of depositing dielectric films

Abstract: A method of forming a silicon carbide layer for use in integrated circuit fabrication processes is provided. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and a dopant in the presence of an electric field. The as-deposited silicon carbide layer has a compressibility that varies as a function of the amount of dopant present in the gas mixture during later formation.

Method of preventing surface roughening during hydrogen prebake of SiGe substrates

Abstract: The invention forms an epitaxial silicon-containing layer on a silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface and avoids creating a rough surface upon which the epitaxial silicon-containing layer is grown. In order to avoid creating the rough surface, the invention first performs a hydrofluoric acid etching process on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. This etching process removes most of oxide from the surface, and leaves a first amount of oxygen (typically 1×1013-1×1015/cm2 of oxygen) on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. The invention then performs a hydrogen pre-bake process which heats the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface sufficiently to remove additional oxygen from the surface and leave a second amount of oxygen, less than the first amount, on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. The heating process leaves an amount of at least 5×1012/cm2 of oxygen (typically, between approximately 1×1013/cm2 and approximately 5×1013/cm2 of oxygen) on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. By leaving a small amount of oxygen on the silicon germanium, patterned strained silicon, or patterned silicon-on-insulator surface, the heating processes avoid changing the roughness of the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. Then the process of epitaxially growing the epitaxial silicon-containing layer on the silicon germanium, patterned strained silicon, or patterned silicon-on-insulator surface is performed.

Valley splitting in strained silicon quantum wells

Abstract: A theory based on localized-orbital approaches is developed to describe the valley splitting observed in silicon quantum wells. The theory is appropriate in the limit of low electron density and relevant for quantum computing architectures. The valley splitting is computed for realistic devices using the quantitative nanoelectronic modeling tool NEMO. A simple, analytically solvable tight-binding model reproduces the behavior of the splitting in the NEMO results and yields much physical insight. The splitting is in general nonzero even in the absence of electric field in contrast to previous works. The splitting in a square well oscillates as a function of S, the number of layers in the quantum well, with a period that is determined by the location of the valley minimum in the Brillouin zone. The envelope of the splitting decays as S−3. The feasibility of observing such oscillations experimentally in Si/SiGe heterostructures is discussed.

Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology

Abstract: We describe the device physics of uniaxial strained silicon transistors. Uniaxial strain is more effective, less costly and easier to implement. The highest PMOS drive current to date is reported: 0.72mA/ /spl mu/m. Pattern sensitivity and mobility/Rext partitioning are discussed. Finally we measure inverter delays as low as 4.6pS, and show 50Mb SRAMs operational at 0.65V.

Strained silicon fin field effect transistor

Abstract: Strained Si surrounding the SiGe embedded body on a SOI (silicon on insulator) substrate forms a novel FinFET. The mobility in the channel is enhanced due to strain of the Si channel. The strained Si FinFET includes a SOI substrate, an SiGe embedded body, a strained Si channel surrounding layer, an oxide layer, a poly Si gate electrode (or metal gate electrode), a source and a drain.

Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same

Abstract: High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Method for producing high throughput strained-Si channel MOSFETS

Abstract: A method for forming a strained silicon layer device with improved wafer throughput and low defect density including providing a silicon substrate; epitaxially growing a first silicon layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; epitaxially growing a step-grade SiGe buffer layer over and contacting the first silicon layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; epitaxially growing a SiGe capping layer over and contacting the step-grade SiGe buffer layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; and, epitaxially growing a second silicon layer using at least one deposition precursor selected from the group consisting of disilane and silane.

Silicon-on-insulator active pixel sensors

Abstract: Active pixel sensors are defined on double silicon on insulator (SOI) substrates such that a first silicon layer is selected to define radiation detection regions, and a second silicon layer is selected to define readout circuitry. The first and second silicon layers are separated by an insulator layer, typically an oxide layer, and the layers can be independently doped. Doping can be provided in the silicon layers of the SOI substrate during assembly of the SOI substrate, or later during device processing. A semiconductor substrate that supports the first and second layers can be removed for, for example, back side radiation detection, using a second insulator layer (typically an oxide layer) as an etch stop.

Engineering strained silicon on insulator wafers with the Smart CutTM technology

Abstract: Strained silicon on insulator wafers are today envisioned as a natural and powerful enhancement to standard SOI wafers and/or bulk-like strained Si layers. This paper is intended to demonstrate through miscellaneous structural results how a layer transfer technique such as the Smart CutTM technology can be used to obtain good quality tensile-strained silicon on insulator wafers. Such a technique uses preferentially hydrogen implantation to peel-off the very top part of an epitaxial stack and transfer it onto another silicon substrate. The formation of an insulator, prior to the bonding onto a new silicon substrate enables the formation of a “semiconductor on insulator” structure. Two approaches based on the Smart Cut technique are considered in this paper. The first one relies on the formation by layer transfer of a relaxed SiGe on insulator (“SGOI”) substrate on which a tensile-strained Si layer is then grown. The second one is based on the transfer of a SiGe relaxed buffer/Si cap stack. A SiGe-free tensile-silicon on insulator (sSOI) substrate is then obtained after the selective etching of the top SiGe layer. The epitaxial layers studied in this article are of two kinds: (i) the thick, nearly fully relaxed SiGe layers (with or without tensile-strained Si layers on top depending on the final structure targeted: SGOI or sSOI) used as the donor wafers in layer transfer operations, and (ii) the thin, relaxed SiGe layers and the thin, tensile-strained Si epitaxial films grown on SGOI substrates. In-depth physical characterizations of these epitaxial layers are used to evaluate the quality of the transferred layers in terms of thickness uniformity, Ge content, strain control, dislocation densities etc… Detailed experiments are also used to demonstrate that these final substrates are compatible with future CMOS applications. The sSOI approach is particularly challenging in this respect as the strain needs to be maintained during many technological operations such as layer transfer, selective removal of the SiGe, high temperature thermal treatments etc. First results showing how the strain is changing during such operations are presented.

High performance strained silicon finfets device and method for forming same

Abstract: A strained Fin Field Effect Transistor (FinFET) (and method for forming the same) includes a relaxed first material having a sidewall, and a strained second material formed on the sidewall of the first material. The relaxed first material and the strained second material form a fin of the FinFET.

METHODS OF SELECTIVE DEPOSITION OF HEAVILY DOPED EPITAXIAL SiGe

Abstract: In one embodiment a method for depositing a silicon film or silicon germanium film on a substrate is provided which includes placing the substrate within a process chamber and heating the substrate surface to a temperature in the range from about 600 C to about 900 C while maintaining a pressure in the process chamber in the range from about 13 Pa (0.1 Torr) to about 27 kPa (200 Torr). A deposition gas is provided to the process chamber and includes SiH4, an optional germanium source gas, an etchant, a carrier gas and optionally at least one dopant gas. The silicon film or the silicon germanium film is selectively and epitaxially grown on the substrate. One embodiment includes a method for depositing a silicon-containing film with an inert gas as the carrier gas. Methods also include the fabrication of electronic devices utilizing selective silicon germanium epitaxial films.

Film thickness constraints for manufacturable strained silicon CMOS

Abstract: This paper studies the effect of the strained silicon thickness on the characteristics of strained silicon MOSFETs on SiGe virtual substrates. NMOSFETs were fabricated on strained silicon substrates with various strained silicon thicknesses, both above and below the strained silicon critical thickness. The low field electron mobility and subthreshold characteristics of the devices were measured. Low field electron mobility is increased by about 1.8 times on all wafers and is not significantly degraded on any of the samples, even for a strained silicon thickness far greater than the critical thickness. From the subthreshold characteristics, however, it is shown that the off-state leakage current is greatly increased for the devices on the wafers with a strained silicon thickness that exceeds the critical thickness. The mechanism of the leakage was examined by using photon emission microscopy. Strong evidence is shown that the leakage mechanism is source/drain electrical shorting caused by enhanced dopant diffusion near misfit dislocations.

Photovoltaic cell and method of fabricating the same

Abstract: An i-type amorphous silicon film and an anti-reflection film made of amorphous silicon nitride or the like are formed in this order on a main surface of an n-type single-crystalline silicon substrate. On a back surface of the n-type single-crystalline silicon substrate are provided a positive electrode and a negative electrode next to each other. The positive electrode includes an i-type amorphous silicon film, a p-type amorphous silicon film, a back electrode, and a collector electrode formed in this order on the back surface of the n-type single-crystalline silicon substrate. The negative electrode includes an i-type amorphous silicon film, an n-type amorphous silicon film, a back electrode, and a collector electrode formed in this order on the back surface of the n-type single-crystalline silicon substrate.

Deposition of silicon germanium on silicon-on-insulator structures and bulk substrates

Abstract: Methods are provided for producing SiGe-on-insulator structures and for forming strain-relaxed SiGe layers on silicon while minimizing defects. Amorphous SiGe layers are deposited by CVD from trisilane and GeH 4 . The amorphous SiGe layers are recrystallized over silicon by melt or solid phase epitaxy (SPE) processes. The melt processes preferably also cause diffusion of germanium to dilute the overall germanium content and essentially consume the silicon overlying the insulator. The SPE process can be conducted with or without diffusion of germanium into the underlying silicon, and so is applicable to SOI as well as conventional semiconductor substrates.

Image sensor comprising isolated germanium photodetectors integrated with a silicon substrate and silicon circuitry

Abstract: In accordance with the invention, an improved image sensor includes an array of germanium photosensitive elements integrated with a silicon substrate and integrated with silicon readout circuits. The silicon transistors are formed first on a silicon substrate, using well known silicon wafer fabrication techniques. The germanium elements are subsequently formed overlying the silicon by epitaxial growth. The germanium elements are advantageously grown within surface openings of a dielectric cladding. Wafer fabrication techniques are applied to the elements to form isolated germanium photodiodes. Since temperatures needed for germanium processing are lower than those for silicon processing, the formation of the germanium devices need not affect the previously formed silicon devices. Insulating and metallic layers are then deposited and patterned to interconnect the silicon devices and to connect the germanium devices to the silicon circuits. The germanium elements are thus integrated to the silicon by epitaxial growth and integrated to the silicon circuitry by common metal layers.

Multiple gate semiconductor device and method for forming same

Abstract: In accordance with an embodiment of the invention, a FinFET device is disclosed which comprises a strained silicon channel layer formed on, at least, the sidewalls of a strain-relaxed silicon-germanium body.

Ultra-thin silicon-on-insulator and strained-silicon-direct-on-insulator with hybrid crystal orientations

Abstract: The invention provides integrated semiconductor devices that are formed upon an SOI substrate having different crystal orientations that provide optimal performance for a specific device. Specifically, an integrated semiconductor structure including at least an SOI substrate having a top semiconductor layer of a first crystallographic orientation and a semiconductor material of a second crystallographic orientation, wherein the semiconductor material is substantially coplanar and of substantially the same thickness as that of the top semiconductor layer and the first crystallographic orientation is different from the second crystallographic orientation is provided. The SOI substrate is formed by forming an opening into a structure that includes at least a first semiconductor layer and a second semiconductor layer that have different crystal orientations. The opening extends to the first semiconductor layer. A semiconductor material is epitaxial grown in the opening and then various etching and etch back processing steps are used in forming the SOI substrate.

Method for producing hydrogenated silicon oxycarbide films

Abstract: A method for producing hydrogenated silicon oxycarbide (H:SiOC) films having low dielectric constant. The method comprises using plasma-assisted polymerization to react a cyclic silane compound containing at least one strained silicon bond to produce the films. The resulting films are useful in the formation of semiconductor devices.

Strained silicon on insulator from film transfer and relaxation by hydrogen implantation

Abstract: Transistors fabricated on SSOI (Strained Silicon On Insulator) substrate, which comprises a strained silicon layer disposed directly on an insulator layer, have enhanced device performance due to the strain-induced band modification of the strained silicon device channel and the limited silicon volume because of the insulator layer. The present invention discloses a SSOI substrate fabrication process comprising various novel approaches. One is the use of a thin relaxed SiGe layer as the strain-induced seed layer to facilitate integration and reduce processing cost. Another is the formation of split implant microcracks deep in the silicon substrate to reduce the number of threading dislocations reaching the strained silicon layer. And lastly is the two step annealing/thinning process for the strained silicon/SiGe multilayer film transfer without blister or flaking formation.

Strained silicon NMOS devices with embedded source/drain

Abstract: A planar NFET on a strained silicon layer supported by a SiGe layer achieves reduced external resistance by removing SiGe material outside the transistor body and below the strained silicon layer and replacing the removed material with epitaxial silicon, thereby providing lower resistance for the transistor electrodes and permitting better control over Arsenic diffusion.

Silicon based thin film solar cell

Abstract: According to the present invention, sufficient light trapping effect can be exhibited and series resistance can be kept small, by sequentially forming a silicon based low refractive index layer and a thin silicon based interface layer on a backside of a photoelectric conversion layer observed from a light incident side, and as a result a silicon based thin film solar cell may be provided efficiently and at low cost.

Experimental study of biaxial and uniaxial strain effects on carrier mobility in bulk and ultrathin-body SOI MOSFETs

Abstract: Biaxial and uniaxial strained silicon technologies are promising for enhancement of CMOS performance. However, the advantage of uniaxial/biaxial strain over biaxial/uniaxial strain in terms of carrier mobility is not clear, since biaxial and uniaxial strain effects on carrier mobility have not till date been directly compared. Furthermore, the carrier mobility under uniaxial strain has not been fully studied in terms of strain directions. On the other hand, in spite of the importance of ultrathin-body (UTB) SOI MOSFETs to suppress the short channel effects in sub-20-nm regime, strain effects in UTB MOSFETs with SOI thickness, T/sub SOI/, of less than 5nm have not be explored yet. In this report, biaxial and uniaxial strain effects on carrier mobility are systematically studied, for the fist time, utilizing externally applied mechanical stress. The biaxial and uniaxial strain effects in UTB MOSFETs with T/sub SOI/ of less than 5nm are also investigated, for the first time.

Method of preventing surface roughening during hydrogen pre-bake of SiGe substrates using chlorine containing gases

Abstract: The invention forms an epitaxial silicon-containing layer on a silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface and avoids creating a rough surface upon which the epitaxial silicon-containing layer is grown. In order to avoid creating the rough surface, the invention first performs a hydrofluoric acid etching process on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. This etching process removes most of oxide from the surface, and leaves only a sub-monolayer of oxygen (typically 1×1013-1×1015/cm2 of oxygen) at the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. The invention then performs a hydrogen pre-bake process in a chlorine containing environment which heats the silicon germanium, strained silicon, or thin silicon-on-insulator surface sufficiently to remove the remaining oxygen from the surface. By introducing a small amount of chlorine containing gases, the heating processes avoid changing the roughness of the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. Then the process of epitaxially growing the epitaxial silicon-containing layer on the silicon germanium, patterned strained silicon, or patterned silicon-on-insulator surface is performed.

Smart-Cut® technology: from 300 mm ultrathin SOI production to advanced engineered substrates

Abstract: The Smart-Cut® process, based on hydrogen implantation and wafer bonding, is a generic thin layer process transfer. Unibond® SOI wafers are today in volume production, showing that splitting and bonding steps can be controlled, with high yields. Taking advantage of standard equipments flexibility, the process has been successfully scaled up to 300 mm. Most advanced 200 mm processes were successfully transferred to 300 mm, with wafers showing uniformity and defectivity results compatible with industry requirements for fully depleted device applications. The number of wafer solutions offered by the Smart-Cut® technology is already much greater than just SOI. Strained silicon on insulator, silicon on quartz (SOQ), single crystal silicon layer on plastic supports, silicon carbide on insulator, germanium on insulator, multilayer SOI structures are just few examples of the potential of Smart Cut® to engineer and design new substrates to answer the demands of the industry. A review of the progress achieved is given.