Showing papers on "Strained silicon published in 2005"

Toward the Introduction of New Materials and Structural Changes to Improve MOSFET Performance

Abstract: SUMMARY AND CONCLUSIONS Scaling CMOS to and beyond the 22-nm technology node(requiring a physical gate length of 9-nm or less) will probablyrequire the introduction of several new material and struc-tural changes to the MOSFET to sustain performance increas-es of 17% per year and to manage SCEs. Material changes willinclude strained silicon n- and p-channels and a new gatestack including a high-k dielectric and a metal gate electrode.Structural changes could include fully depleted UTB SOI sin-gle-gate MOSFETs, perhaps followed by fully depleted UTBdouble-gate structures. Attaining the performance require-ments for the final node for high performance applicationscould further require channels providing quasiballistic carriertransport, or very low-resistance source/drain contacts provid-ed by Schottky metal electrodes. The materials and structuralchanges actually introduced to advanced process technologieswill depend both on their readiness for manufacture and theirvalue in improving performance in the ultra-scaled devices.For example, a high-

Controlled shallow single ion implantation in silicon using an active substrate for sub-20 keV ions

Abstract: We demonstrate a method for the controlled implantation of single ions into a silicon substrate with energy of sub-20‐keV The method is based on the collection of electron-hole pairs generated in the substrate by the impact of a single ion We have used the method to implant single 14‐keV P31 ions through nanoscale masks into silicon as a route to the fabrication of devices based on single donors in silicon

Method for producing gate stack sidewall spacers

Abstract: A method for forming sidewall spacers on a gate stack by depositing one or more layers of silicon containing materials using PECVD process(es) on a gate structure to produce a spacer having an overall k value of about 3.0 to about 5.0. The silicon containing materials may be silicon carbide, oxygen doped silicon carbide, nitrogen doped silicon carbide, carbon doped silicon nitride, nitrogen doped silicon oxycarbide, or combinations thereof. The deposition is performed in a plasma enhanced chemical vapor deposition chamber and the deposition temperature is less than 450° C. The sidewall spacers so produced provide good capacity resistance, as well as excellent structural stability and hermeticity.

20 1%-efficient Crystalline Silicon Solar Cell with Amorphous Silicon Rear-surface Passivation

Abstract: We have developed a crystalline silicon solar cell with amorphous silicon (a-Si:H) rear-surface passivation based on a simple process. The a-Si:H layer is deposited at 225°C by plasma-enhanced chemical vapor deposition. An aluminum grid is evaporated onto the a-Si:H-passivated rear. The base contacts are formed by COSIMA (contact formation to a-Si:H passivated wafers by means of annealing) when subsequently depositing the front silicon nitride layer at 325°C. The a-Si:H underneath the aluminum fingers dissolves completely within the aluminum and an ohmic contact to the base is formed. This contacting scheme results in a very low contact resistance of 3.5 ±0.2 mΩ cm2 on low-resistivity (0.5 Ω cm) p-type silicon, which is below that obtained for conventional Al/Si contacts. We achieve an independently confirmed energy conversion efficiency of 20.1% under one-sun standard testing conditions for a 4 cm2 large cell. Measurements of the internal quantum efficiency show an improved rear surface passivation compared with reference cells with a silicon nitride rear passivation. Copyright © 2005 John Wiley & Sons, Ltd.

Transistor with silicon and carbon layer in the channel region

Abstract: A transistor and method of manufacturing thereof having stressed material layers formed in the channel to increase the speed and improve performance of the transistor. A layer of silicon and carbon is epitaxially grown in the channel region. A thin semiconductor material may be formed over the layer of silicon and carbon, and a stressed semiconductor layer may be epitaxially grown prior to forming the layer of silicon and carbon.

Method for improving transistor performance through reducing the salicide interface resistance

Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.

Semiconductor nano-wire devices and methods of fabrication

Abstract: Nano-wires, preferably of less than 20 nm diameter, can be formed with minimized risk of narrowing and breaking that results from silicon atom migration during an annealing process step. This is accomplished by masking portion of the active layer where silicon atomer would otherwise agglomerate with a material such as silicon dioxide, silicon nitride, or other dielectric that eliminates or substantially reduces the silicon atom migration. Nano-wires, nanotubes, nano-rods, and other features can be formed and can optionally be incorporated into devices, such as by use as a channel region in a transistor device.

Field effect transistors having a strained silicon channel and methods of fabricating same

Abstract: Field effect transistors (FETs) and methods of fabricating FETs that include a channel layer on sidewalls of a structure on a semiconductor substrate and having at least a portion of the channel layer strained in a direction that the sidewalls of the structure extend from the semiconductor substrate are provided. The transistor may be a FinFET, the structure on the semiconductor substrate that includes a fin structure and the sidewalls may be sidewalls of the fin structure. The channel layer may be a Si epitaxial layer and may be on an inner fin structure that includes alternating layers of SiGe and Si. The channel layer may include strained and unstrained portions. The strained and unstrained portions may be sidewalls of the channel layer.

Monte Carlo simulation of Joule heating in bulk and strained silicon

Abstract: This work examines the details of Joule heating in silicon with a Monte Carlo method including efficient, analytic models for the electron bands, acoustic and optical phonon dispersion. We find that a significant portion of the initially generated phonons have low group velocity, and therefore low contribution to heat transport, e.g., optical phonons or acoustic modes near the Brillouin zone edge. The generated phonon spectrum in strained silicon is different from bulk silicon at low electric fields due to band splitting and scattering selection rules which favor g-type and reduce f-type phonon emission. However, heat generation is essentially the same in strained and bulk silicon at high fields, when electrons have enough energy to emit across the entire phonon spectrum despite the strain-induced band splitting. The results of this study are important for electro-thermal analysis of future silicon nanoscale devices.

SOI structure having a SiGe layer interposed between the silicon and the insulator

Abstract: A semiconductor structure and a method of manufacturing a silicon on insulator (SOI) structure having a silicon germanium (SiGe) layer interposed between the silicon and the insulator. According to one manufacturing method, a first SiGe layer, a silicon layer, and a second SiGe layer are epitaxially grown in sequence over a first substrate, and then an insulating layer is formed on the second SiGe layer. Then, impurity ions are implanted into a predetermined location of the first substrate underlying the first SiGe layer to form an impurity implantation region. A second substrate is bonded to the insulating layer on the first substrate. After the first substrate is separated along the impurity implantation region and removed, the first SiGe layer remaining on the surface of the separated region is removed so that the surface of the silicon layer may be exposed.

Output prediction logic circuits with ultra-thin vertical transistors and methods of formation

Abstract: Very fast integrated OPL circuits, such as pseudo-NMOS OPL and dynamic OPL, comprising CMOS gate arrays having ultra-thin vertical NMOS transistors are disclosed. The ultra-thin vertical NMOS transistors of the CMOS gate arrays are formed with relaxed silicon germanium (SiGe) body regions with graded germanium content and strained silicon channels.

Method of forming silicon nitride film and method of manufacturing semiconductor device

Abstract: A method of forming a silicon nitride film comprises: forming a silicon nitride film by applying first gas containing silicon and nitrogen and second gas containing nitrogen and hydrogen to catalyst heated in a reduced pressure atmosphere. A method of manufacturing a semiconductor device comprising the steps of: forming a silicon nitride film by the method as claimed in claim 1 on a substrate having the semiconductor layer, a gate insulation film selectively provided on a principal surface of the semiconductor layer, and a gate electrode provided on the gate insulation film; and removing the silicon nitride film on the semiconductor layer and the gate electrode and leaving a sidewall comprising the silicon nitride film on a side surface of the gate insulation film and the gate electrode by etching the silicon nitride film in a direction generally normal to the principal surface of the semiconductor layer. A method of manufacturing a semiconductor device comprising the steps of: forming a silicon nitride film by the method as claimed in claim 1 on a substrate including a semiconductor layer; forming an interlayer insulation layer on the silicon nitride film; forming a layer having an opening on the interlayer insulation layer; and etching the interlayer insulation layer via the opening in a condition where an etching rate for the silicon nitride film is greater than an etching rate for the interlayer insulation layer.

Germanium silicon heterostructure photodetectors

Abstract: A horizontal germanium silicon heterostructure photodetector comprising a horizontal germanium p-i-n diode disposed over a horizontal parasitic silicon p-i-n diode uses silicon contacts for electrically coupling to the germanium p-i-n through the p-type doped and n-type doped regions in the silicon p-i-n without requiring direct physical contact to germanium material. The current invention may be optically coupled to on-chip and/or off-chip optical waveguide through end-fire or evanescent coupling. In some cases, the doping of the germanium p-type doped and/or n-type doped region may be accomplished based on out-diffusion of dopants in the doped silicon material of the underlying parasitic silicon p-i-n during high temperature steps in the fabrication process such as, the germanium deposition step(s), cyclic annealing, contact annealing and/or dopant activation.

Piezoresistance of silicon and strained Si0.9Ge0.1

Abstract: We present experimentally obtained results of the piezoresistive effect in p-type silicon and strained Si 0.9 Ge 0.1 . Today, strained Si 1− x Ge x is used for high speed electronic devices. This paper investigates if this area of use can be expanded to also cover piezoresistive micro electro mechanical systems (MEMS) devices. The measurements are performed on microfabricated test chips where resistors are defined in layers grown by molecular beam epitaxy on (0 0 1) silicon substrates. A uniaxial stress along the [1 1 0] direction is applied to the chip, with the use of a four point bending fixture. The investigation covers materials with doping levels of N A = 10 18 cm −3 and N A = 10 19 cm −3 , respectively. The results show that the π 66 piezoresistive coefficient in strained Si 0.9 Ge 0.1 is approximately 30% larger than the comparable π 44 piezoresistive coefficient in silicon at a doping level of N A = 10 18 cm −3 . Thus, strained Si 0.9 Ge 0.1 holds promise for use in high sensitivity MEMS devices.

Silicon carbide semiconductor device and process for producing the same

Abstract: A process for producing a semiconductor device, comprising the steps of injecting ions into silicon carbide thin-film (2) provided on silicon carbide substrate (1); heating the resultant silicon carbide substrate in vacuum atmosphere to thereby form carbon layer (5) on a surface of the resultant silicon carbide substrate; and subjecting the resultant silicon carbide substrate to activation annealing in an atmosphere of temperature higher and under a pressure higher than in the step of carbon layer (5) formation.

A 65nm ultra low power logic platform technology using uni-axial strained silicon transistors

Abstract: A leading edge 65nm logic process technology employing uni-axial strained silicon transistors has been optimized for ultra low power products Record PMOS/NMOS drive currents of 038/066 mA/mum, respectively, have been achieved at 12V and off-state leakage of 100 pA/mum Greater than 1000times reduction of SRAM cell standby leakage through implementation of sleep transistors and other leakage suppression schemes are also discussed

Bipolar Semiconductor Device and Process for Producing the Same

Abstract: Production of a bipolar semiconductor device having at least part of a region wherein at current passage electrons and holes re-couple with each other formed of an epitaxial layer of silicon carbide grown from a surface of silicon carbide substrate, wherein the epitaxial layer is formed by first performing hydrogen etching of a surface of silicon carbide substrate and thereafter effecting epitaxial growth of silicon carbide from the etched surface. Further propagation of a basal plane dislocation to the epitaxial layer can be reduced by subjecting the surface of silicon carbide substrate to chemical mechanical polishing prior to the hydrogen etching.

Method for producing dislocation-free strained crystalline films

Abstract: A method for forming dislocation-free strained silicon thin film includes the step of providing two curved silicon substrates. One substrate is curved by the presence of silicon dioxide on a back surface. The other substrate is curved by the presence of a silicon nitride layer. One of the substrates is subject to hydrogen implantation and the two substrates are bonded to one another in an annealing process. The two substrates are separated, thereby leaving a layer of strained silicon on a front side of one of the substrates. A back side layer of silicon dioxide or silicon nitride is then removed to restore the substrate to a substantially planar state. The method may be employed to form dislocation-free strained silicon thin films. The films may be under tensile or compressive strain.

Method of fabricating strained-silicon transistors and strained-silicon CMOS transistors

Abstract: A method of fabricating strained-silicon transistors includes providing a semiconductor substrate, in which the semiconductor substrate contains a gate structure thereon; performing an etching process to form two recesses corresponding to the gate structure within the semiconductor substrate; performing an oxygen flush on the semiconductor substrate; performing a cleaning process on the semiconductor substrate; and performing a selective epitaxial growth (SEG) to form an epitaxial layer in each recess for forming a source/drain region.

Memory characteristics of silicon nitride with silicon nanocrystals as a charge trapping layer of nonvolatile memory devices

Abstract: Silicon nitride with silicon nanocrystals formed by low-energy silicon plasma immersion ion implantation has been investigated as a charge trapping layer of a polycrystalline silicon-oxide-nitride-oxide-silicon-type nonvolatile memory device. Compared with the control sample without silicon nanocrystals, silicon nitride with silicon nanocrystals provides excellent memory characteristics, such as larger width of capacitance-voltage hysteresis, higher program∕erase speed, and lower charge loss rate at elevated temperature. These improved memory characteristics are derived by incorporation of silicon nanocrystals into the charge trapping layer as additional accessible charge traps with a deeper effective trap energy level.

Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer

Abstract: Disclosed is a p-type field effect transistor (pFET) structure and method of forming the pFET. The pFET comprises embedded silicon germanium in the source/drain regions to increase longitudinal stress on the p-channel and, thereby, enhance transistor performance. Increased stress is achieved by increasing the depth of the source/drain regions and, thereby, the volume of the embedded silicon germanium. The greater depth (e.g., up to 100 nm) of the stressed silicon germanium source/drain regions is achieved by using a double BOX SOI wafer. Trenches are etched through a first silicon layer and first buried oxide layer and then the stressed silicon germanium is epitaxially grown from a second silicon layer. A second buried oxide layer isolates the pFET.

Method for fabricating strained silicon-on-insulator structures and strained silicon-on-insulator structures formed thereby

Abstract: A silicon-on-insulator (SOI) device and structure having locally strained regions in the silicon active layer formed by increasing the thickness of underlying regions of a buried insulating layer separating the silicon active layer from the substrate. The stress transferred from the underlying thickened regions of the insulating layer to the overlying strained regions increases carrier mobility in these confined regions of the active layer. Devices formed in and on the silicon active layer may benefit from the increased carrier mobility in the spaced-apart strained regions.

Epitaxial silicon carbide single crystal substrate, and its manufacturing method

Abstract: PROBLEM TO BE SOLVED: To provide an epitaxial silicon carbide single crystal substrate having a silicon carbide single crystal thin film with a high quality and a few defect on the silicon carbide single crystal substrate with a small off-angle and to provide its manufacturing method. SOLUTION: In the epitaxial silicon carbide single crystal substrate having the silicon carbide single crystal thin film with a triangular defect density and a mall surface coarseness on the silicon carbide single crystal substrate with the off-angle of ≤4° and its manufacturing method, a triangular epitaxial defect density on the silicon carbide single crystal thin film is ≤3 piece/cm 2 and a Ra value of the surface coarseness is ≤2.5 nm, and the silicon carbide single crystal thin film has a layer for reducing the defect and the surface coarseness (defect reducing layer) and a layer for acting as a device (active layer) and an atomic ratio (C/Si ratio) of carbon and silicon contained in a material gas at the time of the epitaxial growth of the defect reducing layer is ≥0.5 and less than 1.0 and a C/Si ratio at the time of the epitaxial growth of the active layer is ≥1.0 and ≤1.5 and a growth temperature of each layer is ≥1,600°C and ≤1,650°C. COPYRIGHT: (C)2010,JPO&INPIT

Integration of biaxial tensile strained NMOS and uniaxial compressive strained PMOS on the same wafer

Abstract: A method of fabricating a biaxial tensile strained layer for NMOS fabrication and a uniaxial compressive strained layer for PMOS fabrication on a single wafer for use in CMOS ICs, includes preparing a silicon substrate for CMOS fabrication; depositing, patterning and etching a first and second insulating layers; removing a portion of the second insulating layer from a PMOS active area; depositing a layer of epitaxial silicon on the PMOS active area; removing a portion of the second insulating layer from an NMOS active area; growing an epitaxial silicon layer and growing an epitaxial SiGe layer on the NMOS active area; implanting H 2 + ions; annealing the wafer to relax the SiGe layer; removing the remaining second insulating layer from the wafer; growing a layer of silicon; finishing a gate module; depositing a layer of SiO 2 to cover the NMOS wafer; etching silicon in the PMOS active area; selectively growing a SiGe layer on the PMOS active area; wherein the silicon layer in the NMOS active area is under biaxial tensile strain, and the silicon layer in the PMOS active area is uniaxial compressive strained; and completing the CMOS device.

Strain relaxation in patterned strained silicon directly on insulator structures

Abstract: Strain relaxation is studied in strained silicon directly on insulator (SSDOI) substrates patterned with nanoscale features. Using interference lithography, biaxially strained SSDOI substrates with 30nm thick strained Si on insulator films were patterned into grating structures with 90nm wide stripes, and arrays of 80nm×170nm pillars. The strain profiles of these patterned structures were examined by ultraviolet Raman spectroscopy. Raman analysis of the SSDOI gratings indicates strain relaxation in the 90nm wide stripes, compared to the strain measured in unpatterned portions of the SSDOI wafer. Three-dimensional finite-element modeling of the stress distributions in the grading structures predicts that 95% of the strain is maintained in the direction along the length of the stripes. These simulations are used to decouple the strain components along the width and length of the SSDOI grating structure, inferred from Raman measurements. The results are consistent with substantial stress relaxation across th...

Highly sensitive strain detection in strained silicon by surface-enhanced Raman spectroscopy

Abstract: We used surface-enhanced Raman spectroscopy to observe selective amplification of the vibration mode of Si–Si in strained silicon. By covering the silver island film on a strained silicon layer, the Raman signal from the strained silicon can be detected with a high sensitivity compared with the overwhelming background signal from the underlying silicon layer. This technique allowed us to carry out micro-Raman spectroscopy on strained silicon. This technique can be a precursor for nano-Raman spectroscopy using a tip-enhanced Raman microscope with a sharpened metallic probe tip.

In situ doped embedded sige extension and source/drain for enhanced PFET performance

Abstract: Disclosed is an integrated circuit structure and a method of making such a structure that has a substrate and P-type and N-type transistors on the substrate. The N-type transistor extension and source/drain regions comprise dopants implanted into the substrate. The P-type transistor extension and source/drain regions partially include a strained epitaxial silicon germanium, wherein the strained silicon germanium comprises of two layers, with a top layer that is closer to the gate stack than the bottom layer. The strained silicon germanium is in-situ doped and creates longitudinal stress on the channel region.

Dislocation-free strained silicon-on-silicon by in-place bonding

Abstract: In-place bonding is a technique where silicon-on-insulator (SOI) slabs are bonded by hydrophobic attraction to the underlying silicon substrate when the buried oxide is undercut in dilute HF. The bonding between the exposed surfaces of the SOI slab and the substrate propagates simultaneously with the buried oxide etching. As a result, the slabs maintain their registration and are referred to as “bonded in-place”. We report the fabrication of dislocation-free strained silicon slabs from pseudomorphic trilayer Si/SiGe/SOI by in-place bonding. Removal of the buried oxide allows the compressively strained SiGe film to relax elastically and induce tensile strain in the top and bottom silicon films. The slabs remain bonded to the substrate by van der Waals forces when the wafer is dried. Subsequent annealing forms a covalent bond such that when the upper Si and the SiGe layer are removed, the bonded silicon slab remains strained.

Germanium substrate-type materials and approach therefor

Abstract: Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices.