Showing papers on "Strained silicon published in 2006"

Strained silicon as a new electro-optic material

Abstract: For decades, silicon has been the material of choice for mass fabrication of electronics. This is in contrast to photonics, where passive optical components in silicon have only recently been realized. The slow progress within silicon optoelectronics, where electronic and optical functionalities can be integrated into monolithic components based on the versatile silicon platform, is due to the limited active optical properties of silicon. Recently, however, a continuous-wave Raman silicon laser was demonstrated; if an effective modulator could also be realized in silicon, data processing and transmission could potentially be performed by all-silicon electronic and optical components. Here we have discovered that a significant linear electro-optic effect is induced in silicon by breaking the crystal symmetry. The symmetry is broken by depositing a straining layer on top of a silicon waveguide, and the induced nonlinear coefficient, chi(2) approximately 15 pm V(-1), makes it possible to realize a silicon electro-optic modulator. The strain-induced linear electro-optic effect may be used to remove a bottleneck in modern computers by replacing the electronic bus with a much faster optical alternative.

Fabrication of Single-Crystalline Silicon Nanowires by Scratching a Silicon Surface with Catalytic Metal Particles†

Abstract: A novel strategy for preparing large-area, oriented silicon nanowire (SiNW) arrays on silicon substrates at near room temperature by localized chemical etching is presented. The strategy is based on metal-induced (either by Ag or Au) excessive local oxidation and dissolution of a silicon substrate in an aqueous fluoride solution. The density and size of the as-prepared SiNWs depend on the distribution of the patterned metal particles on the silicon surface. High-density metal particles facilitate the formation of silicon nanowires. Well-separated, straight nanoholes are dug along the Si block when metal particles are well dispersed with a large space between them. The etching technique is weakly dependent on the orientation and doping type of the silicon wafer. Therefore, SiNWs with desired axial crystallographic orientations and doping characteristics are readily obtained. Detailed scanning electron microscopy observations reveal the formation process of the silicon nanowires, and a reasonable mechanism is proposed on the basis of the electrochemistry of silicon and the experimental results.

Uniaxial-process-induced strained-Si: extending the CMOS roadmap

Abstract: This paper reviews the history of strained-silicon and the adoption of uniaxial-process-induced strain in nearly all high-performance 90-, 65-, and 45-nm logic technologies to date. A more complete data set of n- and p-channel MOSFET piezoresistance and strain-altered gate tunneling is presented along with new insight into the physical mechanisms responsible for hole mobility enhancement. Strained-Si hole mobility data are analyzed using six band k/spl middot/p calculations for stresses of technological importance: uniaxial longitudinal compressive and biaxial stress on [001] and [110] wafers. The calculations and experimental data show that low in-plane and large out-of-plane conductivity effective masses and a high density of states in the top band are all important for large hole mobility enhancement. This work suggests longitudinal compressive stress on [001] or [110] wafers and channel direction offers the most favorable band structure for holes. The maximum Si inversion-layer hole mobility enhancement is estimated to be /spl sim/ 4 times higher for uniaxial stress on (100) wafer and /spl sim/ 2 times higher for biaxial stress on (100) wafer and for uniaxial stress on a [110] wafer.

Overview and status of metal S/D Schottky-barrier MOSFET technology

Abstract: In this paper, the metal source/drain (S/D) Schottky-barrier (SB) MOSFET technology is reviewed. The technology offers several benefits that enable scaling to sub-30-nm gate lengths including extremely low parasitic S/D resistance (1% of the total device resistance), atomically abrupt junctions that enable the physical scaling of the device to sub-10-nm gate lengths, superior control of OFF-state leakage current due to the intrinsic Schottky potential barrier, and elimination of parasitic bipolar action. These and other benefits accrue using a low-thermal-budget CMOS manufacturing process requiring two fewer masks than conventional bulk CMOS. The SB-CMOS manufacturing process enables integration of critical new materials such as high-k gate insulators and strained silicon substrates. SB MOSFET technology state of the art is also reviewed, and shown to be focused on barrier-height-lowering techniques that use interfacial layers between the metal S/Ds and the channel region. SB-PMOS devices tend to have superior performance compared to NMOS, but NMOS performance has recently improved by using ytterbium silicide or by using hybrid structures that incorporate interfacial layers to lower the SB height.

Elastically relaxed free-standing strained-silicon nanomembranes.

Abstract: Strain plays a critical role in the properties of materials. In silicon and silicon-germanium, strain provides a mechanism for control of both carrier mobility and band offsets. In materials integration, strain is typically tuned through the use of dislocations and elemental composition. We demonstrate a versatile method to control strain by fabricating membranes in which the final strain state is controlled by elastic strain sharing, that is, without the formation of defects. We grow Si/SiGe layers on a substrate from which they can be released, forming nanomembranes. X-ray-diffraction measurements confirm a final strain predicted by elasticity theory. The effectiveness of elastic strain to alter electronic properties is demonstrated by low-temperature longitudinal Hall-effect measurements on a strained-silicon quantum well before and after release. Elastic strain sharing and film transfer offer an intriguing path towards complex, multiple-layer structures in which each layer's properties are controlled elastically, without the introduction of undesirable defects.

Silicon quantum dot superlattices: Modeling of energy bands, densities of states, and mobilities for silicon tandem solar cell applications

Abstract: Quantum dot superlattices offer prospects for new generations of semiconductor devices One possible recently suggested application is in tandem solar cells based entirely on silicon, using confinement in the quantum dot to control the cell band gap In this paper, we use the effective mass approach to calculate the conduction band structure of a three-dimensional silicon quantum dot superlattice with the dots embedded in a matrix of silicon dioxide, silicon nitride, or silicon carbide The quantum dot superlattice is modeled as a regularly spaced array of equally sized cubic dots in the respective matrix Incorporating the effect of silicon anisotropic effective mass is shown to reduce both the degeneracies of the isotropic solutions and the energy separation between states Electron densities of state and mobilities are derived from the band structure data Theoretical results for the effect of dot size, interdot distance, and matrix material have been obtained These results clarify the required design features of silicon quantum dot superlattices for the proposed all-silicon tandem solar cells

Superconductivity in doped cubic silicon.

Abstract: Although the local resistivity of semiconducting silicon in its standard crystalline form can be changed by many orders of magnitude by doping with elements, superconductivity has so far never been achieved. Hybrid devices combining silicon's semiconducting properties and superconductivity have therefore remained largely underdeveloped. Here we report that superconductivity can be induced when boron is locally introduced into silicon at concentrations above its equilibrium solubility. For sufficiently high boron doping (typically 100 p.p.m.) silicon becomes metallic(1). We find that at a higher boron concentration of several per cent, achieved by gas immersion laser doping, silicon becomes superconducting. Electrical resistivity and magnetic susceptibility measurements show that boron-doped silicon (Si:B) made in this way is a superconductor below a transition temperature T-c approximate to 0.35 K, with a critical field of about 0.4 T. Ab initio calculations, corroborated by Raman measurements, strongly suggest that doping is substitutional. The calculated electron-phonon coupling strength is found to be consistent with a conventional phonon-mediated coupling mechanism(2). Our findings will facilitate the fabrication of new silicon-based superconducting nano-structures and mesoscopic devices with high-quality interfaces.

Ald of silicon films on germanium

Abstract: The use of atomic layer deposition (ALD) to form a semiconductor structure of a silicon film on a germanium substrate is disclosed. An embodiment includes a tantalum nitride gate electrode on a hafnium dioxide gate dielectric on the silicon film (TaN/HfO2/Si/Ge), which produces a reliable high dielectric constant (high k) electronic structure having higher charge carrier mobility as compared to silicon substrates. This structure may be useful in high performance electronic devices. The structure is formed by ALD deposition of a thin silicon layer on a germanium substrate surface, and then ALD forming a hafnium oxide gate dielectric layer, and a tantalum nitride gate electrode. Such a structure may be used as the gate of a MOSFET, or as a capacitor. The properties of the dielectric may be varied by replacing the hafnium oxide with another gate dielectric such as zirconium oxide (ZrO2), or titanium oxide (TiO2).

Electronic transport in nanometre-scale silicon-on-insulator membranes

Abstract: The widely used ‘silicon-on-insulator’ (SOI) system consists of a layer of single-crystalline silicon supported on a silicon dioxide substrate. When this silicon layer (the template layer) is very thin, the assumption that an effectively infinite number of atoms contributes to its physical properties no longer applies, and new electronic, mechanical and thermodynamic phenomena arise1,2,3,4, distinct from those of bulk silicon. The development of unusual electronic properties with decreasing layer thickness is particularly important for silicon microelectronic devices, in which (001)-oriented SOI is often used5,6,7. Here we show—using scanning tunnelling microscopy, electronic transport measurements, and theory—that electronic conduction in thin SOI(001) is determined not by bulk dopants but by the interaction of surface or interface electronic energy levels with the ‘bulk’ band structure of the thin silicon template layer. This interaction enables high-mobility carrier conduction in nanometre-scale SOI; conduction in even the thinnest membranes or layers of Si(001) is therefore possible, independent of any considerations of bulk doping, provided that the proper surface or interface states are available to enable the thermal excitation of ‘bulk’ carriers in the silicon layer.

Fundamentals of silicon material properties for successful exploitation of strain engineering in modern CMOS manufacturing

Abstract: Semiconductor industry has increasingly resorted to strain as a means of realizing the required node-to-node transistor performance improvements. Straining silicon fundamentally changes the mechanical, electrical (band structure and mobility), and chemical (diffusion and activation) properties. As silicon is strained and subjected to high-temperature thermal processing, it undergoes mechanical deformations that create defects, which may significantly limit yield. Engineers have to manipulate these properties of silicon to balance the performance gains against defect generation. This paper will elucidate the current understanding and ongoing published efforts on all these critical properties in bulk strained silicon. The manifestation of these properties in CMOS transistor performance and designs that successfully harness strain is reviewed in the last section. Current manufacturable strained-silicon technologies are reviewed with particular emphasis on scalability. A detailed case study on recessed silicon germanium transistors illustrates the application of the fundamentals to optimal transistor design.

High-speed strained-single-crystal-silicon thin-film transistors on flexible polymers

Abstract: We fabricate thin-film transistors (TFTs) on both strained and unstrained single-crystal Si membranes transferred to flexible-polymer substrates. The active layer is transferred from the starting silicon on insulator (SOI) using a simple, fast, and reliable dry-printing method. When a multilayer Si∕SiGe∕Si structure is pseudomorphically grown on SOI and the buried oxide is selectively removed, strained Si with a negligible density of dislocations is achieved via elastic strain sharing between the SiGe alloy layer and the Si layers. Both the drain current and the transconductance of TFTs fabricated on this strained Si∕SiGe∕Si membrane after its transfer to the flexible polymer are much higher than of TFTs fabricated on the unstrained-Si counterpart.

Physics of Hole Transport in Strained Silicon MOSFET Inversion Layers

Abstract: A comprehensive quantum anisotropic transport model for holes was used to study silicon PMOS inversion layer transport under arbitrary stress. The anisotropic band structures of bulk silicon and silicon under field confinement as a twodimensional quantum gas are computed using the pseudopotential method and a six-band stress-dependent k.p Hamiltonian. Anisotropic scattering is included in the momentum-dependent scattering rate calculation. Mobility is obtained from the Kubo-Greenwood formula at low lateral field and from the fullband Monte Carlo simulation at high lateral field. Using these methods, a comprehensive study has been performed for both uniaxial and biaxial stresses. The results are compared with device bending data and piezoresistance data for uniaxial stress, and device data from strained Si channel on relaxed SiGe substrate devices for biaxial tensile stress. All comparisons show a very good agreement with simulation. It is found that the hole band structure is dominated by 12 "wings," where mechanical stress, as well as the vertical field under certain stress conditions, can alter the energies of the few lowest hole subbands, changing the transport effective mass, density-of-states, and scattering rates, and thus affecting the mobility

Decreasing the etch rate of silicon nitride by carbon addition

Abstract: Methods for forming silicon nitride hard masks are provided. The silicon nitride hard masks include carbon-doped silicon nitride layers and undoped silicon nitride layers. Carbon-doped silicon nitride layers that are deposited from a mixture comprising a carbon source compound, a silicon source compound, and a nitrogen source in the presence of RF power are provided. Also provided are methods of UV post-treating silicon nitride layers to provide silicon nitride hard masks. The carbon-doped silicon nitride layers and UV post-treated silicon nitride layers have desirable wet etch rates and dry etch rates for hard mask layers.

Method for Thin Film Formation

Abstract: A method for thin film formation that can form, at a low temperature, a good thin film having a good interfacial property between a silicon substrate and a silicon oxide film and having a low interfacial trap density is provided. The method for thin film formation comprises generating plasma within a vacuum vessel to generate an active species (radical) and forming a silicon oxide film on a silicon substrate using this active species and a material gas, wherein, in addition to the material gas, a nitrogen atom-containing gas is introduced into the vacuum vessel in its film forming space where the active species (radical) and the material gas come into contact with each other for the first time and are reacted with each other to form a silicon film on the silicon substrate, and wherein the flow rate of the nitrogen atom-containing gas during the formation of the silicon oxide film on the silicon substrate is regulated so as to be the maximum value at least at the time of the start of formation of the silicon film on the silicon substrate.

High-mobility ultrathin strained Ge MOSFETs on bulk and SOI with low band-to-band tunneling leakage: experiments

Abstract: For the first time, the tradeoffs between higher mobility (smaller bandgap) channel and lower band-to-band tunneling (BTBT) leakage have been investigated. In particular, through detailed experiments and simulations, the transport and leakage in ultrathin (UT) strained germanium (Ge) MOSFETs on bulk and silicon-on-insulator (SOI) have been examined. In the case of strained Ge MOSFETs on bulk Si, the resulting optimal structure obtained was a UT low-defect 2-nm fully strained Ge epi channel on relaxed Si, with a 4-nm Si cap layer. The fabricated device shows very high mobility enhancements >3.5/spl times/ over bulk Si devices, 2/spl times/ mobility enhancement and >10/spl times/ BTBT reduction over 4-nm strained Ge, and surface channel 50% strained SiGe devices. Strained SiGe MOSFETs having UT (T/sub Ge/ 4/spl times/ over bulk Si devices, >2.5/spl times/ over strained silicon directly on insulator (SSDOI; strained to 20% relaxed SiGe) devices, and >1.5/spl times/ over 60% strained SiGe (on relaxed bulk Si) devices.

Method for Accelerated Etching of Silicon

Abstract: A method for the plasma-free etching of silicon using the etching gas ClF 3 or XeF 2 and its use are provided. The silicon is provided having one or more areas to be etched as a layer on the substrate or as the substrate material itself. The silicon is converted into the mixed semiconductor SiGe by introducing germanium and is etched by supplying the etching gas ClF 3 or XeF 2 . The introduction of germanium and the supply of the etching gas ClF 3 or XeF 2 may be performed at the same time or alternatingly. In particular, it is provided that the introduction of germanium be performed by implanting germanium ions in silicon.

Fabrication of vertical sidewalls on (110) silicon substrates for use in Si/SiGe photodetectors

Abstract: A method of fabricating vertical sidewalls on silicon (110) substrates for use in Si/SiGe photodetectors includes preparing a silicon (110) layer wherein the silicon (110) plane is parallel to an underlying silicon wafer surface Masking the silicon (110) layer with mask sidewalls parallel to a silicon (111) layer plane and etching the silicon (110) layer to remove an un-masked portion thereof, leaving a patterned silicon (110) layer having vertical silicon (111) sidewalls Removing the mask; growing SiGe-containing layers on the patterned silicon (110) layer; and fabricating a photodetector

Strained silicon fin structure

Abstract: Disclosing is a strained silicon finFET device having a strained silicon fin channel in a double gate finFET structure. The disclosed finFET device is a double gate MOSFET consisting of a silicon fin channel controlled by a self-aligned double gate for suppressing short channel effect and enhancing drive current. The silicon fin channel of the disclosed finFET device is a strained silicon fin channel, comprising a strained silicon layer deposited on a seed fin having different lattice constant, for example, a silicon layer deposited on a silicon germanium seed fin, or a carbon doped silicon layer deposited on a silicon seed fin. The lattice mismatch between the silicon layer and the seed fin generates the strained silicon fin channel in the disclosed finFET device to improve hole and electron mobility enhancement, in addition to short channel effect reduction characteristic inherently in a finFET device.

Nanoscale characterization of strained silicon by tip-enhanced Raman spectroscope in reflection mode

Abstract: We observe localized strains in strained silicon by tip-enhanced near-field Raman spectroscope in reflection mode. The tip-enhanced Raman spectra show that the Raman frequency and intensity of strained silicon were different within a crosshatch pattern induced by lattice mismatch. Micro-Raman measurements, however, show only uniform features because of averaging effect due to the diffraction limit of light. Nanoscale characterization of strained silicon is essential for developing reliable next generation integrated circuits. This technique can be applicable not only to strained silicon but also to any other crystals.

Atomistic calculation of elastic moduli in strained silicon

Abstract: Strained silicon is becoming a new technology in silicon industry where the novel strain-induced features are utilized. In this paper we present a molecular dynamic prediction for the elastic stiffnesses C11, C12 and C44 in strained silicon as functions of the volumetric strain level. Our approach combines basic continuum mechanics with the classical molecular dynamic approach, supplemented with the Stillinger–Weber potential. Using our approach, the bulk modulus, effective elastic stiffnesses C11, C12 and C44 of the strained silicon, including also the effective Young's modulus and Poisson's ratio, are all calculated and presented in terms of figures and formulae. In general, our simulation indicates that the bulk moduli, C11 and C12, increase with increasing volumetric strain whilst C44 is almost independent of the volumetric strain. The difference between strained moduli and those at zero strain can be very large, and therefore use of standard free-strained moduli should be cautious.

Creation of high mobility channels in thin-body SOI devices

Abstract: A method for fabricating a strained silicon film to a silicon on insulation (SOI) wafer. A layer of oxide is deposited onto a wafer that has a stack structure of a first base substrate, a layer of relaxed film=and a second layer of strained film. The SOI wafer has a stack structure of a second base substrate and a layer of oxidized film. The SOI wafer is attached to the wafer and is heated at a first temperature. This causes a silicon dioxide (SiO2) dangling bond to form on the second base substrate of the SOI wafer, transferring the strained film from one wafer to the other.

Future of Strained Si/Semiconductors in Nanoscale MOSFETs

Abstract: The maximum electron and hole mobility enhancement for uniaxial process-induced strained silicon is modeled and experimentally measured using a flexure based 4-point wafer bending jig. The highest known uniaxial stress to date is introduced into the channel of MOSFETs (applied mechanical stress of ~1.0GPa on samples with initial process stress of 1GPa for a total channel stress of ~2Pa). The maximum mobility enhancement from uniaxial stress is found to be greater than ~4.0 and ~1.7 times for holes and electrons, respectively. The physics behind the strain enhanced mobility is explained and future cases of technological importance to the industry are investigated.

Giant enhancement of the carrier mobility in silicon nanowires with diamond coating.

Abstract: We show theoretically that the low-field carrier mobility in silicon nanowires can be greatly enhanced by embedding the nanowires within a hard material such as diamond. The electron mobility in the cylindrical silicon nanowires with 4-nm diameter, which are coated with diamond, is 2 orders of magnitude higher at 10 K and a factor of 2 higher at room temperature than the mobility in a free-standing silicon nanowire. The importance of this result for the downscaled architectures and possible silicon-carbon nanoelectronic devices is augmented by an extra benefit of diamond, a superior heat conductor, for thermal management.

Doped nitride film, doped oxide film and other doped films

Abstract: Adding at least one non-silicon precursor (such as a germanium precursor, a carbon precursor, etc.) during formation of a silicon nitride, silicon oxide, silicon oxynitride or silicon carbide film improves the deposition rate and/or makes possible tuning of properties of the film, such as tuning of the stress of the film. Also, in a doped silicon oxide or doped silicon nitride or other doped structure, the presence of the dopant may be used for measuring a signal associated with the dopant, as an etch-stop or otherwise for achieving control during etching.

Methods of shaping vertical single crystal silicon walls and resulting structures

Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon substrate is exposed to an anisotropic etchant that undercuts the single crystal silicon. By controlling the length of the etch, single crystal silicon islands or smooth vertical walls in the single crystal silicon may be created.

Direct strain measurement in a 65 nm node strained silicon transistor by convergent-beam electron diffraction

Abstract: Using the energy-filtered convergent-beam electron diffraction (CBED) technique in a transmission electron microscope, the authors report here a direct measurement of the lattice parameters of uniaxially strained silicon as close as 25nm below the gate in a 65nm node p-type metal-oxide-semiconductor field-effect transistor with SiGe source and drain. It is found that the dominant strain component (0.58%) is compressive along the source-drain direction. The compressive stress is 1.1GPa along this direction. These findings demonstrate that CBED can serve as a strain metrology technique for the development of strained silicon device technology.

Methods of processing semiconductor wafers having silicon carbide power devices thereon

Abstract: Methods of forming a silicon carbide semiconductor device are disclosed. The methods include forming a semiconductor device at a first surface of a silicon carbide substrate having a first thickness, and mounting a carrier substrate to the first surface of the silicon carbide substrate. The carrier substrate provides mechanical support to the silicon carbide substrate. The methods further include thinning the silicon carbide substrate to a thickness less the first thickness, forming a metal layer on the thinned silicon carbide substrate opposite the first surface of the silicon carbide substrate, and locally annealing the metal layer to form an ohmic contact on the thinned silicon carbide substrate opposite the first surface of the silicon carbide substrate. The silicon carbide substrate is singulated to provide a singulated semiconductor device.

Stacked non-volatile memory with silicon carbide-based amorphous silicon thin film transistors

Abstract: A stacked non-volatile memory device uses amorphous silicon based thin film transistors stacked vertically. Each layer of transistors or cells is formed from a deposited a-Si channel region layer having a predetermined concentration of carbon to form a carbon rich silicon film or silicon carbide film, depending on the carbon content. The dielectric stack is formed over the channel region layer. In one embodiment, the dielectric stack is an ONO structure. The control gate is formed over the dielectric stack. This structure is repeated vertically to form the stacked structure. In one embodiment, the carbon content of the channel region layer is reduced for each subsequently formed layer.

Electron trap density distribution of Si-rich silicon nitride extracted using the modified negative charge decay model of silicon-oxide-nitride-oxide-silicon structure at elevated temperatures

Abstract: The authors modified the charge decay model of silicon-oxide-nitride-oxide-silicon-type memory at the temperatures above 150°C. The modified model includes the effect of the internal electric field induced by the charges trapped in silicon nitride layer. The authors extracted the trap density distributions in energy level of the Si-rich silicon nitride using the model and compared them with those of stoichiometric silicon nitride. It has been revealed that the Si-rich silicon nitride has larger trap density in shallow energy level than the stoichiometric silicon nitride and this relation is reversed as the energy level goes deeper.