Showing papers on "Strained silicon published in 2008"

Germanium FinFETs having dielectric punch-through stoppers

Abstract: A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fine. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.

Design of Tunneling Field-Effect Transistors Using Strained-Silicon/Strained-Germanium Type-II Staggered Heterojunctions

Abstract: Heterojunction tunneling field-effect transistors (HTFETs) that use strained-silicon/strained-germanium type-II staggered band alignment for band-to-band tunneling (BBT) injection are simulated using a nonlocal quantum tunneling model. The tunneling model is first compared to measurements of gate- controlled BBT in previously fabricated strained SiGe diodes and is shown to produce good agreement with the measurements. The simulation of the gated diode structure is then extended to study HTFETs with an effective energy barrier of 0.25 eV at the strained-Si/strained-Ge heterointerface. As the band alignment, particularly the valence band offset, is critical to modeling HTFET operation, analysis of measured characteristics of MOS capacitors fabricated in strained-Si/strained-Ge/relaxed Si0.5Ge0.5 hetero- junctions is used to extract a valence band offset of 0.64 eV at the strained-Si/strained-Ge heterointerface. Simulations are used to compare HTFETs to MOSFETs with similar technology parameters. The simulations show that HTFETs have potential for low-operating-voltage (Vdd < 0.5 V) application and exhibit steep subthreshold swing over many decades while maintaining high ON-state currents.

A 32nm logic technology featuring 2 nd -generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm 2 SRAM cell size in a 291Mb array

Abstract: A 32 nm generation logic technology is described incorporating 2nd-generation high-k + metal-gate technology, 193 nm immersion lithography for critical patterning layers, and enhanced channel strain techniques. The transistors feature 9 Aring EOT high-k gate dielectric, dual band-edge workfunction metal gates, and 4th-generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. Process yield, performance and reliability are demonstrated on a 291 Mbit SRAM test vehicle, with 0.171 mum2 cell size, containing >1.9 billion transistors.

Deposited semiconductor structure to minimize N-type dopant diffusion and method of making

Abstract: In deposited silicon, n-type dopants such as phosphorus and arsenic tend to seek the surface of the silicon, rising as the layer is deposited. When a second undoped or p-doped silicon layer is deposited on n-doped silicon with no n-type dopant provided, a first thickness of this second silicon layer nonetheless tends to include unwanted n-type dopant which has diffused up from lower levels. This surface-seeking behavior diminishes when germanium is alloyed with the silicon. In some devices, it may not be advantageous for the second layer to have significant germanium content. In the present invention, a first heavily n-doped semiconductor layer (preferably at least 10 at % germanium) is deposited, followed by a silicon-germanium capping layer with little or no n-type dopant, followed by a layer with little or no n-type dopant and less than 10 at % germanium. The germanium in the first layer and the capping layer minimizes diffusion of n-type dopant into the germanium-poor layer above.

First-principles study of electronic properties of biaxially strained silicon: Effects on charge carrier mobility

Abstract: Using first-principles method, we calculate the electronic band structure of biaxially strained silicon, from which we analyze the change in electron and hole effective mass as a function of strain and determine the mobility of electrons and holes in the biaxially strained silicon based on Boltzmann transport theory. We found that electron mobility increases with tensile strain and decreases with compressive strain. Such changes are mainly caused by a strain-induced change in electron effective mass, while the suppression of intervalley scattering plays a minor role. On the other hand, the hole mobility increases with both signs of strain and the effect is more significant for compressive strain because the hole effective mass decreases with compressive strain but increases with tensile strain. The strain-induced suppression of interband and intraband scatterings plays also an important role in changing the hole mobility.

New method for growing silicon carbide on silicon by solid-phase epitaxy: Model and experiment

Abstract: A new method of solid-state epitaxy of silicon carbide (SiC) on silicon (Si) is proposed theoretically and realized experimentally. Films of various polytypes of SiC on Si(111) grow through a chemical reaction (at T = 1100–1400°C) between single-crystal silicon and gaseous carbon oxide CO (at p = 10–300 Pa). Some silicon atoms transform into gaseous silicon oxide SiO and escape from the system, which brings about the formation of vacancies and pores in the silicon near the interface between the silicon and the silicon carbide. These pores provide significant relaxation of the elastic stresses caused by the lattice misfit between Si and SiC. X-ray diffraction, electron diffraction, and electron microscopy studies and luminescence analysis showed that the silicon carbide layers are epitaxial, homogeneous over the thickness, and can contain various polytypes and a mixture of them, depending on the growth conditions. The typical pore size is 1 to 5 μm at film thicknesses of ∼20 to 100 nm. Thermodynamic nucleation theory is generalized to the case where a chemical reaction occurs. Kinetic and thermodynamic theories of this growth mechanism are constructed, and the time dependences of the number of new-phase nuclei, the concentrations of chemical components, and the film thickness are calculated. A model is proposed for relaxation of elastic stresses in a film favored by vacancies and pores in the substrate.

High-speed all-optical modulation using polycrystalline silicon microring resonators

Abstract: We experimentally demonstrate on-chip active photonic devices fabricated from deposited polycrystalline silicon, which can be used for monolithic three-dimensional integration of optical networks. The demonstrated modulator is based on all-optical carrier injection in a micrometer-size resonator and has a modulation depth of 10dB and a temporal response of 135ps. Grain boundaries in the polycrystalline silicon (polysilicon) material result in faster electron-hole recombination, enabling a shortened carrier lifetime and a faster optical switching time compared to similar devices based on crystalline silicon.

Passivation of wide band-gap based semiconductor devices with hydrogen-free sputtered nitrides

Abstract: A passivated semiconductor structure and associated method are disclosed. The structure includes a silicon carbide substrate or layer; an oxidation layer on the silicon carbide substrate for lowering the interface density between the silicon carbide substrate and the thermal oxidation layer; a first sputtered non-stoichiometric silicon nitride layer on the thermal oxidation layer for reducing parasitic capacitance and minimizing device trapping; a second sputtered non-stoichiometric silicon nitride layer on the first layer for positioning subsequent passivation layers further from the substrate without encapsulating the structure; a sputtered stoichiometric silicon nitride layer on the second sputtered layer for encapsulating the structure and for enhancing the hydrogen barrier properties of the passivation layers; and a chemical vapor deposited environmental barrier layer of stoichiometric silicon nitride for step coverage and crack prevention on the encapsulant layer.

Highly stable amorphous-silicon thin-film transistors on clear plastic

Abstract: Hydrogenated amorphous-silicon (a-Si:H) thin-film transistors (TFTs) have been fabricated on clear plastic with highly stable threshold voltages. When operated at a gate field of 2.5×105V∕cm, the threshold voltage shift extrapolated to only ∼1.2V after ten years. This stability is achieved by a high deposition temperature for the gate silicon nitride insulator which reduces charge trapping and high hydrogen dilution during a-Si:H growth to reduce defect creation in a-Si:H. This gate field of 2.5×105V∕cm is sufficient to drive phosphorescent organic light emitting diodes (OLEDs) at a brightness of 1000Cd∕m2. The half-life of the TFT current is over ten years, slightly longer than the luminescence half-life of high quality green OLEDs.

Extremely dense arrays of germanium and silicon nanostructures

Abstract: Results of investigations into surface processes of the formation of germanium and silicon nanostructures are analyzed. A mechanism of three-dimensional island nucleation and relaxation of strained two-dimensional layers in heteroepitaxy of germanium in silicon, which initiates spontaneous island growth, is considered. The oxidation of the silicon surface prior to germanium or silicon deposition drastically alters the growth mechanism, leading to the formation of islands with an extremely high areal density of 1012 – 1013 cm−2 and with sizes of less than 10 nm. The effects of spatial quantization determine their properties. Moreover, arrays of these islands form a unique surface for the growth of Si layers that are able to emit photons in the 1.5–1.6-μm wavelength range.

Carrier Transport in High-Mobility III–V Quantum-Well Transistors and Performance Impact for High-Speed Low-Power Logic Applications

Abstract: DC and high-frequency device characteristics of In0.7Ga0.3As and InSb quantum-well field-effect transistors (QWFETs) are measured and benchmarked against state-of- the-art strained silicon (Si) nMOSFET devices, all measured on the same test bench. Saturation current (Ion) gam of 20% is observed in the In0.7Ga0.3As QWFET over the strained Si nMOSFET at (Vg - Vt) = 0.3 V, Vds = 0.5 V, and matched Ioff, despite higher external resistance and large gate-to-channel thickness. To understand the gain in Ion, the effective carrier velocities (veff) near the source-end are extracted and it is observed that at constant (Vg - Vt) = 0.3 V and Vds = 0.5 V, the veff of In0.7Ga0.3As and InSb QWFETs are 4-5times higher than that of strained silicon (Si) nMOSFETs due to the lower effective carrier mass in the QWFETs. The product of veff and charge density (ns), which is a measure of "intrinsic" device characteristics, for the QWFETs is 50%-70% higher than strained Si at low-voltage operation despite lower ns in QWFETs. Calibrated simulations of In0.7Ga0.3As QWFETs with reduced gate-to-channel thickness and external resistance matched to the strained Si nMOSFET suggest that the higher veff will result in more than 80% Ion increase over strained Si nMOSFETs at Vds = 0.5 V, (Vg - Vt) = 0.3 V, and matched Ioff, thus showing promise for future high-speed and low-power logic applications.

Effects of the compensation level on the carrier lifetime of crystalline silicon

Abstract: This study focuses on the evolution of the carrier lifetime with the compensation level in crystalline silicon. Especially we show that an increase in the compensation level reduces the recombination strength of doping species and of some metal impurities. These theoretical results are confirmed by the chemical and electrical characterizations of strongly compensated multicrystalline silicon wafers. These results are of paramount importance since an accurate control of the compensation level can lead to strong improvements in silicon solar cells efficiencies.

Isolated germanium nanowire on silicon fin

Abstract: The present invention describes a method of and an apparatus for providing a wafer, the wafer including Silicon; etching trenches in the wafer to form Silicon fins; filling Silicon Oxide in the trenches; planarizing the Silicon Oxide; recessing the Silicon Oxide to a first thickness to form exposed Silicon pedestals from the Silicon fins; depositing SiGe over the exposed Silicon pedestal; recessing the Silicon Oxide to a second thickness; undercutting the exposed Silicon pedestals to form necked-in Silicon pedestals; oxidizing thermally and annealing the SiGe; and forming Germanium nanowires.

Thermal stability of amorphous silicon/silicon nitride stacks for passivating crystalline silicon solar cells

Abstract: The thermal stability of amorphous silicon/silicon nitride double layer surface passivation of p-type and n+-type crystalline surfaces is investigated for different deposition temperatures of the silicon nitride capping layer. An increase from 300to400°C results in a significant improvement of the thermal stability of the surface passivation. The minimum surface recombination velocity achieved on p-type (1.5Ωcm) silicon wafers is 0.75±0.6cm∕s and remains at 10±0.5cm∕s after 30min annealing at 500°C.

Phosphorous clustering in germanium-rich silicon germanium

Abstract: The formation of clusters consisting of donor atoms and lattice vacancies can deleteriously affect the performance of silicon germanium devices. In the present study results from electronic structure calculations are evaluated using mass action analysis to identify the extent to which phosphorous-vacancy clusters form in germanium-rich silicon germanium. Although it is energetically favourable to form clusters containing up to four phosphorous atoms, clusters are only important at lower temperatures. At such temperatures the formation of the cluster, in which four phosphorous atoms are tetrahedrally coordinated around a vacancy, is especially stable. At high temperatures unbound vacancies and phosphorous atoms are dominant.

Methods of fabricating silicon carbide power devices by at least partially removing an n-type silicon carbide substrate, and silicon carbide power devices so fabricated

Abstract: A silicon carbide power device is fabricated by forming a p-type silicon carbide epitaxial layer on an n-type silicon carbide substrate, and forming a silicon carbide power device structure on the p-type silicon carbide epitaxial layer. The n-type silicon carbide substrate is at least partially removed, so as to expose the p-type silicon carbide epitaxial layer. An ohmic contact is formed on at least some of the p-type silicon carbide epitaxial layer that is exposed. By at least partially removing the n-type silicon carbide substrate and forming an ohmic contact on the p-type silicon carbide epitaxial layer, the disadvantages of using a p-type substrate may be reduced or eliminated. Related structures are also described.

Method for producing a semiconductor integrated circuit including a thin film transistor and a capacitor

Abstract: The formation of contact holes and a capacitor is performed in a semiconductor integrated circuit such as an active matrix circuit. An interlayer insulator having a multilayer (a lower layer is silicon oxide; an upper layer is silicon nitride) each having different dry etching characteristic is formed. Using a first mask, the silicon nitride corresponding to the upper layer in the interlayer insulator is etched by dry etching. This etching is completed by using the silicon oxide corresponding to the lower layer as an etching stopper. A pattern is formed using a second mask to form selectively the silicon oxide corresponding to the lower layer. Thus a first portion that the silicon oxide and the silicon nitride are etched and a second portion that only silicon nitride is etched are obtained. The first portion is used as a contact hole. A capacitor is formed in the second portion.

Hetero-junction silicon solar cell and fabrication method thereof

Abstract: Disclosed are a hetero-junction silicon solar cell and a fabrication method thereof. The hetero-junction silicon solar cell according to the present invention forms a pn junction of a crystalline silicon substrate and a passivation layer doped with impurities so as to minimize a recombination of electrons and holes, making it possible to maximize efficiency of the hetero-junction silicon solar cell. The present invention provides a hetero-junction silicon solar cell comprising a crystalline silicon substrate and a passivation layer that is formed on the crystalline silicon substrate and is doped with impurities.

Ultra shallow junction formation by epitaxial interface limited diffusion

Abstract: A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.

Silicon carbide semiconductor device and method for producing the same

Abstract: A gate electrode 18 formed on a silicon carbide substrate 11 includes a silicon lower layer 18A and a silicide upper layer 18B provided on the silicon lower layer 18A, the silicide upper layer 18B being made of a compound of a first metal and silicon. A source electrode 1 as formed on the surface of the silicon carbide substrate 11 and in contact with an n type source region and a p+ region contains second metal silicide different from the first metal silicide. Side faces of the silicon lower layer 18A are covered with an insulator.

Device fabrication with solid–liquid–solid grown silicon nanowires

Abstract: High quality, single-crystal silicon nanowires were successfully grown from silicon wafers with a nickel catalyst by utilizing a solid–liquid–solid (SLS) mechanism. The nanowires were composed of a crystalline silicon core with an average diameter of 10 nm and a thick outer oxide layer of between 20 and 30 nm at a growth temperature of 1000 °C. When utilizing the SLS growth mechanism, the diameter of the silicon nanowire is dependent solely upon the growth temperature, and has no relation to either the size or the shape of the catalyst. The characteristics of the silicon nanowires are highly dependent upon the properties of the silicon substrate, such as the crystal phase of silicon itself, as well as the doping type. The possibility of doping of silicon nanowires grown via the SLS mechanism without any external dopant source was demonstrated by measuring the electrical properties of a silicon nanowire field effect transistor.

Highly efficient tip-enhanced Raman spectroscopy and microscopy of strained silicon.

Abstract: We present a versatile tip-enhanced Raman spectroscopy (TERS) system that permits efficient illumination and detection of optical properties in the visible range to obtain high signal-to-noise Raman signals from surfaces and interfaces of materials using an edge filter. The cutoff wavelength of the edge filter is tuned by changing the angle of incident beam to deliver high incident power and effectively collect scattered near-field signals for nanoscopic investigation in depolarized TERS configuration. The dynamic design of the instrument provides a unique combination of features that allows us to perform reflection or transmission mode TERS to cover both opaque and transparent samples. A detailed description of improvements of TERS was carried out on a thin strained silicon surface layer. The utilization of an edge filter for shorter collection time, specialized tip for higher field enhancement and for elimination of Raman signal from the tip, shorter wavelength, sample orientation relative to probing polarization, and depolarized configuration for higher contrast Raman signal is discussed.

Microscopic description of light induced defects in amorphous silicon solar cells.

Abstract: Using a combination of quantum and classical computational approaches, we model the electronic structure in amorphous silicon in order to gain an understanding of the microscopic atomic configurations responsible for light-induced degradation of solar cells. We demonstrate that regions of strained silicon bonds could be as important as dangling bonds for creating traps for charge carriers. Further, our results show that defects are preferentially formed when a region in the amorphous silicon contains both a hole and a light-induced excitation. These results are consistent with the puzzling dependencies on temperature, time, and pressure observed experimentally.

Efficiency and reliability enhancement of silicon nanocrystal field-effect luminescence from nitride-oxide gate stacks

Abstract: We report on a field-effect light emitting device based on silicon nanocrystals in silicon oxide deposited by plasma-enhanced chemical vapor deposition. The device shows high power efficiency and long lifetime. The power efficiency is enhanced up to ∼0.1% by the presence of a silicon nitride control layer. The leakage current reduction induced by this nitride buffer effectively increases the power efficiency two orders of magnitude with regard to similarly processed devices with solely oxide. In addition, the nitride cools down the electrons that reach the polycrystalline silicon gate lowering the formation of defects, which significantly reduces the device degradation.

Strain relaxation in transistor channels with embedded epitaxial silicon germanium source/drain

Abstract: We report on the channel strain relaxation in transistors with embedded silicon germanium layer selectively grown in source and drain areas on recessed Si(001). Nanobeam electron diffraction is used to characterize the local strain in the device channel. Our results show that strain is reduced in the device channel regions after implantation and thermal anneal.

Boron activation and diffusion in silicon and strained silicon-on-insulator by rapid thermal and flash lamp annealings

Abstract: We present experimental results on the activation and diffusion behaviors of boron in silicon-on-insulator and strained silicon-on-insulator using standard rapid thermal processing treatments as well as flash lamp annealing. After boron implantation at different doses and at a low energy of 1 keV, samples were annealed to activate the dopants, and secondary ion mass spectrometry and Hall measurements were carried out to determine boron diffusion and the amount of activated dopants, respectively. In contrast to rapid thermal annealing, flash lamp annealing enables the activation without significant diffusion of dopants. In addition, we investigated the effect of coating the samples with antireflection layers to increase the absorbed energy during flash annealing. As a result, the activation was increased significantly to values comparable with the activation obtained with standard annealing. Furthermore, the relation between the observed boron diffusion and activation as a function of the implantation and ...

Hydrogen diffusion in silicon from plasma-enhanced chemical vapor deposited silicon nitride film at high temperature

Abstract: The stable hydrogen isotope deuterium (D), which is released during the annealing of deuterated silicon nitride films, diffuses through the crystalline silicon and is captured by a thin, amorphous layer of silicon sputtered on the rear surface. We report on the measurement of the concentration of “penetrated” D by secondary ion mass spectrometry to monitor the flux of D diffusing through single-crystalline silicon wafers. The penetrated D content in the trapping layer increases with the annealing time. However, the flux of D injected into the silicon from the silicon nitride layer decreases as annealing time increases.

Measurement of Enhanced Gate-Controlled Band-to-Band Tunneling in Highly Strained Silicon-Germanium Diodes

Abstract: Strained silicon-germanium (Si0.6Ge0.4) gated diodes have been fabricated and analyzed. The devices exhibit significantly enhanced gate-controlled tunneling current over that of coprocessed silicon control devices. The current characteristics are insensitive to measurement temperature in the 80 K to 300 K range. Independently extracted valence band offset at the strained Si0.6Ge0.4/Si interface is 0.4 eV, yielding a Si0.6Ge0.4 bandgap of 0.7 eV, which is much reduced compared to that of Si. The results are consistent with device operation based on quantum-mechanical band-to-band (BTB) tunneling rather than on thermal generation. Moreover, simulation of the strained Si0.6Ge0.4 device using a quantum-mechanical BTB tunneling model is in good agreement with the measurements.

Group-III nitride epitaxial layer on silicon substrate

Abstract: A semiconductor device includes a silicon substrate; silicon faceted structures formed on a top surface of the silicon substrate; and a group-III nitride layer over the silicon faceted structures. The silicon faceted structures are separated from each other, and have a repeated pattern.

Silicon carbide semiconductor substrate and silicon carbide semiconductor device by using thereof

Abstract: A manufacturing method is provided for a silicon carbide semiconductor substrate adapted for reduced basal plane dislocations in a silicon carbide epitaxial layer. Between a silicon carbide epitaxial layer for device fabrication (i.e., a drift layer) and a base substrate formed of a silicon carbide single-crystal wafer, a highly efficient dislocation conversion layer through which any basal plane dislocations in the silicon carbide single-crystal wafer are converted into threading edge dislocations very efficiently when the dislocations propagate into the layer epitaxially grown is provided by epitaxial growth. Assigning to the dislocation conversion layer a donor concentration lower than that of the drift layer, therefore, allows the above conversion of a larger number of basal plane dislocations than the case where the drift layer exists alone (without the dislocation conversion layer).