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Showing papers on "Strained silicon published in 2011"


Journal ArticleDOI
TL;DR: Because monolayer MoS(2) has a direct bandgap, it can be used to construct interband tunnel FETs, which offer lower power consumption than classical transistors, and could also complement graphene in applications that require thin transparent semiconductors, such as optoelectronics and energy harvesting.
Abstract: Two-dimensional materials are attractive for use in next-generation nanoelectronic devices because, compared to one-dimensional materials, it is relatively easy to fabricate complex structures from them. The most widely studied two-dimensional material is graphene, both because of its rich physics and its high mobility. However, pristine graphene does not have a bandgap, a property that is essential for many applications, including transistors. Engineering a graphene bandgap increases fabrication complexity and either reduces mobilities to the level of strained silicon films or requires high voltages. Although single layers of MoS(2) have a large intrinsic bandgap of 1.8 eV (ref. 16), previously reported mobilities in the 0.5-3 cm(2) V(-1) s(-1) range are too low for practical devices. Here, we use a halfnium oxide gate dielectric to demonstrate a room-temperature single-layer MoS(2) mobility of at least 200 cm(2) V(-1) s(-1), similar to that of graphene nanoribbons, and demonstrate transistors with room-temperature current on/off ratios of 1 × 10(8) and ultralow standby power dissipation. Because monolayer MoS(2) has a direct bandgap, it can be used to construct interband tunnel FETs, which offer lower power consumption than classical transistors. Monolayer MoS(2) could also complement graphene in applications that require thin transparent semiconductors, such as optoelectronics and energy harvesting.

12,477 citations


Journal ArticleDOI
TL;DR: Electro-optic characterization yields a record high value χ(2)(yyz) = 122 pm/V for the second-order susceptibility of the strained silicon waveguide and a strict linear dependence between the applied modulation voltage V(mod) and the resulting effective index change Δn(eff).
Abstract: We demonstrate for the first time a fully integrated electro-optic modulator based on locally strained silicon rib-waveguides. By depositing a Si3N4 strain layer directly on top of the silicon waveguide the silicon crystal is asymmetrically distorted. Thus its inversion symmetry is broken and a linear electro-optic effect is induced. Electro-optic characterization yields a record high value χ(2)yyz = 122 pm/V for the second-order susceptibility of the strained silicon waveguide and a strict linear dependence between the applied modulation voltage Vmod and the resulting effective index change Δneff. Spatially resolved micro-Raman and terahertz (THz) difference frequency generation (DFG) experiments provide in-depth insight into the origin of the electro-optic effect by correlating the local strain distribution with the observed second-order optical activity.

190 citations


Book
07 Mar 2011
TL;DR: In this article, the Monte Carlo method for the Boltzmann transport equation was used to compute the equi-energy lines with the k-p model and the charge density produced by a perturbation potential.
Abstract: 1. Introduction 2. Bulk semiconductors and the semi-classical model 3. Quantum confined inversion layers 4. Carrier scattering in silicon MOS transistors 5. The Boltzmann transport equation 6. The Monte Carlo method for the Boltzmann transport equation 7. Simulation of bulk and SOI silicon MOSFETs 8. MOS transistors with arbitrary crystal orientation 9. MOS transistors with strained silicon channels 10. MOS transistors with alternative materials Appendix A. Mathematical definitions and properties Appendix B. Integrals and transformations over a finite area A Appendix C. Calculation of the equi-energy lines with the k-p model Appendix D. Matrix elements beyond the envelope function approximation Appendix E. Charge density produced by a perturbation potential.

138 citations


Patent
29 Jun 2011
TL;DR: In this article, the authors describe methods for fabricating a FINFET integrated circuit that includes epitaxially growing a first silicon germanium layer and a second silicon layer overlying a silicon substrate.
Abstract: Methods are provided for fabricating a FINFET integrated circuit that includes epitaxially growing a first silicon germanium layer and a second silicon layer overlying a silicon substrate. The second silicon layer is etched to form a silicon fin using the first silicon germanium layer as an etch stop. The first silicon germanium layer underlying the fin is removed to form a void underlying the fin and the void is filled with an insulating material. A gate structure is then formed overlying the fin.

133 citations


Journal ArticleDOI
TL;DR: In this article, the compatibility of GeSn materials with source/drain engineering processes (B implantation and activation and NiGeSn formation) has been studied, and a low thermal budget has been determined for those processes on GeSn alloys.

107 citations


Patent
09 Sep 2011
TL;DR: In this paper, a method of fabricating and a structure of a merged multi-fin finFET is proposed, which includes forming single-crystal silicon fin from the silicon layer of an SOI substrate having a very thin buried oxide layer and merging the end regions of the fins by growing vertical epitaxial silicon from the substrate and horizontal epitaxially silicon from ends of the fin such that vertical epitaxisial silicon growth predominates.
Abstract: A method of fabricating and a structure of a merged multi-fin finFET. The method includes forming single-crystal silicon fins from the silicon layer of an SOI substrate having a very thin buried oxide layer and merging the end regions of the fins by growing vertical epitaxial silicon from the substrate and horizontal epitaxial silicon from ends of the fins such that vertical epitaxial silicon growth predominates.

83 citations


Journal ArticleDOI
TL;DR: A quantum mechanical superposition of a long-lived, localized phonon and a matter excitation is described and results indicate that single or many-body devices based on these systems are experimentally realizable.
Abstract: A quantum mechanical superposition of a long-lived, localized phonon and a matter excitation is described. We identify a realization in strained silicon: a low-lying donor transition (P or Li) driven solely by acoustic phonons at wavelengths where high-Q phonon cavities can be built. This phonon-matter resonance is shown to enter the strongly coupled regime where the "vacuum" Rabi frequency exceeds the spontaneous phonon emission into noncavity modes, phonon leakage from the cavity, and phonon anharmonicity and scattering. We introduce a micropillar distributed Bragg reflector Si/Ge cavity, where Q≃10(5)-10(6) and mode volumes V≲25λ(3) are reachable. These results indicate that single or many-body devices based on these systems are experimentally realizable.

80 citations


Journal ArticleDOI
TL;DR: In this article, the authors identify the silicon nitride matrix itself as responsible for the photoluminescence, and conclude that silicon nanocrystal films are inappropriate if one aims at investigating photolumininescence from silicon nanoparticles within such a matrix.
Abstract: Silicon nitride compounds emit photoluminescence all over the visible range. Recent studies ascribed this luminescence to quantum-size effects within silicon nanocrystals that were either shown or assumed to form inside the silicon nitride matrix; the luminescence of the matrix itself was ignored. In contrast, observing the same luminescence even without the presence of silicon crystallites, our work identifies the silicon nitride matrix itself as responsible for the photoluminescence. All experimental observations are well explained by band tail luminescence from the silicon matrix. In contrast to the silicon nanocrystal approach, our model explains all aspects of the luminescence. As a consequence, we conclude that silicon nitride films are inappropriate if one aims at investigating photoluminescence from silicon nanocrystals within such a matrix.

79 citations


Patent
Sungkwan Kang1, Keum Seok Park1, Byeong-Chan Lee1, Sang-Bom Kang1, Nam-Kyu Kim1 
08 Jun 2011
TL;DR: In this article, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween, and a silicon layer is formed to cap the epitaxial layer.
Abstract: A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.

78 citations


Journal ArticleDOI
TL;DR: The anisotropic thermoelectric transport properties of biaxially strained silicon were studied with the focus on a possible enhancement of the power factor to understand the fact that the thermopower decreases if degenerate bands are energetically lifted due to a strain-induced redistribution of states.
Abstract: On the basis of detailed first-principles calculations the anisotropic thermoelectric transport properties of biaxially strained silicon were studied with the focus on a possible enhancement of the power factor. Electron as well as hole doping was examined in a broad doping and temperature range. In the low temperature and low doping regime an enhancement of the power factor was obtained for compressive and tensile strain in the electron-doped case, and for compressive strain in the hole-doped case. In the thermoelectrically more important high temperature and high doping regime a slight enhancement of the power factor was only found for the hole-doped case under small biaxial tensile strain. The results are discussed in terms of band structure effects. An analytical model is presented to understand the fact that the thermopower decreases if degenerate bands are energetically lifted due to a strain-induced redistribution of states.

61 citations


Journal ArticleDOI
TL;DR: In this article, a detailed material study of ultrafast laser textured silicon surfaces was performed to gain insight into the impact of ultra fast laser processing conditions on photovoltaic device properties.

Patent
10 May 2011
TL;DR: In this paper, an epitaxial silicon carbide single-crystal substrate is constructed by repeating a dope layer that is 0.5 µm or less, followed by a non-dope layer of 0.1 µm, where the dope layer is formed with the ratio of the number of carbon atoms in a material gas being 1.5 to 2.0.
Abstract: Provided is an epitaxial silicon carbide single-crystal substrate in which a silicon carbide epitaxial film having excellent in-plane uniformity of doping density is disposed on a silicon carbide single-crystal substrate having an off angle that is between 1o to 6o. The epitaxial film is grown by repeating a dope layer that is 0.5 µm or less and a non-dope layer that is 0.1 µm or less. The dope layer is formed with the ratio of the number of carbon atoms to the number of silicon atoms (C/Si ratio) in a material gas being 1.5 to 2.0, and the non-dope layer is formed with the C/Si ratio being 0.5 or more but less than 1.5. The resulting epitaxial silicon carbide single-crystal substrate comprises a high-quality silicon carbide epitaxial film, which has excellent in-plane uniformity of doping density, on a silicon carbide single-crystal substrate having a small off angle.

Patent
12 Aug 2011
TL;DR: In this article, a tensile strained germanium is provided that can be sufficiently strained to provide a nearly direct band gap material or a direct-band gap material, which can be used to emit or detect photons.
Abstract: Tensile strained germanium is provided that can be sufficiently strained to provide a nearly direct band gap material or a direct band gap material. Compressively stressed or tensile stressed stressor materials in contact with germanium regions induce uniaxial or biaxial tensile strain in the germanium regions. Stressor materials may include silicon nitride or silicon germanium. The resulting strained germanium structure can be used to emit or detect photons including, for example, generating photons within a resonant cavity to provide a laser.


Journal ArticleDOI
TL;DR: The authors' studies rule out the influence of defects in the PL emission, and it is proposed that owing to the combined effect of strain and quantum confinement, the strained Si NCs exhibit direct band gap-like behavior.
Abstract: In this article, we report on the visible absorption, photoluminescence (PL), and fast PL decay dynamics from freestanding Si nanocrystals (NCs) that are anisotropically strained. Direct evidence of strain-induced dislocations is shown from high-resolution transmission electron microscopy images. Si NCs with sizes in the range of approximately 5-40 nm show size-dependent visible absorption in the range of 575-722 nm, while NCs of average size <10 nm exhibit strong PL emission at 580-585 nm. The PL decay shows an exponential decay in the nanosecond time scale. The Raman scattering studies show non-monotonic shift of the TO phonon modes as a function of size because of competing effect of strain and phonon confinement. Our studies rule out the influence of defects in the PL emission, and we propose that owing to the combined effect of strain and quantum confinement, the strained Si NCs exhibit direct band gap-like behavior.

Journal ArticleDOI
TL;DR: In this paper, a gate-first flow was used to preserve uniaxial tensile strain in the transistors of strained-silicon-on-insulator (SSOI) undoped-body high-κ /metal-gate n-channel fin-shaped field effect transistors (nFinFETs).
Abstract: Strained-silicon-on-insulator (SSOI) undoped-body high-κ /metal-gate n-channel fin-shaped field-effect transistors (nFinFETs) at scaled gate lengths and pitches (i.e.,LGATE ~ 25 nm and a contacted gate pitch of 130 nm) were fabricated using a gate-first flow. A “long and narrow” fin layout (i.e., fin length ~ 1 μm) was leveraged to preserve uniaxial tensile strain in the transistors. These devices exhibit drive currents suitable for high-performance logic technology. The change in the slope of RON - LGATE (dRON/dLGATE), transconductance GMSAT, and injection velocity (vinj) measurements indicate a ~ 15% mobility-induced ION enhancement with SSOI relative to SOI nFinFETs at ultrashort gate lengths. Raman measurements conducted on SSOI substrates after fin formation demonstrate the preservation of ~ 1.3-GPa uniaxial tensile strain even after 1100°C annealing.

Patent
Sei-Hyung Ryu1
15 Mar 2011
TL;DR: In this paper, an n-type drift layer, a first p-type silicon carbide region adjacent to the drift layer and having an oxide layer on the drifting layer, and an N-type limiting region disposed between the drift and a portion of the first P-type region are discussed.
Abstract: Silicon carbide metal-oxide semiconductor field effect transistors (MOSFETs) may include an n-type silicon carbide drift layer, a first p-type silicon carbide region adjacent the drift layer and having a first n-type silicon carbide region therein, an oxide layer on the drift layer, and an n-type silicon carbide limiting region disposed between the drift layer and a portion of the first p-type region. The limiting region may have a carrier concentration that is greater than the carrier concentration of the drift layer. Methods of fabricating silicon carbide MOSFET devices are also provided.

Journal ArticleDOI
TL;DR: Using the technique of TE/TM mode birefringence, waveguide geometries for both slab and strip channel waveguides are derived that offer perfect phase matching of three lightwaves for SHG/SFG along a uniform waveguide, thereby offering the prospect of efficient wavelength conversion in monolithic silicon photonics.
Abstract: Using analysis and numerical simulation, we have investigated near-infrared and mid-infrared second-harmonic generation (SHG) and sum frequency generation (SFG) in crystal silicon (SOI) waveguides that possess a strong second-order nonlinear susceptibility by virtue of a Si3N4 straining layer applied directly to the top surface of the waveguide. This layer induces anisotropic compressive strain in the waveguide core. Using the technique of TE/TM mode birefringence, we have derived waveguide geometries for both slab and strip channel waveguides that offer perfect phase matching of three lightwaves for SHG/SFG along a uniform waveguide, thereby offering the prospect of efficient wavelength conversion in monolithic silicon photonics.

Patent
27 Sep 2011
TL;DR: In this article, a noble-metal alloy particle is used to catalyze the oxidation of the silicon wafer substrate surface in contact therewith, and an etchant is then used to simultaneous etch the silicon dioxide to result in local micro-etching at the surface of the substrate.
Abstract: A method of forming micro-pore structures or trench structures on a surface of a silicon wafer substrate comprises (A) forming at least a noble-metal alloy particle on the surface of the silicon wafer substrate; and (B) then followed by employing a chemical wet etching on the surface of the silicon wafer substrate. During the processes, noble-metal alloy particle is used to catalyze the oxidation of the silicon wafer substrate surface in contact therewith, and an etchant is used to simultaneous etch the silicon dioxide to result in local micro-etching at the surface of the silicon wafer substrate, thereby forming micro-pore structures or trench structures on the surface of the silicon wafer substrate. The method increases the power conversion efficiency of the solar cells and reduces the manufacturing costs so as to increase the production benefits of the solar cells.

Journal ArticleDOI
TL;DR: This work has developed a method to excite the "forbidden" transverse-optical phonons in single tensile strained silicon nanowires using high-resolution polarized Raman spectroscopy, and inferred mechanical properties are inferred from the measured strain profiles.
Abstract: The accurate manipulation of strain in silicon nanowires can unveil new fundamental properties and enable novel or enhanced functionalities. To exploit these potentialities, it is essential to overcome major challenges at the fabrication and characterization levels. With this perspective, we have investigated the strain behavior in nanowires fabricated by patterning and etching of 15 nm thick tensile strained silicon (100) membranes. To this end, we have developed a method to excite the “forbidden” transverse-optical (TO) phonons in single tensile strained silicon nanowires using high-resolution polarized Raman spectroscopy. Detecting this phonon is critical for precise analysis of strain in nanoscale systems. The intensity of the measured Raman spectra is analyzed based on three-dimensional field distribution of radial, azimuthal, and linear polarizations focused by a high numerical aperture lens. The effects of sample geometry on the sensitivity of TO measurement are addressed. A significantly higher se...

Journal ArticleDOI
TL;DR: In this paper, the authors demonstrate that Si-XII and Si-III can be formed under pressure applied by nanoindentation and these phases are metastable at room temperature and pressure.
Abstract: Conventional silicon devices are fabricated in the diamond cubic phase of silicon, so-called Si-I. Other phases of silicon such as Si-XII and Si-III can be formed under pressure applied by nanoindentation and these phases are metastable at room temperature and pressure. We demonstrate in this letter that such phases exhibit different electrical properties to normal (diamond cubic) silicon and exploit this to perform maskless, room temperature, electrical patterning of silicon by writing both conductive and insulating zones directly into silicon substrates by nanoindentation. Such processing opens up a number of potentially new applications without the need for high temperature processing steps.

Proceedings ArticleDOI
01 Oct 2011
TL;DR: In this article, the opportunities, limits and challenges for future silicon-based field effect transistors (FETs) tailored for radio frequency (RF) and millimeter (mm)-wave circuit design are discussed.
Abstract: In this paper, the opportunities, limits and challenges for future silicon-based field effect transistors (FETs) tailored for radio frequency (RF) and millimeter (mm)-wave circuit design are discussed. After the review of CMOS FET scaling down to the 10 nm node, advanced CMOS techniques such as silicon on insulator (SOI), strained silicon, high-k, low temperature and multigate transistors are treated. Moreover, emerging Beyond CMOS FET concepts based on silicon nanowires, graphene and carbon nano tubes (CNTs) are discussed as potential replacement or extension to CMOS.

Journal ArticleDOI
TL;DR: In this paper, the effect of the parasitic source/drain resistance on the piezoresistive coefficient determination is addressed in detail, and the model is implemented a general relation to calculate the coefficients for arbitrary directions of current and stress in the (0, 0, 1) silicon (Si) plane.
Abstract: This paper presents a novel implementation of variable uniaxial mechanical stress model to be used with DC circuit simulation, e.g. using BSIM3v3 transistor model. Based on transistor measurements under various uniaxial stress conditions two stress-dependent parameters are identified, namely the carriers mobility and to a lesser extend the carrier saturation velocity. The effect of the parasitic source/drain resistance on the piezoresistive coefficient determination is addressed in detail. Using the fundamental piezoresistive coefficients, the model has implemented a general relation to calculate the coefficients for arbitrary directions of current and stress in the (0 0 1) silicon (Si) plane. The extended transistor model allows for simulating the effect of uniaxial stress on any MOSFET geometry, under different operation conditions and for any combination of the drain current and stress orientations in the (0 0 1) silicon (Si) plane. The method proposed in this paper is validated by static and dynamic stress-dependent simulations and comparison with experimental data. The method is simulator-independent and can be adapted to other bulk CMOS technologies including SOI processes.

Patent
15 Nov 2011
TL;DR: In this paper, a method for producing an epitaxial silicon carbide single crystal substrate with a small off angle was proposed, in which a hydrogen gas and a gas containing silicon and chlorine are flowed such that the concentration of silicon atoms with respect to hydrogen atoms in the hydrogen gas is 0.0001% to 0.01%.
Abstract: The purpose of the invention is to provide a method for producing an epitaxial silicon carbide single crystal substrate which has a high quality silicon carbide single crystal thin film with less surface defects, etc. on a silicon carbide single crystal substrate with a small off angle. According to the present invention, in the method for producing an epitaxial silicon carbide single crystal substrate which has a high quality silicon carbide single crystal thin film with less surface defects, etc. on a silicon carbide single crystal substrate with an off angle of 4° or less, prior to epitaxial growth, a hydrogen gas and a gas containing silicon and chlorine are flowed such that the concentration of silicon atoms with respect to hydrogen atoms in the hydrogen gas is 0.0001% to 0.01%, and after a pre-treatment etching of 0.1 μm to 1 μm at a temperature of 1550°C to 1650°C is carried out, an epitaxial layer is formed.

Journal ArticleDOI
TL;DR: In this paper, a relaxed SiGe/strained Si enhancement-mode gate stack for quantum dots is proposed and demonstrated in a 150 mm Si foundry setting that uses implanted ohmics and chemical-vapor-deposited dielectrics.
Abstract: We propose and demonstrate a relaxed-SiGe/strained-Si enhancement-mode gate stack for quantum dots. A mobility of 1.6 × 105 cm2/Vs at 5.8 × 1011/cm2 is measured in Hall bars that witness the same device process flow as the quantum dot. Periodic Coulomb blockade measured in a double-top-gated lateral quantum dot nanostructure terminates with open diamonds up to ±10 mV of dc voltage across the device. The devices were fabricated within a 150 mm Si foundry setting that uses implanted ohmics and chemical-vapor-deposited dielectrics. A modified implant, polycrystalline silicon formation and annealing conditions were utilized to minimize the thermal budget that potentially leads to Ge/Si interdiffusion.

Journal ArticleDOI
TL;DR: In this article, a relaxed SiGe/strained Si (SiGe/s-Si) enhancement-mode gate stack for quantum dots is proposed and demonstrated in a double-top-gated lateral quantum dot nanostructure.
Abstract: We propose and demonstrate a relaxed-SiGe/strained-Si (SiGe/s-Si) enhancement-mode gate stack for quantum dots. The enhancement-mode SiGe/s-Si structure is pursued because it spaces the quantum dot away from charge and spin defect rich dielectric interfaces and minimizes background dopants. A mobility of 1.6\times10^5 cm^2/Vs at 5.8\times10^{11}/cm^2 is measured in Hall bars that witness the same device process flow as the quantum dot. Periodic Coulomb blockade (CB) is measured in a double-top-gated lateral quantum dot nanostructure. The CB terminates with open diamonds up to \pm 10 mV of DC voltage across the device. The devices were fabricated within a 150 mm Si foundry setting that uses implanted ohmics and chemical-vapor-deposited dielectrics, in contrast to previously demonstrated enhancement-mode SiGe/s-Si structures made with AuSb alloyed ohmics and atomic-layer-deposited dielectric. A modified implant, polysilicon formation and annealing conditions were utilized to minimize the thermal budget so that the buried s-Si layer would not be washed out by Ge/Si interdiffusion.

Patent
08 Mar 2011
TL;DR: In this paper, a photovoltaic (PV) device with improved blue response is presented, which includes a silicon substrate with an emitter layer on a light receiving side.
Abstract: A photovoltaic (PV) device with improved blue response. The PV device includes a silicon substrate with an emitter layer on a light receiving side. The emitter layer has a low opant level such that it has sheet resistance of 90 to 170 ohm/sq. Anti-reflection in the PV device is provided solely by a nanostructured or black silicon surface on the light-receiving surface, through which the emitter is formed by diffusion. The nanostructures of the black silicon are formed in a manner that does not result in gold or another high-recombination metal being left in the black silicon such as with metal-assisted etching using silver. The black silicon is further processed to widen these pores so as to provide larger nanostructures with lateral dimensions in the range of 65 to 150 nanometers so as to reduce surface area and also to etch away a highly doped portion of the emitter.

Proceedings ArticleDOI
Terence B. Hook1, Maud Vinet, R. Murphy1, Shom Ponoth1, Laurent Grenouillet 
01 Dec 2011
TL;DR: In this article, the authors examined threshold voltage matching as a function of silicon thickness variation in ETSOI (Extremely Thin Silicon On Insulator) transistors and found that mismatch due to silicon thickness variations is not random and is not therefore to be described by the conventional area dependence.
Abstract: In this work we examine threshold voltage matching as a function of silicon thickness variation in ETSOI (Extremely Thin Silicon On Insulator) transistors. Analysis of silicon thickness data in terms of threshold voltage and direct experimental measurements of matching lead to several specific observations: that mismatch due to silicon thickness variation is not random and is not therefore to be described by the conventional area dependence; that adjacent transistors are very closely matched; that silicon wafer processing can modulate the variation and therefore the matching.

Journal ArticleDOI
TL;DR: Convergent beam electron diffraction and geometric phase analysis were used to measure strain in the gate channel of a p‐type strained silicon metal–oxide–semiconductor field‐effect transistor allowing for direct comparison of the relative advantages of each technique.
Abstract: Summary Convergent beam electron diffraction and geometric phase analysis were used to measure strain in the gate channel of a p-type strained silicon metal–oxide–semiconductor field-effect transistor. These measurements were made on exactly the same transmission electron microscopy specimen allowing for direct comparison of the relative advantages of each technique. The trends in the strain values show good agreement in both the [] and [001] directions, but the absolute strain values are offset from each other. This difference in the absolute strain measured using the two techniques is attributed to the way the reference strain is defined for each.

Patent
Chi-Ming Chen1, Po-Chun Liu1, Hung-Ta Lin1, Chung-Yi Yu1, Chia-Shiung Tsai1, Ho-Yung David Hwang1 
01 Dec 2011
TL;DR: A semiconductor structure includes a silicon substrate, more than one bulk layer of group-III/group-V (III-V) compound semiconductor atop the silicon substrate; and each bulk layer is separated by an interlayer.
Abstract: A semiconductor structure includes a silicon substrate; more than one bulk layer of group-III/group-V (III-V) compound semiconductor atop the silicon substrate; and each bulk layer of the group III-V compound is separated by an interlayer.