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Showing papers on "Strained silicon published in 2014"


Proceedings ArticleDOI
01 Dec 2014
TL;DR: In this paper, a 14nm logic technology using 2nd-generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described.
Abstract: A 14nm logic technology using 2nd-generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described. The transistors feature rectangular fins with 8nm fin width and 42nm fin height, 4th generation high-k metal gate, and 6th-generation strained silicon, resulting in the highest drive currents yet reported for 14nm technology. This technology is in high-volume manufacturing.

558 citations


Journal ArticleDOI
TL;DR: In this article, the authors explore substoichiometric molybdenum trioxide (MoOx, x < 3) as a dopant-free, hole-selective contact for silicon solar cells.
Abstract: We explore substoichiometric molybdenum trioxide (MoOx, x < 3) as a dopant-free, hole-selective contact for silicon solar cells. Using an intrinsic hydrogenated amorphous silicon passivation layer between the oxide and the silicon absorber, we demonstrate a high open-circuit voltage of 711 mV and power conversion efficiency of 18.8%. Due to the wide band gap of MoOx, we observe a substantial gain in photocurrent of 1.9 mA/cm2 in the ultraviolet and visible part of the solar spectrum, when compared to a p-type amorphous silicon emitter of a traditional silicon heterojunction cell. Our results emphasize the strong potential for oxides as carrier selective heterojunction partners to inorganic semiconductors.

358 citations


Journal ArticleDOI
TL;DR: This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack.
Abstract: The performance of strained silicon (Si) as the channel material for today's metal-oxide-semiconductor field-effect transistors may be reaching a plateau. New channel materials with high carrier mobility are being investigated as alternatives and have the potential to unlock an era of ultra-low-power and high-speed microelectronic devices. Chief among these new materials is germanium (Ge). This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack. Next, Ge is compared to compound III-V materials in terms of p-channel device performance to review how it became the first choice for PMOS devices. Different Ge device architectures, including surface channel and quantum well configurations, are reviewed. Finally, state-of-the-art Ge device results and future prospects are also discussed.

128 citations


Patent
31 Mar 2014
TL;DR: In this paper, the etch of two doped silicon portions at two different etch rates is described. And the etches are shown to reduce trapped charges during use and increase the lifespan of flash memory devices.
Abstract: Methods of etching two doped silicon portions at two different etch rates are described. An n-type silicon portion may be etched faster than a p-type silicon portion when both are exposed and present on the same substrate. The n-type silicon portion may be doped with phosphorus and the p-type silicon portion may be doped with boron. In one example, the n-type silicon portion is single crystal silicon and the p-type silicon portion is polycrystalline silicon (a.k.a. polysilicon). The p-type silicon portion may be a polysilicon floating gate in a flash memory cell and may be located above a gate silicon oxide which, in turn, is above an n-type active area single crystal silicon portion. The additional trimming of the n-type active area silicon portion may reduce the accumulation of trapped charges during use and increase the lifespan of flash memory devices.

122 citations


Patent
13 Jan 2014
TL;DR: In this paper, a method of isotropically etching a dielectric film involves partially modifying exposed regions of a silicon nitride layer with an oxygen-based plasma process to provide a modified portion and an unmodified portion.
Abstract: Methods of patterning silicon nitride dielectric films are described. For example, a method of isotropically etching a dielectric film involves partially modifying exposed regions of a silicon nitride layer with an oxygen-based plasma process to provide a modified portion and an unmodified portion of the silicon nitride layer. The method also involves removing, selective to the unmodified portion, the modified portion of the silicon nitride layer with a second plasma process.

118 citations


Patent
05 Aug 2014
TL;DR: In this article, the authors described methods of etching back an oxide-nitride-oxide (ONO) layer of a 3-D flash memory cell without breaking vacuum.
Abstract: Methods of etching back an oxide-nitride-oxide (ONO) layer of a 3-d flash memory cell without breaking vacuum are described. The methods include recessing the two outer silicon oxide dielectric layers to expose the flanks of the thin silicon nitride layer. The silicon nitride layer is then etched back from all exposed sides to hasten the process on the same substrate processing mainframe. Both etching back the silicon oxide and etching back the silicon nitride use remotely excited fluorine-containing apparatuses attached to the same mainframe to facilitate performing both operations without an intervening atmospheric exposure. The process may also be reversed such that the silicon nitride is etched back first.

109 citations


Patent
03 Jul 2014
TL;DR: In this article, the authors describe the formation of a transistor using low-K dielectric constant material (e.g., a void) between an elongated gate and a contact to increase the attainable switching speed of the device.
Abstract: Transistors and their methods of formation are described. Low dielectric constant material (e.g. a void) is placed between an elongated gate and a contact to increase the attainable switching speed of the gate of the device. An elongated structural slab of silicon nitride is temporarily positioned on both sides of the gate. Silicon oxide is formed over the silicon nitride slabs and the gate. Contacts are formed through the silicon oxide. The silicon oxide is selectively etched back to expose the silicon nitride slab. A portion or all the silicon nitride slab is removed and replaced with low-K dielectric or any dielectric with an air-gap to enable higher switching speed of the transistor. The highly-selective silicon nitride etch uses remotely excited fluorine and a very low electron temperature in the substrate processing region.

104 citations


Journal ArticleDOI
TL;DR: It is found that the concentration of metal impurities in crystalline silicon nanowires increases with the growth rate and can reach a level of two orders of magnitude higher than that in their equilibrium solubility.
Abstract: The incorporation of metal atoms into silicon nanowires during metal-particle-assisted growth is a critical issue for various nanowire-based applications. Here we have been able to access directly the incorporation and redistribution of metal atoms into silicon nanowires produced by two different processes at growth rates ranging from 3 to 40 nm s(-1), by using laser-assisted atom probe tomography and scanning transmission electron microscopy. We find that the concentration of metal impurities in crystalline silicon nanowires increases with the growth rate and can reach a level of two orders of magnitude higher than that in their equilibrium solubility. Moreover, we demonstrate that the impurities are first incorporated into nanowire volume and then segregate at defects such as the twin planes. A dimer-atom-insertion kinetic model is proposed to account for the impurity incorporation into nanowires.

103 citations


Journal ArticleDOI
TL;DR: A review of recent advances in the field of epitaxial growth of SiC films on Si by means of a new method of substitution of film atoms for substrate atoms has been presented in this article.
Abstract: A review of recent advances in the field of epitaxial growth of SiC films on Si by means of a new method of epitaxial substitution of film atoms for substrate atoms has been presented. The basic statements of the theory of the new method used for synthesizing SiC on Si have been considered and extensive experimental data have been reported. The elastic energy relaxation mechanism implemented during the growth of epitaxial SiC films on Si by means of the new method of substitution of atoms has been described. This method consists in substituting a part of carbon atoms for silicon matrix atoms with the formation of silicon carbide molecules. It has been found experimentally that the substitution for matrix atoms occurs gradually without destroying the crystalline structure of the matrix. The orientation of the film is determined by the “old” crystalline structure of the initial silicon matrix rather than by the silicon substrate surface only, as is the case where conventional methods are used for growing the films. The new growth method has been compared with the classical mechanisms of thin film growth. The structure and composition of the grown SiC layers have been described in detail. A new mechanism of first-order phase transformations in solids with a chemical reaction through an intermediate state promoting the formation of a new-phase nuclei has been discussed. The mechanism providing the occurrence of a wide class of heterogeneous chemical reactions between the gas phase and a solid has been elucidated using the example of the chemical interaction of the CO gas with the single-crystal Si matrix. It has been shown that this mechanism makes it possible to grow a new type of templates, i.e., substrates with buffer transition layers for growing wide-band-gap semiconductor films on silicon. A number of heteroepitaxial films of wide-band-gap semiconductors, such as SiC, AlN, GaN, and AlGaN on silicon, whose quality is sufficient for the fabrication of a wide class of micro- and optoelectronic devices, have been grown on the SiC/Si substrate grown by solid-phase epitaxy.

100 citations


Journal ArticleDOI
TL;DR: In this article, the authors proposed an alternative etching process based on thin film modification by light ions implantation followed by a selective removal of the modified layer with respect to the nonmodified material.
Abstract: Silicon nitride spacer etching realization is considered today as one of the most challenging of the etch process for the new devices realization. For this step, the atomic etch precision to stop on silicon or silicon germanium with a perfect anisotropy (no foot formation) is required. The situation is that none of the current plasma technologies can meet all these requirements. To overcome these issues and meet the highly complex requirements imposed by device fabrication processes, we recently proposed an alternative etching process to the current plasma etch chemistries. This process is based on thin film modification by light ions implantation followed by a selective removal of the modified layer with respect to the non-modified material. In this Letter, we demonstrate the benefit of this alternative etch method in term of film damage control (silicon germanium recess obtained is less than 6 A), anisotropy (no foot formation), and its compatibility with other integration steps like epitaxial. The etch mechanisms of this approach are also addressed.

66 citations


Journal ArticleDOI
TL;DR: In this article, the authors propose a solution to the long-standing problem of silicon nanocrystals being an indirect-gap material and consequently is an inefficient light emitter. But they also show that silicon can be transformed into a material with fundamental direct bandgap via a concerted action of quantum confinement and tensile strain, which can be used for the integration of optoelectronics on silicon wafers.
Abstract: Silicon, a semiconductor underpinning the vast majority of microelectronics, is an indirect-gap material and consequently is an inefficient light emitter. This hampers the ongoing worldwide effort towards the integration of optoelectronics on silicon wafers. Even though silicon nanocrystals are much better light emitters, they retain the indirect-gap nature. Here, we propose a solution to this long-standing problem: silicon nanocrystals can be transformed into a material with fundamental direct bandgap via a concerted action of quantum confinement and tensile strain. We document this transformation by DFT calculations mapping the E(k) band-structure of Si nanocrystals. The experimental proofs are then given firstly by a 10 000× increase in the photon emission rate of strained silicon nanocrystals together with their altered absorbance spectra, both of which point to direct dipole-allowed transitions, secondly by single nanocrystal spectroscopy, confirming reduced phonon energies and thus the presence of tensile strain, and lastly by photoluminescence studies under external hydrostatic pressure.

Journal ArticleDOI
TL;DR: In this paper, the authors used injection-level-dependent open-circuit voltage (Suns- Voc) measurements for the characterization and optimization of the doped amorphous silicon (a-Si:H) layers.
Abstract: Besides passivation of the c-Si absorber, provided mainly by the undoped buffer layer, the net doping of the silicon thin films plays a major role in the performance of silicon-based heterojunction (SHJ) solar cells. However, junction engineering is complex as high net doping often interferes with the interface passivation and the optical properties of the silicon thin films. We show that injection-level-dependent open-circuit voltage (Suns- Voc) measurements are a simple and valuable method for the characterization and optimization of the doped amorphous silicon (a-Si:H) layers. It is shown by experiment and device simulations that at high illumination intensities the Suns- Voc characteristic exhibits a strong signature of defect recombination within the a-Si:H, which is determined by the a-Si:H doping and the interfacial transparent conducting oxide (TCO) properties. This fact is exploited for a qualitative interpretation of the interplay between a-Si:H and the interfacial TCO properties. As a clear correlation between the Suns- Voc characteristic and the maximum power point conditions of the devices exists, fill factor (FF) losses attributed to the doped a-Si:H and the interfacial TCO properties can 1) be easily predicted in the early stage of device optimization on simple test structures, or 2) these FF losses can be identified and distinguished from other FF losses in the final device.

Journal ArticleDOI
TL;DR: The effective second-order optical susceptibility χxxy(2)¯ evolutions have been determined for 3 different waveguide widths 385 nm, 435 nm and 465 nm and it showed higher values for longer wavelengths and narrower waveguides and an explanation based on the strain distribution within the waveguide and its overlap with optical mode is given.
Abstract: We investigate the influence of the wavelength, within the 1.3μm–1.63μm range, on the second-order optical nonlinearity in silicon waveguides strained by a silicon nitride (Si3N4) overlayer. The effective second-order optical susceptibility χxxy(2)¯ evolutions have been determined for 3 different waveguide widths 385 nm, 435 nm and 465 nm and it showed higher values for longer wavelengths and narrower waveguides. For wWG = 385 nm and λ = 1630 nm, we demonstrated χxxy(2)¯ as high as 336 ± 30 pm/V. An explanation based on the strain distribution within the waveguide and its overlap with optical mode is then given to justify the obtained results.

Journal ArticleDOI
TL;DR: In this paper, an 18-μm crystalline silicon solar cell was integrated with a steel alloy substrate, achieving an efficiency of 16.8% with an opencircuit voltage of 632 mV and a short-circuit current density of 34.5 mA/cm
Abstract: Thin crystalline silicon solar cells have the potential to achieve high efficiency due to the potential for increased voltage. Thin silicon wafers are fragile; therefore, means of support must be provided. This paper reports the design, development, and analysis of an 18-μm crystalline silicon solar cell electrically integrated with a steel alloy substrate. This ultrathin silicon is epitaxially grown on porous silicon and then transferred onto the steel substrate. This method allows the independent processing of each surface. The steel substrate enables robust handling and provides a conductive back plane. Three groups of cells with planar and textured structures are compared; significant improvements in J sc , V oc , and fill factor (FF) are achieved. The best cell shows an efficiency of 16.8% with an open-circuit voltage of 632 mV and a short-circuit current density of 34.5 mA/cm 2 .

Journal ArticleDOI
TL;DR: In this article, a 20nm-thick protective layer was constructed between the amorphous silicon and the atomic layer of a sputtered transparent electrode that acts as a barrier, impeding hole and electron collection.
Abstract: We examine damage-free transparent-electrode deposition to fabricate high-efficiency amorphous silicon/crystalline silicon heterojunction solar cells. Such solar cells usually feature sputtered transparent electrodes, the deposition of which may damage the layers underneath. Using atomic layer deposition, we insert thin protective films between the amorphous silicon layers and sputtered contacts and investigate their effect on device operation. We find that a 20-nm-thick protective layer suffices to preserve, unchanged, the amorphous silicon layers beneath. Insertion of such protective atomic-layer-deposited layers yields slightly higher internal voltages at low carrier injection levels. However, we identify the presence of a silicon oxide layer, formed during processing, between the amorphous silicon and the atomic-layer-deposited transparent electrode that acts as a barrier, impeding hole and electron collection.

Book
08 Dec 2014
TL;DR: In this paper, the authors describe different techniques for growing single-crystalline silicon wafers. But the main focus of this paper is the analysis of the properties of the wafer and its properties.
Abstract: Preface About the Author Introduction Silicon: The Semiconductor Why Single Crystals Revolution in Integrated Circuit Fabrication Technology and the Art of Device Miniaturization Use of Silicon as a Semiconductor Silicon Devices for Boolean Applications Integration of Silicon Devices and the Art of Circuit Miniaturization MOS and CMOS Devices for Digital Applications LSI, VLSI, and ULSI Circuits and Applications Silicon for MEMS Applications Summary References Silicon: The Key Material for Integrated Circuit Fabrication Technology Introduction Preparation of Raw Silicon Material Metallurgical-Grade Silicon Purification of Metallurgical-Grade Silicon Ultra-High Pure Silicon for Electronics Application Polycrystalline Silicon Feed for Crystal Growth Summary References Importance of Single Crystals for Integrated Circuit Fabrication Introduction Crystal Structures Different Crystal Structures in Nature Cubic Structures Diamond Crystal Structure Silicon Crystal Structure Silicon Crystals and Atomic Packing Factors Crystal Order and Perfection Crystal Orientations and Planes Influence of Dopants and Impurities in Silicon Crystals Summary References Different Techniques for Growing Single-Crystal Silicon Introduction Bridgman Crystal Growth Technique Czochralski Crystal Growth/Pulling Technique Crucible Choice for Molten Silicon Chamber Temperature Profile Seed Selection for Crystal Pulling Environmental and Ambient Control in the Crystal Chamber Crystal Pull Rate and Seed/Crucible Rotation Dopant Addition for Growing Doped Crystals Methods for Continuous Czochralski Crystal Growth Impurity Segregation between Liquid and Grown Silicon Crystals Crystal Growth Striations Use of a Magnetic Field in the Czochralski Growth Technique Large-Area Silicon Crystals for VLSI and ULSI Applications Post-Growth Thermal Gradient and Crystal Cooling after Pull-Out Float-Zone Crystal Growth Technique Seed Selection Environment and Chamber Ambient Control Heating Mechanisms and RF Coil Shape Crystal Growth Rate and Seed Rotation Dopant Distribution in Growing Crystals Impurity Segregation between Liquid and Grown Silicon Crystals Use of Magnetic Field for Float-Zone Growth Large Area Silicon Crystals and Limitations of Shape and Size Thermal Gradient and Post-Growth Crystal Cooling Zone Refining of Single-Crystal Silicon Other Silicon Crystalline Structures and Growth Techniques Silicon Ribbons Silicon Sheets Silicon Whiskers and Fibers Silicon in Circular and Spherical Shapes Silicon Hollow Tubes Casting of Polycrystalline Silicon for Photovoltaic Applications Summary References From Silicon Ingots to Silicon Wafers Introduction Radial Resistivity Measurements Boule Formation, Identification of Crystal Orientation, and Flats Ingot Slicing Mechanical Lapping of Wafer Slices Edge Profiling of Slices Chemical Etching and Mechanical Damage Removal Chemimechanical Polishing for Planar Wafers Surface Roughness and Overall Wafer Topography Megasonic Cleaning Final Cleaning and Inspection Summary References Evaluation of Silicon Wafers Introduction Acoustic Laser Probing Technique Atomic-Force Microscope Studies on Surfaces Auger Electron Spectroscopic Studies Chemical Staining and Etching Techniques Contactless Characterization Deep-Level Transient Spectroscopy Defect Decoration by Metals Electron Beam and High-Energy Electron Diffraction Studies Flame Emission Spectrometry Four-Point Probe Technique for Resistivity Measurement and Mapping Fourier Transform Infrared Spectroscopy Measurements for Impurity Identification Gas Fusion Analysis Hall Mobility Mass Spectra Analysis Minority Carrier Diffusion Length/Lifetime/Surface Photovoltage Optical Methods for Impurity Evaluation Photoluminescence Method for Determining Impurity Concentrations Gamma-Ray Diffractometry Scanning Electron Microscopy for Defect Analysis Scanning Optical Microscope Secondary Ion Mass Spectrometer for Impurity Distribution Spreading Resistance and Two-Point Probe Measurement Technique Stress Measurements Transmission Electron Microscopy van der Pauw Resistivity Measurement Technique for Irregular-Shaped Wafers X-Ray Technique for Crystal Perfection and Dislocation Density Summary References Resistivity and Impurity Concentration Mapping of Silicon Wafers Introduction Electrically Active and Inactive Impurities Surface Mapping and Concentration Contours Surface Roughness Mapping on a Complete Wafer Summary References Impurities in Silicon Wafers Effect of Intentional and Unintentional Impurities and Their Influence on Silicon Devices Intentional Dopant Impurities in Silicon Wafers Aluminum Antimony Arsenic Boron Gallium Phosphorus Unintentional Dopant Impurities in Silicon Wafers Carbon Chromium Copper Germanium Gold Helium Hydrogen Iron Nickel Nitrogen Oxygen Tin Other Metallic Impurities Summary References Defects in Silicon Wafers Introduction Impact of Defects in Silicon Devices and Structures Point Defects and Vacancies Line Defects Bulk Defects and Voids Dislocations and Screw Dislocations Swirl Defects Stacking Faults Precipitations Surface Pits/Crystal-Originated Particles Grown Vacancies and Defects Thermal Donors Slips, Cracks, and Shape Irregularities Stress, Bowing, and Warpage Summary References Silicon Wafer Preparation for VLSI and ULSI Processing Introduction Purity of Chemicals Used for Silicon Processing Degreasing of Silicon Wafers Removal of Metallic and Other Impurities Gettering of Metallic Impurities Denuding of Silicon Wafers Neutron Irradiation Argon Annealing of Wafers Hydrogen Annealing of Wafers Final Cleaning, Rinsing, and Wafer Drying Summary References Packing of Silicon Wafers Packing of Fully Processed Blank Silicon Wafers Storage of Wafers and Control of Particulate Contamination Storage of Wafers and Control of Particulate Contamination with Process-Bound Wafers Summary References Index

Journal ArticleDOI
TL;DR: In this article, the use of intrinsic silicon oxide as a buffer layer at the p-i interface of thin-film silicon solar cells is shown to provide significant advantages, including an improvement in carrier collection in the blue region of the spectrum.

Journal ArticleDOI
TL;DR: In this paper, a supersaturation of nitrogen atoms is found in the surface layer of microstructured silicon after femtosecond (fs) laser irradiation in NF3, which makes the nitrogen-hyperdoped silicon exhibit good thermal stability of optical properties.
Abstract: A supersaturation of nitrogen atoms is found in the surface layer of microstructured silicon after femtosecond (fs) laser irradiation in NF3. The average nitrogen concentration in the uppermost 50 nm is about 0.5 ± 0.2 at. %, several orders of magnitude higher than the solid solubility of nitrogen atoms in silicon. The nitrogen-hyperdoped silicon shows high crystallinity in the doped layer, which is due to the repairing effect of nitrogen on defects in silicon lattices. Nitrogen atoms and vacancies can be combined into thermal stable complexes after fs laser irradiation, which makes the nitrogen-hyperdoped silicon exhibit good thermal stability of optical properties.

Journal ArticleDOI
TL;DR: Through the incorporation of finite element simulations encompassing the theoretical distribution of strain, the applied bias field, and the optical modes supported by the waveguide geometry, two phenomenological scaling coefficients are extracted which relate the induced optical nonlinearities to the local strain gradient.
Abstract: We theoretically consider the existence of multiple nonzero components of the second-order nonlinear susceptibility tensor, χ(2), generated via strain-induced symmetry breaking in crystalline silicon. We determine that, in addition to the previously reported χxxy(2) component, the χyyy(2) component also becomes nonzero based on the remaining symmetry present in the strained material. In order to characterize these two nonlinearities, we fabricate Fabry–Perot waveguide resonators on 250 nm thick silicon-on-insulator wafers clad with 180 nm of compressively stressed (−1.275 GPa) silicon nitride. We measure the shifts in these devices’ modal effective indices in response to several bias electric fields and calculate the χeff,xxy(2) and χeff,yyy(2) nonlinear susceptibility tensor elements induced by the breaking of the guiding material’s inversion symmetry. Through the incorporation of finite element simulations encompassing the theoretical distribution of strain, the applied bias field, and the optical modes supported by the waveguide geometry, we extract two phenomenological scaling coefficients which relate the induced optical nonlinearities to the local strain gradient.

Book ChapterDOI
TL;DR: Silicon heterojunction solar cells are crystalline silicon-based devices in which thin amorphous silicon layers deposited on the wafer surfaces serve as passivated, carrier-selective contacts as mentioned in this paper.
Abstract: Silicon heterojunction solar cells are crystalline silicon-based devices in which thin amorphous silicon layers deposited on the wafer surfaces serve as passivated, carrier-selective contacts. The success of this technology is attributable to the ability of amorphous silicon to passivate dangling bonds—thereby removing surface recombination sites—without blocking charge carrier transport. This unique combination allows the recombination-active metal contacts to be displaced from the wafer surfaces, enabling record-high open-circuit voltages of up to 750 mV and efficiencies of up to 25.6%. This chapter introduces the silicon heterojunction concept and discusses device fabrication, operation, and manufacturing. Active areas of research and likely future developments are identified throughout.

Journal ArticleDOI
21 Nov 2014-ACS Nano
TL;DR: X-ray reflectivity measurements of increasingly more complex interfaces involving silicon (001) substrates reveal the existence of a thin low-density layer intruding between the single-crystalline silicon and the amorphous native SiO2 terminating it, and the importance of accounting for this layer in modeling silicon/liquid interfaces and silicon-supported monolayers is demonstrated.
Abstract: X-ray reflectivity measurements of increasingly more complex interfaces involving silicon (001) substrates reveal the existence of a thin low-density layer intruding between the single-crystalline silicon and the amorphous native SiO2 terminating it. The importance of accounting for this layer in modeling silicon/liquid interfaces and silicon-supported monolayers is demonstrated by comparing fits of the measured reflectivity curves by models including and excluding this layer. The inclusion of this layer, with 6–8 missing electrons per silicon unit cell area, consistent with one missing oxygen atom whose bonds remain hydrogen passivated, is found to be particularly important for an accurate and high-resolution determination of the surface normal density profile from reflectivities spanning extended momentum transfer ranges, now measurable at modern third-generation synchrotron sources.

Journal ArticleDOI
TL;DR: A novel methodology for characterizing electron transport in III-V multigate nanowire field effect transistors (NWFETs) is reported and it is shown that by implementing parallel arrays of nanowires, it is possible to enhance the signal-to-noise ratio of the measurement, enabling more reliable measurement of Hall voltage (carrier concentration) and, hence, mobility.
Abstract: The III-V semiconductors such as In x Ga 1-x As (x = 0.53-0.70) have attracted significant interest in the context of low power digital complementary metal-oxide-semiconductor (CMOS) technology due to their superior transport properties. However, top-down patterning of III-V semiconductor thin films into strongly confined quasi-one-dimensional (1D) nanowire geometries can potentially degrade the transport properties. To date, few reports exist regarding transport measurement in multigate nanowire structures. In this work, we report a novel methodology for characterizing electron transport in III-V multigate nanowire field effect transistors (NWFETs). We demonstrate multigate NWFETs integrated with probe electrodes in Hall Bridge geometry to enable four-point measurements of both longitudinal and transverse resistance. This allows for the first time accurate extraction of Hall mobility and its dependence on carrier concentration in III-V NWFETs. Furthermore, it is shown that by implementing parallel arrays of nanowires, it is possible to enhance the signal-to-noise ratio of the measurement, enabling more reliable measurement of Hall voltage (carrier concentration) and, hence, mobility. We characterize the mobility for various nanowire widths down to 40 nm and observe a monotonic reduction in mobility compared to planar devices. Despite this reduction, III-V NWFET mobility is shown to outperform state-of-the-art strained silicon NWFETs. Finally, we demonstrate evidence of room -temperature ballistic transport, a desirable property in the context of short channel transistors, in strongly confined III-V nanowire junctions using magneto-transport measurements in a nanoscale Hall-cross structure.

Journal Article
TL;DR: In this paper, the structural features most strongly associated with hole traps in hydrogenated nanocrystalline silicon with very low crystalline volume fraction were identified and a mechanism by which deep hole traps associated with bridge bonds may contribute to the Staebler-Wronski effect was proposed.
Abstract: Genetic programming is used to identify the structural features most strongly associated with hole traps in hydrogenated nanocrystalline silicon with very low crystalline volume fraction. The genetic programming algorithm reveals that hole traps are most strongly associated with local structures within the amorphous region in which a single hydrogen atom is bound to two silicon atoms (bridge bonds), near fivefold coordinated silicon (floating bonds), or where there is a particularly dense cluster of many silicon atoms. Based on these results, we propose a mechanism by which deep hole traps associated with bridge bonds may contribute to the Staebler-Wronski effect.

Journal ArticleDOI
TL;DR: In this article, the electrical and optical properties of p-type hydrogenated amorphous silicon carbide (a-SiC:H) are compared with p-Type H-Si:H emitter material of silicon heterojunction solar cells.
Abstract: In this paper, the electrical and optical properties of p-type hydrogenated amorphous silicon carbide (a-SiC:H) are compared with p-type hydrogenated amorphous silicon (a-Si:H) widely used as emitter material of silicon heterojunction solar cells. The difference in solar-cell performance of the two emitters shows that p-type a-SiC:H emitter is able to enhance the short-circuit current density (J sc ) by reducing the parasitic absorption loss and reflection loss without degrading the electrical performance of devices. The application of the p-type a-SiC:H emitter can lead to a J sc increase of about 1 mA/cm 2 , compared with the p-type a-Si:H emitter. Our silicon heterojunction solar cell with p-type a-SiC:H emitter shows an active-area efficiency of 20.8% and the short-circuit current density of 40.3 mA/cm 2 .

Journal ArticleDOI
TL;DR: In this paper, an organic crystal cladding of N-benzyl-2-methyl-4-nitroaniline (BNA) was applied to silicon-on-insulator (SOI) waveguides, which have a CMOS-like metal stack on top.
Abstract: Silicon waveguides can be functionalized with an organic χ(2)-nonlinear cladding. This complements silicon photonics with the electro-optic (EO) effect originating from the cladding and enables functionalities such as pure phase modulation, parametric amplification, or THz-wave generation. Claddings based on a polymer matrix containing chromophores have been introduced, and their strong χ(2) nonlinearity has already been used to demonstrate ultralow power consuming modulators. However, these silicon-organic hybrid (SOH) devices inherit not only the advantageous properties; these polymer claddings require an alignment procedure called poling and must be operated well below their glass transition temperature. This excludes some applications. In contrast, claddings made from organic crystals come with a different set of properties. In particular, there is no need for poling. This new class of claddings also promises stronger resilience to high temperatures, better long-term stability, and photo-chemical stability. We report on the deposition of an organic crystal cladding of N-benzyl-2-methyl-4-nitroaniline (BNA) on silicon-on-insulator (SOI) waveguides, which have a CMOS-like metal stack on top. Adhering to such an architecture, which preserves the principal advantage of using CMOS-based silicon photonic fabrication processes, permits the first demonstration of high-speed modulation at 12.5 Gbit/s in this material class, which proves the availability of the EO effect from BNA on SOI also for other applications.

Patent
Qing Liu1, Hong He1, Bruce B. Doris1
31 Dec 2014
TL;DR: In this paper, a SiGe-on-insulator FinFET employs a silicon nitride liner to prevent de-stabilizing oxidation at the base of the SiGe fin.
Abstract: A structurally stable SiGe-on-insulator FinFET employs a silicon nitride liner to prevent de-stabilizing oxidation at the base of a SiGe fin. The silicon nitride liner blocks access of oxygen to the lower corners of the fin to facilitate fabrication of a high-concentration SiGe fin. The silicon nitride liner is effective as an oxide barrier even if its thickness is less than about 5 nm. Use of the SiN liner provides structural stability for fins that have higher germanium content, in the range of 25-55% germanium concentration.

Proceedings ArticleDOI
30 Oct 2014
TL;DR: In this article, a non-destructive method to introduce impurity atoms into silicon (Si) and germanium (Ge) using Molecular Layer Doping (MLD) is described.
Abstract: This work describes a non-destructive method to introduce impurity atoms into silicon (Si) and germanium (Ge) using Molecular Layer Doping (MLD). Molecules containing dopant atoms (arsenic) were designed, synthesized and chemically bound in self-limiting monolayers to the semiconductor surface. Subsequent annealing enabled diffusion of the dopant atom into the substrate. Material characterization included assessment of surface analysis (AFM) and impurity and carrier concentrations (ECV). Record carrier concentration levels of arsenic (As) in Si (∼5×1020 atoms/cm3) by diffusion doping have been achieved, and to the best of our knowledge this work is the first demonstration of doping Ge by MLD. Furthermore due to the ever increasing surface to bulk ratio of future devices (FinFets, MugFETs, nanowire-FETS) surface packing spacing requirements of MLD dopant molecules is becoming more relaxed. It is estimated that a molecular spacing of 2 nm and 3 nm is required to achieve doping concentration of 1020 atoms/cm3 in a 5 nm wide fin and 5 nm diameter nanowire respectively. From a molecular perspective this is readily achievable.

Journal ArticleDOI
TL;DR: In this article, the authors investigated the crystallization process of silicon quantum dots (QDs) imbedded in hydrogenated amorphous Si-rich silicon carbide (a-SiC:H) films.

Journal ArticleDOI
TL;DR: In this article, a review of the characteristics of both strain techniques, global and local, is presented, with special emphasis on performance of NMOS biaxial strain and PMOS uniXial strain.
Abstract: Semiconductor industry is currently facing with the fact that conventional submicron CMOS technology is approaching the end of their capabilities, at least when it comes to scaling the dimensions of the components. Therefore, much attention is paid to device technology that use new technological structures and new channel materials. Modern technological processes, which mainly include ultra high vacuum chemical vapor deposition, molecular beam epitaxy and metal-organic molecular vapor deposition, enable the obtaining of ultrathin, crystallographically almost perfect, strained layers of high purity. In this review paper we analyze the role that such layers have in modern CMOS technologies. It’s given an overview of the characteristics of both strain techniques, global and local, with special emphasis on performance of NMOS biaxial strain and PMOS uniaxial strain. Due to the improved transport properties of strained layers, especially high mobility of charge carriers, the emphasis is on mechanisms to increase the charge mobility of strained silicon and germanium, in light of recent developments in CMOS technology.

Patent
19 May 2014
TL;DR: In this paper, the authors used channeled implants into silicon carbide crystals to form a semiconductor structure and annealing the crystallographic axis at a time-temperature product of less than about 30,000° C.-hours to activate the implanted ions.
Abstract: Methods of forming a semiconductor structure include the use of channeled implants into silicon carbide crystals. Some methods include providing a silicon carbide layer having a crystallographic axis, heating the silicon carbide layer to a temperature of about 300° C. or more, implanting dopant ions into the heated silicon carbide layer at an implant angle between a direction of implantation and the crystallographic axis of less than about 2°, and annealing the silicon carbide layer at a time-temperature product of less than about 30,000° C.-hours to activate the implanted ions.