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Showing papers on "Strained silicon published in 2019"


Journal ArticleDOI
TL;DR: In this paper, the authors demonstrate group IV quantum dot arrays in silicon metal-oxide-semiconductor (SiMOS), strained silicon (Si/SiGe) and strained germanium (Ge/GeGe).
Abstract: Electrons and holes confined in quantum dots define an excellent building block for quantum emergence, simulation, and computation. In order for quantum electronics to become practical, large numbers of quantum dots will be required, necessitating the fabrication of scaled structures such as linear and 2D arrays. Group IV semiconductors contain stable isotopes with zero nuclear spin and can thereby serve as excellent host for spins with long quantum coherence. Here we demonstrate group IV quantum dot arrays in silicon metal-oxide-semiconductor (SiMOS), strained silicon (Si/SiGe) and strained germanium (Ge/SiGe). We fabricate using a multi-layer technique to achieve tightly confined quantum dots and compare integration processes. While SiMOS can benefit from a larger temperature budget and Ge/SiGe can make ohmic contact to metals, the overlapping gate structure to define the quantum dots can be based on a nearly identical integration. We realize charge sensing in each platform, for the first time in Ge/SiGe, and demonstrate fully functional linear and two-dimensional arrays where all quantum dots can be depleted to the last charge state. In Si/SiGe, we tune a quintuple quantum dot using the N+1 method to simultaneously reach the few electron regime for each quantum dot. We compare capacitive cross talk and find it to be the smallest in SiMOS, relevant for the tuning of quantum dot arrays. These results constitute an excellent base for quantum computation with quantum dots and provide opportunities for each platform to be integrated with standard semiconductor manufacturing.

78 citations


Journal ArticleDOI
TL;DR: It is reported that the piezoresistance coefficient of SiC NW is 17 times that of its bulk counterparts, which provides new insights to develop high performance SiC devices, to help avoid catastrophic failure when working in harsh environments.
Abstract: Reports reveal that the piezoresistance coefficients of silicon carbide (SiC) nanowires (NWs) are 2 to 4 times smaller than those of their corresponding bulk counterparts. It is a challenge to eliminate contamination in adhering NWs onto substrates. In this study, a new setup was developed, in which NWs were manipulated and fixed by a goat hair and conductive silver epoxy in air, respectively, in the absence of any depositions. The goat hair was not consumed during manipulation of the NWs. The process took advantage of the stiffness and tapered tip of the goat hair, which is unlike the loss issue of beam sources in depositions. With the new fixing method, in situ transmission electron microscopy (TEM) electromechanical coupling measurements were performed on pristine SiC NWs. The piezoresistance coefficient and carrier mobility of SiC NW are -94.78 × 10-11 Pa-1 and 30.05 cm2 V-1 s-1, respectively, which are 82 and 527 times respectively greater than those of SiC NWs reported previously. We, for the first time, report that the piezoresistance coefficient of SiC NW is 17 times those of its bulk counterparts. These findings provide new insights to develop high performance SiC devices and to help avoid catastrophic failure when working in harsh environments.

57 citations


Journal ArticleDOI
TL;DR: In this article, the origin of second harmonic generation (SHG) in a silicon waveguide strained by a silicon nitride cladding is investigated in detail, and an effective second-order nonlinear susceptibility of ~0.5
Abstract: Strained silicon waveguides have been proposed to break the silicon centrosymmetry, which inhibits second-order nonlinearities. Even if electro-optic effect and second harmonic generation (SHG) were measured, the published results presented plenty of ambiguities due to the concurrence of different effects affecting the process. In this work, the origin of SHG in a silicon waveguide strained by a silicon nitride cladding is investigated in detail. From the measured SHG efficiencies, an effective second-order nonlinear susceptibility of ~0.5 pmV−1 is extracted. To evidence the role of strain, SHG is studied under an external mechanical load, demonstrating no significant dependence on the applied stress. On the contrary, a 254 nm ultraviolet (UV) exposure of the strained silicon waveguide suppresses completely the SHG signal. Since UV irradiation is known to passivate charged defects accumulated in the silicon nitride cladding, this measurement evidences the crucial role of charged centers. In fact, charged defects cause an electric field in the waveguide that via the third order silicon nonlinearity induces the SHG. This conclusion is supported by numerical simulations, which accurately model the experimental results.

35 citations


Journal ArticleDOI
TL;DR: In this paper, the performance of a strained silicon channel in silicon nanotube FET (Si-NTFET) device was analyzed and three-dimensional simulations of the structure were carried out using ATLAS TCAD simulator and the model is calibrated with respect to previously published experimental data.
Abstract: In this paper, we have presented an analysis on the performance of a strained silicon channel in silicon nanotube FET (Si-NTFET) device. Si-NTFET devices have tube-shaped channel region and because of this conduction in the channel can be controlled in two ways from outside the tube and from inside (from hollow side) the tube which results in better control over the short channel effects (SCEs). Bi-axial strain induced into the device by the inclusion of silicon-–germanium layer in between the channel. Three-dimensional simulations of the structure are carried out using ATLAS TCAD simulator and the model is calibrated with respect to previously published experimental data. The transfer characteristics, drain induced barrier lowering (DIBL), threshold voltage, I on and I off , subthreshold swing of the Si-NTFET and strained Si-NTFET devices are investigated. It is seen that in strained Si-NTFET, the drive capability and inversion charge density is much higher compared to that of Si-NTFET. Evaluation of electrical performances confirms that the DIBL and other SCEs are either reduced or remains the same. However, the use of strained Si-NTFET is more suited for high speed and low power applications.

30 citations


Journal ArticleDOI
TL;DR: In this article, the authors demonstrate an effective epitaxial route for the manipulation and enrichment of the intriguing spin-dependent phenomena boasted by germanium and report on spin quantum beats between Zeeman-split levels under an external magnetic field.
Abstract: We demonstrate an effective epitaxial route for the manipulation and further enrichment of the intriguing spin-dependent phenomena boasted by germanium. We show optical initialization and readout of spins in Ge-rich germanium-tin alloys and report on spin quantum beats between Zeeman-split levels under an external magnetic field. While heavy Sn atoms can be readily utilized to strengthen the spin-orbit coupling, our experiments reveal robust spin orientation in a wide temperature range and a persistent spin lifetime that noticeably approaches the nanosecond regime at room temperature. In addition, time decay photoluminescence experiments evidence a temperature-induced monotonic decrease of the carrier lifetime, eventually providing crucial insights also into nonradiative recombination mechanisms.

26 citations


Journal ArticleDOI
TL;DR: In this paper, the authors used the equilibrium molecular dynamics approach for the evaluation of thermal conductivity considering different interatomic potentials, including Tersoff, Environment-Dependent Interatomic Potential, and Modified Embedded Atom Method potentials.
Abstract: In this work, we investigated the tensile and compression forces effect on the thermal conductivity of silicon. We used the equilibrium molecular dynamics approach for the evaluation of thermal conductivity considering different interatomic potentials. More specifically, we tested Stillinger-Weber, Tersoff, Environment-Dependent Interatomic Potential, and Modified Embedded Atom Method potentials for the description of silicon atom motion under different strain and temperature conditions. It was shown that the Tersoff potential gives a correct trend of the thermal conductivity with the hydrostatic strain, while other potentials fail, especially when the compression strain is applied. Additionally, we extracted phonon density of states and dispersion curves from molecular dynamics simulations. These data were used for direct calculations of the thermal conductivity considering the kinetic theory approach. Comparison of molecular dynamics and kinetic theory simulations results as a function of strain and temperature allowed us to investigate the different factors affecting the thermal conductivity of the strained silicon.

18 citations


Journal ArticleDOI
TL;DR: In this paper, the authors investigated the effect of bending the strings diagonally or perpendicularly with respect to the silicon frame and found that increasing the clamp width for diagonal strings slightly increases the fundamental out-of-plane mode at small radii, while perpendicular strings only deteriorate with increasing clamp width.
Abstract: Nanomechanical resonators based on strained silicon nitride (Si$_3$N$_4$) have received a large amount of attention in fields such as sensing and quantum optomechanics due to their exceptionally high quality factors ($Q$s). Room-temperature $Q$s approaching 1 billion are now in reach by means of phononic crystals (soft-clamping) and strain engineering. Despite great progress in enhancing $Q$s, difficulties in fabrication of soft-clamped samples limits their implementation into actual devices. An alternative means of achieving ultra-high $Q$s was shown using trampoline resonators with engineered clamps, which serves to localize the stress to the center of the resonator, while minimizing stress at the clamping. The effectiveness of this approach has since come into question from recent studies employing string resonators with clamp-tapering. Here, we investigate this idea using nanomechanical string resonators with engineered clampings similar to those presented for trampolines. Importantly, the effect of orienting the strings diagonally or perpendicularly with respect to the silicon frame is investigated. It is found that increasing the clamp width for diagonal strings slightly increases the $Q$s of the fundamental out-of-plane mode at small radii, while perpendicular strings only deteriorate with increasing clamp width. Measured $Q$s agree well with finite element method simulations even for higher-order resonances. The small increase cannot account for previously reported $Q$s of trampoline resonators. Instead, we propose the effect to be intrinsic and related to surface and radiation losses.

15 citations


Journal ArticleDOI
24 May 2019
TL;DR: In this paper, the authors presented a theoretical model to describe the combined characteristics of strained silicon nanoscale double-gate MOSFET along with high k dielectric layer.
Abstract: This study presents a theoretical model to describe the combined characteristics of strained silicon nanoscale double gate MOSFET along with high k dielectric layer. Although a well- tempered MOSFET with strong gate electrostatics can be devised using high k gate material, lower conduction band offset (CBO) over silicon results in leakage and subsequent static power dissipation. The study shows that this effect can reduce the Ion/Ioff ratio to 2 × 102 with 2 nm thick TiO2 dielectric layer (k = 60) along with mobility degradation. Incorporating the effects of strained silicon and high k dielectrics in MOSFETs exhibits bandstructure alteration and increase in CBO. This inhibits carrier tunnelling causing leakage with restoration of Ion/Ioff ratio to 4.5 × 106. The mobility can also be improved along with the maintenance of effective gate electrostatics. Thus the study illustrates the possibility of designing the nanoscale MOS devices with all the essential characteristics without trade-off over other performance parameters.

14 citations


Journal ArticleDOI
TL;DR: The demonstrated p-type SiGe quantum well infrared photodetectors (QWIPs) on a strained-silicon-on-insulator (sSOI) substrate allows strain-balancing between the QWIP heterostructure with an average composition of Si0.7Ge0.3 and the substrate, and therefore lifts restrictions to the active material thickness faced by SiGe growth on silicon or silicon-on -insulator substrates.
Abstract: We demonstrate p-type SiGe quantum well infrared photodetectors (QWIPs) on a strained-silicon-on-insulator (sSOI) substrate. The sSOI system allows strain-balancing between the QWIP heterostructure with an average composition of Si0.7Ge0.3 and the substrate, and therefore lifts restrictions to the active material thickness faced by SiGe growth on silicon or silicon-on-insulator substrates. The realized sSOI QWIPs feature a responsivity peak at detection wavelengths around 6 µm, based on a transition between heavy-hole states. The fabricated devices have been thoroughly characterized and compared to equivalent material simultaneously grown on virtual Si0.7Ge0.3 substrates based on graded SiGe buffers. Responsivities of up to 3.6 mA/W are achieved by the sSOI QWIPs at 77 K, demonstrating the large potential of sSOI-based devices as components for a group-IV optoelectronic platform in the mid-infrared spectral region.

11 citations


Dissertation
19 Oct 2019
TL;DR: In this article, a novel Fano cavity resonator enabled by sub-wavelength engineering is proposed, which achieves a high extinction ratio (23 dB) with a small Q factor of only 5600, and characterized by an ultra-low power consumption of less than 5 fj/bit when relying on the free carrier plasma dispersion effect.
Abstract: Second-order Pockels and the third-order Kerr effects are among the important effects exploited for light modulation and light generation in integrated photonic platforms. To take advantage of these nonlinearities in silicon photonics, especially due to the lack of second order effect in bulk Si, the use of subwavelength optical structures is explored. In this context, this thesis work has focused on two main aspects, including: 1) Exploration of a novel photonic cavity scheme to take benefit of the electro-optical Pockels effect in strained Si structures for the realization of ultra-fast lower-consumption compact silicon modulators; 2) Exploration of a new family of waveguides leading to an automatic satisfaction of energy/momentum conservation for the purpose of Kerr frequency comb generation in integrated photonic platforms. For improving the performances of integrated silicon resonant optical modulators, we have developed a novel Fano cavity resonator enabled by sub-wavelength engineering, leading simultaneously to high extinction ratio (23 dB) with a small Q factor of only 5600, and characterized by an ultra-low power consumption of less than 5 fj/bit when relying on the free carrier plasma dispersion effect. We have further extended the method to design a strained silicon Fano modulation structure which performances traditionally suffer from the weak amplitude of the exploited strain-induced Pockels effect and from considerable microwave losses due to large footprint components. By means of the proposed ultra-compact subwavelength structured Fano resonator, around 200-fold/60-fold (Q factor of 32000/5600) improvement on the modulation extinction ratio with the same driven voltage was theoretically predicted. For improving the exploitation of silicon Kerr nonlinearities, we have proposed a novel family of graded index optical waveguides intending to automatically fulfill the energy and momentum conservation laws of four-wave mixing processes. The design of the waveguide section is based on a principle inherited from quantum wells of wave mechanics and concepts inherited from subwavelength structures for the practical realization of the rather particular index profiles. Standing on these specific waveguides in term of light dispersion, we have applied them to the modeling of frequency micro-combs (e.g. frequency combs generated using micro-ring resonators and a CW light source) by solving the nonlinear relevant equations (Lugiato-Lefever) to dynamically analyze the soliton comb spectrum generation process in various configurations. On top of this model, the specifically automatically phase-matched sub-wavelength-enabled graded-index waveguides were considered to trim and extend the bandwidth of silicon soliton frequency combs, demonstrating enlarged bandwidth and improved spectrum design flexibility with respect to previous works. Overall, one of the dominant features of our study was to contribute to showing that sub-long wavelength photonic structures could provide concrete solutions to problems useful for the realization of on-chip non-linear functions. Subwavelength/nano structures not only benefit to passive photonic circuits which have been intensively developed in the past ten years, but also show strong potentials in the realization of active functions. This subwavelength toolbox is decisive in practice for the concrete achievement of the objectives pursued.

10 citations


Journal ArticleDOI
TL;DR: In this article, the effect of germanium doping on the performance of an optical PN phase shifter in silicon photonics platform is analyzed using a 2D process simulation tool.

Journal ArticleDOI
TL;DR: In this article, the authors used first-principles electronic structure methods to calculate the electronic thermoelectric properties (i.e., due to electronic transport only) of singlecrystalline bulk n-type silicon-germanium alloys vs Ge composition, temperature, doping concentration, and strain.
Abstract: We use first-principles electronic structure methods to calculate the electronic thermoelectric properties (i.e., due to electronic transport only) of single-crystalline bulk n-type silicon-germanium alloys vs Ge composition, temperature, doping concentration, and strain. We find excellent agreement to available experiments for the resistivity, mobility, and Seebeck coefficient. These results are combined with the experimental lattice thermal conductivity to calculate the thermoelectric figure of merit Z T, finding very good agreement with experiments. We predict that 3% tensile hydrostatic strain enhances the n-type Z T by 50% at carrier concentrations of n = 10 20 cm − 3 and a temperature of T = 1200 K. These enhancements occur at different alloy compositions due to different effects: at 50% Ge composition, the enhancements are achieved by a strain induced decrease in the Lorenz number, while the power factor remains unchanged. These characteristics are important for highly doped and high temperature materials, in which up to 50% of the heat is carried by electrons. At 70% Ge, the increase in Z T is due to a large increase in the electrical conductivity produced by populating the high mobility Γ conduction band valley, lowered in energy by strain.

Journal ArticleDOI
TL;DR: In this article, the authors used first-principles electronic structure methods to calculate the electronic thermoelectric properties (i.e. due to electronic transport only) of single-crystalline bulk silicon-germanium alloys vs Ge composition, temperature, doping concentration and strain.
Abstract: We use first-principles electronic structure methods to calculate the electronic thermoelectric properties (i.e. due to electronic transport only) of single-crystalline bulk $n$-type silicon-germanium alloys vs Ge composition, temperature, doping concentration and strain. We find excellent agreement to available experiments for the resistivity, mobility and Seebeck coefficient. These results are combined with the experimental lattice thermal conductivity to calculate the thermoelectric figure of merit $ZT$, finding very good agreement with experiment. We predict that 3% tensile hydrostatic strain enhances the $n$-type $ZT$ by 50% at carrier concentrations of $n=10^{20}$ cm$^{-3}$ and temperature of $T=1200K$. These enhancements occur at different alloy compositions due to different effects: at 50% Ge composition the enhancements are achieved by a strain induced decrease in the Lorenz number, while the power factor remains unchanged. These characteristics are important for highly doped and high temperature materials, in which up to 50% of the heat is carried by electrons. At 70% Ge the increase in $ZT$ is due to a large increase in electrical conductivity produced by populating the high mobility $\Gamma$ conduction band valley, lowered in energy by strain.

Journal ArticleDOI
TL;DR: The use of a p-i-n junction and an asymmetric cladding is proposed to eliminate the unwanted carrier influence and improve the electro-optical modulation response.
Abstract: The magnitude and origin of the electro-optic measurements in strained silicon devices has been lately the object of a great controversy. Furthermore, recent works underline the importance of the masking effect of free carriers in strained waveguides and the low interaction between the mode and the highly strained areas. In the present work, the use of a p-i-n junction and an asymmetric cladding is proposed to eliminate the unwanted carrier influence and improve the electro-optical modulation response. The proposed configuration enhances the effective refractive index due to the strain-induced Pockels effect in more than two orders of magnitude with respect to the usual configuration.

Journal ArticleDOI
TL;DR: In this paper, a simulation study of SSOI technology, where the strain profiles of "fins" with different dimensions and layer thicknesses are analyzed, is presented, for the first time, that a buried oxide (BOX) as thin as 10-15 nm is able to effectively memorize the strain.
Abstract: Strained silicon-on-insulator (SSOI) is a promising platform for 5G, which will require both high-performance and low-power complementary metal–oxide–semiconductor (CMOS) devices. Hence, it is important to understand the behavior of strain in SSOI at deeply scaled dimensions. We thus present a simulation study of SSOI technology, where the strain profiles of “fins” with different dimensions and layer thicknesses are analyzed. We discover, for the first time, that a buried oxide (BOX) as thin as 10–15 nm is able to effectively memorize the strain. It is also able to retain the strain under annealing up to 1000 °C, a result verified by the Raman measurements. Such a thin BOX enables a good back-gate control for dynamic threshold voltage ( ${V}_{\text{t}}$ ) tuning of SSOI transistors. The ability to have a good performance enhancement (from strain), and dynamic ${V}_{\text{t}}$ tunability (from thin BOX) makes SSOI favorable for 5G mixed-signal applications.

Journal ArticleDOI
TL;DR: In this paper, the authors investigated tensile and compression forces effect on the thermal conductivity of silicon and used an equilibrium molecular dynamics approach for the evaluation of thermal conductivities considering different interatomic potentials.
Abstract: In this work, we investigated tensile and compression forces effect on the thermal conductivity of silicon. We used equilibrium molecular dynamics approach for the evaluation of thermal conductivity considering different interatomic potentials. More specifically, we tested Stillinger-Weber, Tersoff, Environment-Dependent Interatomic Potential and Modified Embedded Atom Method potentials for the description of silicon atom motion under different strain and temperature conditions. Additionally, we extracted phonon density of states and dispersion curves from molecular dynamics simulations. These data were used for direct calculations of thermal conductivity considering the kinetic theory approach. Comparison of molecular dynamics and kinetic theory simulations results as a function of strain and temperature allowed us to investigate the different factors affecting the thermal conductivity of strained silicon.

Book ChapterDOI
01 Jan 2019
TL;DR: In this article, the scaling trend brings issues about power consumption, transistor density and off-leakage current, together with carrier mobility degradation, and the continuous scaling-down of device dimensions and further performance enhancement are facing more and more severe challenges.
Abstract: With transistor dimension shrinking into nanoscale regime as described in the previous chapter, conventional gate oxide thickness has been scaled near the thickness limit of 1 nm. This scaling trend brings issues about power consumption, transistor density and off-leakage current, together with carrier mobility degradation. Furthermore, the continuous scaling-down of device dimensions and further performance enhancement are facing more and more severe challenges.

Dissertation
22 Mar 2019
TL;DR: In this article, second order optical nonlinearities in silicon waveguides are studied and it is shown that this nonlinearity does not originate on the applied strain, but on the presence of trapped charges that induce a static electric field inside the waveguide.
Abstract: In this thesis, second order optical nonlinearities in silicon waveguides are studied. At the beginning, the strained silicon platform is investigated in detail. In recent years, second order nonlinearities have been demonstrated on this platform. However, the origin of these nonlinearities was not clear. This thesis offers a clear answer to this question, demonstrating that this nonlinearity does not originate on the applied strain, but on the presence of trapped charges that induce a static electric field inside the waveguide. Based on this outcome, a way to induce larger electric fields in silicon waveguide is studied. Using lateral p-n junctions, strong electric fields are introduced in the waveguides, demonstrating both electro-optic effects and second-harmonic generation. These results, together with a detailed modeling of the system, pave the way through the demonstration of spontaneous parametric down-conversion in silicon.

Journal ArticleDOI
TL;DR: In this paper, the effect of heating and cooling in the range of 25-900°C on the lattice deformations of diamond wire-sawn polycrystalline and scratched monocrystalline silicon surfaces was studied in detail using Raman microscopy.
Abstract: The effect of heating and cooling in the range of 25–900 °C on the lattice deformations of diamond wire-sawn polycrystalline and scratched monocrystalline silicon surfaces was studied in detail using Raman microscopy. Mechanically treated silicon surfaces contain tensile or compressive strained silicon with varying deformation strength and areas with high-pressure silicon phases and amorphous silicon. It is shown that compressive deformed silicon relaxes after heating the sample to 600 °C, while tensile deformed silicon only relaxes after multiple heating and cooling cycles. Raman measurements during the heating and after the cooling phases reveal the individual thermal expansion and relaxation behavior of the deformed silicon states. Compressive deformed silicon relaxes during the heating phase, while tensile deformed silicon relaxes during the cooling phase. It is, therefore, possible to separately relax certain deformation states using thermal annealing without changing the topography of the surface.The effect of heating and cooling in the range of 25–900 °C on the lattice deformations of diamond wire-sawn polycrystalline and scratched monocrystalline silicon surfaces was studied in detail using Raman microscopy. Mechanically treated silicon surfaces contain tensile or compressive strained silicon with varying deformation strength and areas with high-pressure silicon phases and amorphous silicon. It is shown that compressive deformed silicon relaxes after heating the sample to 600 °C, while tensile deformed silicon only relaxes after multiple heating and cooling cycles. Raman measurements during the heating and after the cooling phases reveal the individual thermal expansion and relaxation behavior of the deformed silicon states. Compressive deformed silicon relaxes during the heating phase, while tensile deformed silicon relaxes during the cooling phase. It is, therefore, possible to separately relax certain deformation states using thermal annealing without changing the topography of the surface.

Journal ArticleDOI
TL;DR: In this paper, the performance of strained Si on insulator as potential material for forced stacked multi-threshold FinFET based inverter considering its ultra low power applications has been investigated.
Abstract: This work investigates the performance of strained Si on insulator as potential material for forced stacked multi-threshold FinFET based inverter considering its ultra low-power applications. Using the calibrated exhaustive 3D-TCAD mixed-mode simulation a comparative analysis of conventional and forced stack FinFET based inverters has been performed. The static and dynamic characteristics have been compared with conventional and forced stacked FinFET based inverter. The leakage in standby mode can be reduced through well-defined stack and multi-threshold (VTH) transistors. Channel doping is optimized to get higher VTH devices. To improve the speed of circuits FinFETs are designed on strained Silicon on Insulator (sSOI) wafer. Uniform uniaxial tensile stress in sSOI gives the advantage of high ON current in n-FinFETs. It is observed that using strained FinFETs the maximum delay is reduced below 10 ps and using multi VTH forced stack technique the leakage power is reduced. Hence, forced stack technique based FinFET can evolve as a potential candidate for the future ultra-low power device applications.

Journal ArticleDOI
TL;DR: In this article, a waveguide microstructures based on strained silicon with the use of silicon carbonitride and silicon nitride films as cladding layers are created, which allows obtaining high values of intrinsic mechanical stresses in films (about 700 MPa).
Abstract: Waveguide microstructures based on strained silicon with the use of silicon carbonitride and silicon nitride films as cladding layers are created. A plasma-enhanced chemical vapor deposition technique is developed, which allows obtaining high values of intrinsic mechanical stresses in films (about 700 MPa). The strained waveguide structures are characterized by micro-Raman spectroscopy during a scanning procedure. It is demonstrated that deposition of silicon carbonitride and silicon nitride films induces compressive stresses in the silicon waveguide, which is proved by the shift of the maximum of the main peak of scattering on LO-phonons of silicon toward higher wave numbers. The compressive stresses in the silicon waveguide clad with silicon nitride and carbonitride layers are estimated as 350 and 250 MPa, respectively, which is sufficient for the emergence of nonlinear optical properties of silicon (Pockels effect).

Journal ArticleDOI
TL;DR: The results of the experimental observation of stimulated terahertz emission under optical intracenter excitation of uniaxially strained bismuth-doped silicon are presented in this article.
Abstract: The results of the experimental observation of stimulated terahertz emission under optical intracenter excitation of uniaxially strained bismuth-doped silicon are presented. Pumping in the presented experiment is performed using a FELIX free-electron laser. It is shown that uniaxial strain of the silicon crystal leads to a significant change in the stimulated emission spectrum of the impurity.

Patent
23 May 2019
TL;DR: In this article, a gate is formed on a substrate and a hard mask layer is created on the spacer, and an annealing process is performed to repair damages to the epitaxial layer caused by the ion implantation process.
Abstract: A method for fabricating a semiconductor device. A gate is formed on a substrate. A spacer is formed on each sidewall of the gate. A hard mask layer is formed on the spacer. A recessed region is formed in the substrate and adjacent to the hard mask layer. An epitaxial layer is formed in the recessed region. The substrate is subjected to an ion implantation process to bombard particle defects on the hard mask layer with inert gas ions. An annealing process is performed to repair damages to the epitaxial layer caused by the ion implantation process. The hard mask layer is then removed.

Patent
20 Aug 2019
TL;DR: In this article, a three-dimensional flash memory and a channel process with low on-state current and uniformity problem was solved by using the strained silicon technology, the channel carrier mobility was effectively improved, and the Coulomb interaction caused by channel doping was compensated.
Abstract: The invention belongs to the field of semiconductor memories and particularly discloses strained silicon channels applied to a three-dimensional flash memory and a preparation method thereof. The strained silicon channels applied to the three-dimensional flash memory are formed by Si atoms and Ge atoms. The strained silicon channels are set on flash memory strings for forming the three-dimensionalflash memory, any of the flash memory strings is a three-dimensional stacked structure and is vertically set on a substrate. According to the invention, by improving the specific components of the channel material and the corresponding deposition process, the problem that a three-dimensional flash memory and a channel process thereof has low on-state current and driving and device uniformity problem faced by the increase of the number of stacked layers in the prior art can be solved, the preparation of a vertical channel is carried out by using the strained silicon technology, the channel carrier mobility can be effectively improved, and the Coulomb interaction caused by channel doping is compensated.

Patent
02 May 2019
TL;DR: In this article, a strain inducing intermediate layer (SIIL) is used to strain the silicon layer of a CMOS transistor, which can be used to form different complementary metal oxide semiconductor transistors with improved characteristics.
Abstract: A semiconductor device includes a porous silicon layer on a silicon substrate. A strain inducing intermediate layer (SIIL) is on the porous silicon layer. A silicon layer is on the SIIL. Lattice constant of the silicon layer is different from lattice constant of the SIIL. Thus, the silicon layer is strained. By employing different strain inducing materials in the SIIL, the silicon layer can be used to form different complementary metal oxide semiconductor (CMOS) transistors with improved characteristics.


Proceedings ArticleDOI
01 Aug 2019
TL;DR: In this paper, the effective oxide thickness of the device using gate stacked insulator was determined using the variable oxide thickness (VARIOT) technique, where the thickness of each layer which consists of SiO 2 and high-k material will vary accordingly.
Abstract: This paper demonstrates an optimisation approach for strained Silicon Surrounding Gate MOSFET. The main contribution of this work is to determine the effective oxide thickness of the device using gate stacked insulator. Gate stack configuration plays a significant role in alleviating the leakage current and minimises the short channel effects. The thickness of the insulator layer is determined using the variable oxide thickness(VARIOT) technique. Using this method, the thickness of each layer which consists of SiO 2 and high-k material will vary accordingly. In order to enable the transport properties of a short channel device, two models are invoked in TCAD simulators, namely Bohr Quantum Potential and velocity saturation model. Three types of high-k dielectrics were used such as Si 3 N 4 , HfO 2 and AL 2 O 3 to determine the most advantages configuration on its device performance. It found that the gate stack with SiO 2 /Si 3 N 4 configuration contributed the most improvement when it's lowering the leakage current and threshold voltage appreciably. The on-state current, threshold voltage and off-state current estimated about 1.2e-4, 0.17 V and 1e-8 accordingly. Moreover, the value of subthreshold swing (SS) and Drain Induced Barrier Lowering of the device approximately as 50 and 15, respectively, which is beyond the ideal case of conventional MOSFET.

Proceedings ArticleDOI
01 Feb 2019
TL;DR: In this article, a double gate nano-FET with the concept of heterostructure on insulator (HOI) and strain engineering infused in the channel region was developed, which provided better control over the leakage current on introduction of the second gate in bottom side of substrate.
Abstract: A Double Gate (DG) Nano-FET is developed here with the concept of heterostructure on insulator (HOI) and strain engineering infused in the channel region. The device developed provided better control over the leakage current on introduction of the second gate in bottom side of substrate leading to nominal carrier mobility due to the strained SiGe layer sandwiched between two layers of Strained Silicon (s-Si) for both the gates. The DG nano structure is developed on 45 nm technology and provided ∼63% enrichment in leakage in comparison to the 40 nm tri-layered HOI MOSFET, but lattice mismatch scattering degraded the devices performance. Thus, with a predominantly smooth characteristic curve less leakage current is observed for the DG Nano-FET device.