Strained silicon

About: Strained silicon is a research topic. Over the lifetime, 6076 publications have been published within this topic receiving 138975 citations.

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.

Theoretical aspects of the luminescence of porous silicon.

Abstract: The luminescence in the visible range of porous silicon is analyzed in the hypothesis of quantum confinement. We calculate the electronic and optical properties of silicon crystallites and wires with sizes between 0 and 4.5 nm. The band-gap energies of such confined systems are in agreement with the photon energies observed in luminescence. We calculate the radiative recombination times of the confined excitons. We conclude that experimental nonradiative processes in porous silicon are more efficient than calculated radiative ones at T=300 K. The high photoluminescence efficiency of porous silicon is due to the small probability of finding a nonradiative recombination center in silicon nanocrystallites. Recently, it has been proposed that the low-temperature dependence of the experimental radiative decay time of the luminescence of porous silicon could be explained by the exchange splitting in the fundamental exciton. We show that the influence of the valley-orbit splitting cannot be excluded. The sharp optical-absorption edge above 3.0 eV is not proof of the molecular origin of the properties of porous silicon because silicon nanostructures present a similar absorption spectrum. We calculate the nonradiative capture of electrons or holes on silicon dangling bonds and show that it is very dependent on the confinement. We find that the presence of one dangling bond at the surface of a crystallite in porous silicon must destroy its luminescent properties above 1.1 eV but can produce a luminescence below 1.1 eV due to a radiative capture on the dangling bond.

A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors

Abstract: This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions Dramatic performance enhancement relative to unstrained devices are reported These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 12nm physical gate oxide and Ni salicide World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/) and 800/spl mu/A//spl mu/m (low V/sub T/) at 12V are demonstrated NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region High NMOS drive currents of 126mA//spl mu/m (high VT) and 145mA//spl mu/m (low VT) at 12V are reported The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families

A 90-nm logic technology featuring strained-silicon

Abstract: A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/ CDO for high-performance dense logic is presented. Strained silicon is used to increase saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10% and 25%, respectively. Using selective epitaxial Si/sub 1-x/Ge/sub x/ in the source and drain regions, longitudinal uniaxial compressive stress is introduced into the p-type MOSEFT to increase hole mobility by >50%. A tensile silicon nitride-capping layer is used to introduce tensile strain into the n-type MOSFET and enhance electron mobility by 20%. Unlike all past strained-Si work, the hole mobility enhancement in this paper is present at large vertical electric fields in nanoscale transistors making this strain technique useful for advanced logic technologies. Furthermore, using piezoresistance coefficients it is shown that significantly less strain (/spl sim/5 /spl times/) is needed for a given PMOS mobility enhancement when applied via longitudinal uniaxial compression versus in-plane biaxial tension using the conventional Si/sub 1-x/Ge/sub x/ substrate approach.

Characteristics of the Surface‐State Charge (Qss) of Thermally Oxidized Silicon

Abstract: The nature of the surface-state charge (Qss) associated with thermally oxidized silicon has been studied experimentally using MOS structures. The effects of oxidation conditions, silicon orientation, annealing treatments, oxide thickness, and electric field were examined, as well as the physical location of the surface-state charge. The results indicate that the surface-state charge can be reproducibly controlled over a range 1010-1012 cm -2, and that it is an intrinsic property of the silicon dioxide-silicon system. It appears to be due to an excess silicon species introduced into the oxide layer near the silicon during the oxidation process.