Strained silicon

About: Strained silicon is a research topic. Over the lifetime, 6076 publications have been published within this topic receiving 138975 citations.

A logic nanotechnology featuring strained-silicon

Abstract: Strained-silicon (Si) is incorporated into a leading edge 90-nm logic technology . Strained-Si increases saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10 and 25%, respectively. The process flow consists of selective epitaxial Si/sub 1-x/Ge/sub x/ in the source/drain regions to create longitudinal uniaxial compressive strain in the p-type MOSFET. A tensile Si nitride-capping layer is used to introduce tensile uniaxial strain into the n-type MOSFET and enhance electron mobility. Unlike past strained-Si work: 1) the amount of strain for the n-type and p-type MOSFET can be controlled independently on the same wafer and 2) the hole mobility enhancement in this letter is present at large vertical electric fields, thus, making this flow useful for nanoscale transistors in advanced logic technologies.

A 14nm logic technology featuring 2 nd -generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size

Abstract: A 14nm logic technology using 2nd-generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described. The transistors feature rectangular fins with 8nm fin width and 42nm fin height, 4th generation high-k metal gate, and 6th-generation strained silicon, resulting in the highest drive currents yet reported for 14nm technology. This technology is in high-volume manufacturing.

Overview and status of metal S/D Schottky-barrier MOSFET technology

Abstract: In this paper, the metal source/drain (S/D) Schottky-barrier (SB) MOSFET technology is reviewed. The technology offers several benefits that enable scaling to sub-30-nm gate lengths including extremely low parasitic S/D resistance (1% of the total device resistance), atomically abrupt junctions that enable the physical scaling of the device to sub-10-nm gate lengths, superior control of OFF-state leakage current due to the intrinsic Schottky potential barrier, and elimination of parasitic bipolar action. These and other benefits accrue using a low-thermal-budget CMOS manufacturing process requiring two fewer masks than conventional bulk CMOS. The SB-CMOS manufacturing process enables integration of critical new materials such as high-k gate insulators and strained silicon substrates. SB MOSFET technology state of the art is also reviewed, and shown to be focused on barrier-height-lowering techniques that use interfacial layers between the metal S/Ds and the channel region. SB-PMOS devices tend to have superior performance compared to NMOS, but NMOS performance has recently improved by using ytterbium silicide or by using hybrid structures that incorporate interfacial layers to lower the SB height.

Stress‐related problems in silicon technology

Abstract: The silicon integrated‐circuits chip is built by contiguously embedding, butting, and overlaying structural elements of a large variety of materials of different elastic and thermal properties. Stress develops in the thermal cycling of the chip. Furthermore, many structural elements such as CVD (chemical vapor deposition) silicon nitride, silicon dioxide, polycrystalline silicon, etc., by virtue of their formation processes, exhibit intrinsic stresses. Large localized stresses are induced in the silicon substrate near the edges and corners of such structural elements. Oxidation of nonplanar silicon surfaces produces another kind of stress that can be very damaging, especially at low oxidation temperatures. Mismatch of atomic sizes between dopants and the silicon, and heteroepitaxy produce another class of strain that can lead to the formation of misfit dislocations. Here we review the achievements to date in understanding and modeling these diverse stress problems.

Luminescence of silicon materials : chains, sheets, nanocrystals, nanowires, microcrystals, and porous silicon

Abstract: Both nanocrystal silicon and porous silicon thin films show efficient visible luminescence at room temperature, thus suggesting the possibility of introducing some form of optically active, silicon-based material into integrated circuit processing. In this context, I discuss and analyze the responsible electronic quantum size effects and excited-state photophysics. In a broader context I discuss silicon optical and electronic properties as a function of dimensionality and surface chemistry. As one progresses from trans-polysilane (1D-Si) through puckered sheet polysilyne (2D-Si) to diamond lattice silicon (3D-Si), there is a systematic progression from direct to indirect gap behavior