Showing papers on "Stuck-at fault published in 1971"

A Random and an Algorithmic Technique for Fault Detection Test Generation for Sequential Circuits

Abstract: Two procedures are presented for generating fault detection test sequences for large sequential circuits. In the adaptive random procedure one can achieve a tradeoff between test generation time, length, and percent of circuit tested. An algorithmic path-sensitizing procedure is also presented. Both procedures employ a three-valued logic system. Some experimental results are given.

A Nand Model ror Fault Diagnosis in Combinational Logic Networks

Abstract: A network model colled the normal NAND model is introduced for the study of fault diagnosis in combinational logic circuits. It is shown that every network can be transformed into an equivalent normal NAND network from which all the information pertaining to the diagnosis of the original network con be obtained. The use of this model greatly simplifies fault analysis and test generation.

On the Design of Multiple Fault Diagnosable Networks

Abstract: This paper considers the design of diagnosable combinational networks. The diagnosability criterion used here requires that the single fault detection test set for the network also detects all multiple faults. Several recent studies in the area of multiple fault diagnosis are reviewed and the results which are pertinent to this investigation are summarized. It is shown that, under certain conditions, internal fan-out may be present without adversely affecting the detection of multiple faults. These results suggest design techniques which lead to readily diagnosable networks.

Fault Tolerant Sequential Machines

Abstract: A machine representation of permanent memory faults is introduced where, if M is a sequential machine representing some fault free system, a memory fault is represented by a function μ on the states of M, and the result of the fault by an appropriately determined machine Mμ. Given this representation, the investigation is primarily concerned with faults that are tolerated (masked) in the sense that resulting behavior relates in some specified way to original behavior. Several types of fault masking are thus considered and conditions for their existence investigated. The restriction to a special class of stable faults is also studied, this class being of interest since it includes all faults which correspond to "stuck-at" failures in the memory cells of a sequential switching network.

Failure activity determination technique in fault simulation

Abstract: The failure activity determination technique of the present application represents a new approach to fault simulation designed to significantly reduce the time required to perform such simulations. This new technique may be used in conjunction with any interpretive fault simulation program (i.e., any program using list structures to trace and calculate circuit activity in a logic design). The improved technique consists essentially of using previously calculated good machine values during the fault simulation for any logic blocks that are not effected by the failure(s) being simulated. Thus, new values must be calculated for only a subset of the total logic circuitry. This subset, or failure partition, of the logic is determined dynamically during the fault simulation through the use of a series of flags within the circuit list structure.

Ground fault detection system with sequential line testing

Abstract: An a-c line, isolated from ground by a transformer, is continuously tested for ground faults through a switching network which sequentially completes a circuit between the a-c conductors, an apparent active power source, and a ground fault detection network. A fault condition detection network is coupled through a bridge circuit to the a-c lines, to provide an indication of a simple fault on either line, or a substantially unbalanced fault on both lines. An oscillator and ring counter arrangement continuously drives a switching network to test for individual line grounds, and balanced and unbalanced double line faults. A self-contained power supply arrangement is provided.

Fault locating system for electrical circuits

Abstract: A fault locating system for electrical circuits consisting of three major components, a fault sensor, a control circuit or channel, and an indicating device. The fault sensors indicate an abnormal current flow when a fault occurs and transmit the information through the control circuit or channel to the indicating device which in turn displays the information. The control circuit connects the fault sensors in series or parallel, and the sensors are oriented in spaced relationship along the cable or electrical circuit being monitored so that fault detection between adjacent sensors is determined by the indicating device. The system may be set up for automatic resetting. The preferred sensor is a magnetic reed switch, and the fault indicator preferably incorporates a circuit with fast response.

On the Design of Minimum Length Fault Tests for Combinational Circuits

Abstract: Techniques for deriving the minimum length tests are developed for irredundant combinational circuits that contain single faults The development is based on the Boolean difference function The Boolean difference function is expanded to form two analytical expressions that can be used to calculate the tests for any stuck-at-zero and stuck-at-one fault within combinational circuits

Means for dual level ground fault protection of a.c. circuits

Abstract: Circuitry for detection of ground fault currents in alternating current circuits utilizable with grounded or ungrounded systems and for protectively interrupting the circuits, comprises means for deriving monitoring signals from representative of the fault currents and applying the signals to first and second relays. The first relay is responsive at a low level of fault current to pass control current from a source of control power to warning such as a lamp and horn. The second relay is responsive at a higher level of fault current to pass control current to an interrupter device for the circuits being monitored. Adjustment means in the circuitry sets the two threshold levels of fault current at which the relays respectively respond. Seal-in circuit means keep the first relay actuated to activate the alarms continuously after their operation is initiated. A time delay network prevents relay response to instantaneous transient currents exceeding the lower threshold. The circuitry is unitized for use at any standard voltage, current and frequency and to isolate all current carrying components. The circuits being monitored can serve as a source of control power or an independent source can be provided.

First fault annunciator system

Abstract: Fault occurrence displaying system, for use with machinery, which automatically signals and initially displays only a firstoccurring of perhaps several machine faults which occasion machine shut-down. The system includes means for automatically signaling and displaying both system failure and proper system functioning as well as means automatically operative to hold a fault signal on until manually turned off and means to hold successive fault signals inoperative until the first-occurring fault signal is silenced (i.e., turned off).

Determination of Fault Surge Waveshapes with Particular Reference to Fault Detection

Abstract: This paper describes the analytical procedure of determining the attenuation and distortion of fault-generated surges on transmission lines when the skin effects of conductor and earth are taken into account. Herein, the term which considers the skin effect of the earth has been modified. After comparing the results with known approaches, a method, for selecting the circuit parameters of the detection circuit which is used to couple the fault signal from the transmission line to the fault-locating equipment, is given.

An algorithm for generating a fault detection test for a class of sequential circuits

Abstract: In this paper we consider the problem of generating a fault detection sequence for sequential circuits. We employ a three valued logic system which allows us to handle race and hazard conditions. The main result of this paper is an algorithm for constructing a minimal length input sequence X such that g o (Y o , X ) ≠ g i (Y i , X ), where g o (g i ) is the output of the circuit containing no fault (fault i), starting in state Y o (Y i ), when input sequence X is applied. Both synchronous and asynchronous circuits are considered. Asynchronous circuits are mapped into “equivalent” combinational switching functions by introducing new input and output variables associated with the present and next state of the element. The solution to the sequential circuit test generation problem is shown to require the ability to generate a test to detect a multiple fault in a combinational circuit.

Detection of failures in combinational digital circuits

Abstract: The paper is concerned with the problem of determining, by terminal experiments, whether a given combinational switching circuit operates correctly or whether it is impaired by some malfunction. We shall be primarily concerned with permanent faults due to component failures. It is assumed that other procedures will be employed to protect the circuit against the effects of transient faults. A method is presented for the detection of failures in combinational switching circuits. The method provides minimal sets of tests for 2-level circuits and nearly minimal sets of tests for multilevel circuits.

On theDesignofMinimumLengthFaultTests forCombinational Circuits

Abstract: forderiving theminimumlength testsare developedforirredundant combinational circuits thatcontain single faults. Thedevelopment isbasedon theBoolean difference function. TheBoolean difference function isexpanded toformtwoanalytical expressions that can beusedtocalculate thetestsforany stuck-at-zero andstuck-at-one fault within combinational circuits. A map methodisthendeveloped directly fromtheseanalytical expressions. The minimumtestforthecomplete circuit can thenbe taken directly fromthemap. IndexTerms-Error correction, fault detection, fault diagnosis.