Showing papers on "Stuck-at fault published in 1974"

Bridging and Stuck-At Faults

Abstract: The commonly used stuck-at fault fails to model logic circuit shorts. Bridging faults are defined to model these circuit mal-functions. This model is based on wired logic which is a characteristic of many logic families such as resistor-transistor logic (RTL), diode transistor logic (DTL), emitter-coupled logic (ECL), etc. It does not apply to TTL circuits. The model also limits to fan-out-free leads.

Fault tree synthesis for chemical processes

Abstract: This paper outlines the concepts for a systematic approach to the safety analysis of chemical processing systems. A procedure for automatically generating fault trees is presented. The fault trees describe nearly all the failure modes for the system under analysis. The fault tree generation procedure uses information on (1) the description of the system (detailed flowsheet), (2) physical and chemical properties of materials in and around the system, and (3) unit models which describe the behavior of the units within the system and which are assembled to describe the behavior of the complete system. The unit models are connected to form an information flow structure for the complete processing system. Unit failure models are also defined for common chemical units. By systematically defining hazard states and searching the information flow structure for the system, it is possible to generate fault trees for the complete process. An analysis of the fault trees can reveal the important failure modes for the process.

The Effects of Races, Delays, and Delay Faults on Test Generation

Abstract: Test sequences constructed by most test generation procedures often create time dependent results when applied to a circuit. These dependencies often invalidate the test. The main cause for this situation is that the test generation procedures and circuit models employed do not take into account many aspects of delay associated with a circuit. In this paper we present modeling techniques to be used by conventional test generation procedures to alleviate some of these problems. These models include the cases of equal, unequal and ambiguous delay values. Both inertial and transport delays are considered. Both static and dynamic output behavior is studied, though we restrict inputs to fundamental mode operation. Finally, a new type of fault, caUed a delay fault, is introduced, and a model developed so that a test to detect this class of fault can be generated via conventional test generation techniques. In summary, this paper attempts to outline procedures and identify problem areas so that test generation is more of a science rather than a hit and miss process, and so that the correctness of results need not always be verified via simulation or physical fault injection.

Minimal Fault Tests for Combinational Networks

Abstract: The problem of how to determine minimal sets of tests for single and multiple faults in irredundant combinational circuits is dealt with It is shown that the "Equivalent Sum of Products" form of the given network contains all the information necessary to derive a min; mal test set A simple procedure which generates a minimal test set Ts for single faults is described Fault masking is then studied and it is shown how to find the multiple faults undetected by Ts Finally a method which derives a nearly minimal multiple fault test set Tm where Ts [mi][/mi] Tm is given

Fault-Tolerant Asynchronous Sequential Machines

Abstract: A general design technique for achieving single fault-tolerant asynchronous sequential circuits is described. The design procedures apply over a large range of fault conditions and are extremely easy to use. Generally, less than three times the logic required for a single copy is needed to achieve single fault tolerance. In addition to fault tolerance, real time fault detection is easily achieved and it is immediately known when single fault tolerant capability is exceeded.

Timing analysis for digital fault simulation using assignable delays

Abstract: The techniques to be described in this paper are generally applicable to any time domain, parallel fault, digital logic simulation system. The particular implementation was done on the CC-TEGAS3 system and quoted results are from this system.The first technique to be considered provides accuracy of fault simulation when using assignable nominal delays for different element types. The second technique provides for handling fault induced activity in a network, in such a way as to considerably reduce the amount of simulation time required.

Ground fault and neutral fault detection circuit

Abstract: A circuit is disclosed for detecting ground faults and neutral faults and for providing power interruption in response thereto. The circuit monitors the current flow in the line and neutral conductors and provides a signal to a power interruption circuit in the event that a ground fault or a neutral fault condition is detected. In addition, a signal having a certain frequency is generated and coupled on the neutral line to enhance the probability of detecting neutral faults.

Ground fault protective systems with variable rate integration of fault signals

Abstract: To minimize nuisance tripping for spurious causes in ground fault protective systems, fault-characterizing signals derived from differential currents in alternating current supply lines are subjected to a variable integration automatically adapted to the magnitude of the fault-characterizing signal. Higher level signals are integrated at augmented rates, preferably with an antilog characteristic. The supply circuit is interrupted when the expanded and integrated signal exceeds a threshold value.

Multiple-Fault Detection and Location in Fan-Out Free Combinational Circuits

Abstract: Two algorithms are presented for the detection and location of single or multiple stuck faults in a fan-out free combinational circuit. The algorithms are based on a canonic representation of the indistinguishability classes of faults. The number of tests required in these algorithms are shown to be a linear function of the number of gates in the circuit.

Design Technique of Fail-Safe Sequential Circuits Using Flip-Flops For Internal Memory

Abstract: A method for the realization of fail-safe sequential circuits is presented where flip-flops are employed for representing the internal states. First, such a design technique where the circuit will be trapped in an erroneous state into which it is transferred by a fault is shown. Further, the condition for assuring that the circuit will be dropped into the particular (predetermined) final state when a fault exists is described. Finally, some extensions of the technique are attempted.

A Fail-Safe Asynchronous Sequential Machine

Abstract: This paper examines the dynamic fault behavior of asynchronous sequential machines, specifically identifying the faults which cause critical races and hazards, and presents a state assignment technique leading to a machine that enters one of a small set of error states whenever a fault occurs. Entry into an error state can be checked by very simple check circuits; a self-testing check circuit and one requiring only two tests for fault detection are discussed. An extension of the state assignment technique to produce a machine that is fail-safe is also presented. The fail-safe design has the property that once a fault has caused the machine to malfunction and enter an error state, the machine never leaves the error state and therefore does not produce erroneous outputs. This machine detects all but a small class of multiple faults.

A minicomputer-based logic circuit fault simulator

Abstract: A logic circuit simulator implemented on a mini-computer with 16K core handles 1000 zero- and unit-delay gates. Single "stuck-at-0", "stuck-at-1", and "short-circuit" faults are simulated in parallel seven at a time using a table-driven selective-trace fault-injection algorithm. For a typical 100-gate circuit the simulation rate for the fault-free circuit or for a group of seven faults is about 800 input patterns per minute, and a complete fault simulation run takes about 5 minutes and costs $1.This paper, aimed at simulator program-designers rather than users, describes technical details of the implementation including minicomputer considerations, the data structure, coding three-valued-logic for efficient parallel simulation, the selective-trace algorithm, the recognition and resolution of critical races in flip-flops, the recognition and resolution of circuit oscillations, implicit fault collapsing, and short-circuit fault simulation.

A quality measure for LSI components

Abstract: Large-scale integration components are subjected to testing based on stuck fault modeling. Stuck fault testing often does not provide patterns for all possible stuck conditions that can exist in a circuit. Because of the incompleteness of test coverage, a new quality measure is needed-one that is not based on sample inspection. Such an LSI quality measure is described in this paper. The LSI quality measure can be related to component yield and is based on the stuck fault testing coverage, the physical circuit design layout, and the rate of faults occurring on elemental circuit geometries. The concept of the LSI quality measure is illustrated in this paper by an example. Starting from a block diagram and an assumed stuck fault coverage, some stuck faults are assumed to remain untested. For these untested faults, the elemental circuit geometries in a corresponding FET circuit layout are determined, and the quality measure calculated. Common sense rules are offered for optimizing the quality and lowering its cost impact on higher levels of assembly.

A system of computer programs for efficient test generation for combinational switching circuits

Abstract: Modules of computer programs for test generation, fault simulation and test minimization for combinational switching circuits have been written. They form a system of computer programs in which a special strategy directs the choice of a test set. The object is to minimize the number of tests which is required for the detection of logical faults in combinational switching circuits.

An Examination of Algebraic Test Generation Methods for Multiple Faults

Abstract: A generalized test function (GTF) is derived that gives all tests for a multiple stuck-at fault in a combinational logic circuit. The GTF is then used as the basis for an examination of several algebraic test generation methods that have appeared in the literature. Deficiencies are found in some methods.

Comments on "Cause-Effect Analysis for Multiple Fault Detection in Combinational Networks"

Abstract: Bosson and Hong1 have developed an effective procedure for multiple fault detection. However, their claim that their procedure gives near-minimal results is not necessarily the case.

Comments on "Multiple Fault Detection in Combinational Networks"

Abstract: Some comments on a recent contribution on multiple fault detection using test sets for single fault detection are presented. A counter example that shows some defects in generalizing from a tree to an arbitrary network are also included.

Extension of Boolean differentiation to define a test for a specific logic fault in a combinational logic network

Abstract: The letter demonstrates an extension of Boolean difference to obtain a test for a specific fault. The extension is compared with Roth's D calculus, and it is shown that the two concepts are complementary. A procedure for determining the total fault-detection capability of each test is indicated.