Showing papers on "Stuck-at fault published in 1978"

Efficient Algorithms for Testing Semiconductor Random-Access Memories

Abstract: A fault model which views faults in semiconductor random-access memories at a functional level instead of at a basic gate level is presented. An efficient 0(n) algorithm to detect all faults in the fault model is described. The fault model is then extended to incorporate more complex faults. An 0(n · log2 n) algorithm is presented for one such extended fault model.

Universal Test Sets for Multiple Fault Detection in AND-EXOR Arrays

Abstract: The fault-detection problem in AND-EXOR arrays is formulated in a new framework. The arrays considered are more general compared to those by the previous researchers. Designs of fault-detecting test sets to detect all multiple faults in these networks are presented. The designs are independent of the function realized and hence can be generated easily.

Deductive Fault Simulation with Functional Blocks

Abstract: This paper presents a method of propagating the effects of faults through functional blocks using the deductive (fault list) technique. An extension of the method is shown to be effective for simulating internal faults in functional blocks. The techniques presented here have been used for implementing the functional simulation capability in the Logic Analysis for Maintenance Planning (LAMP) System at Bell Laboratories.

Automatic system level test generation and fault location for large digital systems

Abstract: A system for automatic test generation and fault location, FLT-700, is described in this paper. It can treat large digital systems with 100K blocks (logic gates) or more. This is realized by utilizing Scan-Path concept, automatic partitioning and test generation techniques and automatic fault location technique. Serviceability for large computer systems can, therefore, be improved and easy maintenance realized. can treat sequential circuits as combinational circuits. Flip-flops in logic cards are serially connected with Scan-Path as shown in Fig.l(b). Therefore these flip-flops can operate as a shift register. Gates for selecting logic cards are also incorporated in each card. Therefore, the specified card in a logic unit with many logic cards can be selected by X-Y address signals (Fig.l(c)). Then, test data can be scanned into the card and operational results be scanned out of it.

Complex logical fault detection apparatus and method

Abstract: The present invention relates to apparatus and method for testing logic circuit boards for complex logical faults contained therein. A known good identical logic circuit is stimulated by a preselected sequence of binary test patterns and the number of transitions in logical state before achieving a final logical state as well as the final logical state for a number of points within the circuit are monitored and saved. The logic circuit being tested is then stimulated by the same test pattern sequence and the number of transitions and final logical states achieved are compared. Failure to have identity between the known good logical circuit and the logical circuit being tested both as to number of transitions and final logical state achieved for the tested points indicates a malfunction within the board which would not be detected by mere sampling of the final output state alone.

Automatic System Level Test a Fault Location for Large Digital Systems

Abstract: A system for automatic test generation and fault location, FLT-700, is described in this paper. It can treat large digital systems with 100K blocks (logic gates) or more. This is realized by utilizing Scan-Path concept, automatic partitioning and test generation techniques and automatic fault location technique. Serviceability for large computer systems can, therefore, be improved and easy maintenance realized.

Generation of Optimal Transition Count Tests

Abstract: The problem of generating minimum-length transition count (TC) tests is examined for combinational logic circuits whose behavior can be defined by an n-row fault table. Methods are presented for generating TC tests of length n+2 and 2n-1 for fault detection and fault location, respectively. It is shown that these tests are optimal with respect to the class of n-row fault tables in the sense that there exist n-row fault tables that cannot be covered by shorter TC tests. The practical significance of these tests is discussed.

SALOGS-IV A Program to Perform Logic Simulation and Fault Diagnosis

Abstract: The simulation algorithm for multiple logic levels, modeling considerations and the network and simulation languages used in SALOGS, Version IV, are discussed. Also presented is the method for fault diagnosis and test sequence generation and the philosophy used in the code development.

An Optimal Approach to Fault Tolerant Software Systems Design

Abstract: A systematic method of providing software system fault recovery with maximal fault coverage subject to resource constraints of overall recovery cost and additional fault rate is presented. This method is based on a model for software systems which provides a measure of the fault coverage properties of the system in the presence of computer hardware faults. Techniques for system parameter measurements are given. An optimization problem results which is a doubly-constrained 0,1 Knapsack problem. Quantitative results are presented demonstrating the effectiveness of the approach.

Fault secure multiple-valued logic networks

Abstract: Fault secure multiple-valued logic networks have their outputs encoded in an error-detecting code so that assumed failures either result in no output error or in a detectable (noncode) output. In this paper we discuss a way of constructing fault secure combinational networks as well as a generalization that we define to be “strongly fault secure.” The only constraint on the networks themselves is that they be made of positive unate gates and use unordered output encodings.The fault assumptions are quite general; they include stuck-at faults as well as many other failures which seem reasonable in a multiple-valued technology. Protection is provided against both permanent and intermittent faults. Various unordered codes and their properties are discussed as is the construction of check circuits that are themselves fault secure or strongly fault secure.

A note on single fault detection in positive resistor circuits

Abstract: The no gain property of positive resistor circuits is used to show that in such circuits if one and only one resistor changes from its nominal value, then the voltage change across that resistor is greater than or equal to all of the other resistor voltage changes in the circuit. This property can be used to locate single faults in positive resistor circuits.

The synthesis of fault trees

Abstract: Fault tree synthesis models, in order to be useful in assessment and control of risk, must be modular in the modeling of behavior; all possible modes of behavior must be describable; loops should be modeled naturally; range of variables must be greater than 0.1; and the fault tree or Boolean equation must be deduced from the models. Multiply-edged directed graphs models meet the needs of a fault tree synthesis. The Lapp-Powers fault tree synthesis algorithm is based on logical combinations of digraph variables which could cause a particular deviation in an output variable. Given the correct models, the algorithm will generate the correct fault tree for the system. A flow control system and a heat exchanger system are analyzed, as examples of using the models and the algorithm.

Fault Analysis in Electronic Circuits and Systems. II.

Abstract: : Several Studies resulting from a research program directed at the development of mathematical foundations for fault analysis in electronic circuits and systems are reported Specific topics covered include fault analysis by functional methods, fault analysis in linear and affine sequential circuits, and fault prediction

Incomplete Fault Coverage In Modular Miltiprocessor Systems

Abstract: In an early paper Preparata, Metze, and Chien formulated a model of system level diagnosis in which it is assumed that a fault-free module can detect any fault in a module it is testing. In practice this assumption may not be true. If a fault-free module can only detect p × 100% of all faults (or equivalently detect a fault with probability p) we refer to this as incomplete fault coverage. With incomplete fault coverage it is possibile that a system will fail to detect a faulty module. In this paper we consider the problem of designing systems which minimize the probability of failure to detect for a given fault coverage p. We show that the ability to detect faults does not only depend on the number of modules n and testing links m, but also in general, on the structure of the network (i.e. the exact interconnection pattern of testing links). Systems which are optimal with respect to fault detectability are presented for various n and m, and a correspondence between detectability and the girth of the system testing graph is presented. The effect of system structure on diagnosability is briefly discussed.

False fault generation control system

Abstract: PURPOSE: To change arbitrarily a false fault generation position, a timing, etc., without treatments such as insertion of a special instruction into an operating program by utilizing the processing function of a sub-processing unit to control false fault generation. CONSTITUTION: An instruction address, an address which designated the set position of a false fault, and data which sets the generation timing of the false fault are set to data processing unit 1, and the instruction address to generate the false fault and the generation timing are held in stop address register 12 and timing data register 13 respectively. Independent storage program-type system control unit 2 is connected to this unit 1 through interface 15 to SMP, and the processing function of unit 2 is used to compare the false fault generation timing set in register 13 with the timing of an executing instruction by address comparator circuit 5 when unit 1 is executing the instruction of instruction address register 3, and a false fault signal is generated in a position designated by register 13. COPYRIGHT: (C)1980,JPO&Japio

Fault detection in sequential machines with increased fault coverage

Abstract: This letter develops an approach for fault detection and checking sequence design of sequential machines based on the principle of machine modification through augmentation of extra input and extra outputs, taking into consideration the case where faults occurring in a machine may cause an increase in its number of states.

Functional Simulation and Fault Diagnosis

Abstract: Some aspects of the application of functional simulation to fault diagnosis are discussed. A technique for functional simulation that preserves a high level of accuracy is described. Applicability of this method to fault simulation and diagnosis is shown by presenting an approach to diagnostic testing and giving an algorithm for test point placement. The compatibility of the functional simulation technique and the partitioning of the system for diagnosis is indicated.

Fault diagnosis system for duplicating central process system

Abstract: PURPOSE: To secure the switching to the other process system in case the fault takes place at one process system and at the same time to write the contents of the system containing the fault into the auxiliary memory device, and thus to perform the automatic diagnosis of the fault via the normal system and based on the written memory contents CONSTITUTION: Auxiliary memory device 216 and channel 214 are formed into a common device, and other main memory 200 and 210 plus CPU202 and 212 are duplicated For the fault diagnosis system of such duplicating central system, data transfer unit 218 is provided to detect the system-down of the system in the access state containing 200 and 210 plus 202 and 212 Then the memory contents is memorized directly into device 216 via channel 217 from 200 or 210 of the faulty system, and the contents memorized in unit 218 via 210 or 200 plus 212 or 202 which was switched to the access state due to the fault occurrence Thus, the cause of the fault is diagnosed COPYRIGHT: (C)1979,JPO&Japio

Interactive fault isolation of analog hybrid circuit cards

Abstract: Modern custom hybrids which contain many analog and also digital circuits in a single flatpack, have increased the functional density of circuit cards 4 to 6 times. The consolidation of many complex functions and differing technologies on a single card has exposed the need for new fault isolation techniques, particularly for the manufacturing environment, due to high first-time through failure rates, the difficulty and cost of manual fault isolation, and the large cost of hybrid replacement. The interactive fault isolation technique optimizes the key attributes of the ATE and the human: the ATE rapidly and accurately characterizes the analog fault signatures, but the actual diagnosis is performed off-line with the aid of a fault dictionary by a human. Fault signatures of unknown signals are rapidly acquired at connector pins and at component nodes with an adaptively programmed DMM, counter, and Waveform analyzer which are appro priately connected over the ATE's instrument bus. The acquired signal characteristics are tested for validity prior to display and printing. The interactive technique does not require the development of individual diagnostic programs for each circuit card and is applicable to existing 2nd and 3rd generation ATE.

Logout system of memory controller

Abstract: PURPOSE: To enable a memory controller in a system operation state to collect data when a temporarily fault occurs by controlling the freeze release of the access acception of the memory controller, the logout of the internal state at fault time and storage to an external memory through a fault processor. CONSTITUTION: When fault generating circuit 21 of memory controller 1 detects a fault such as address and parity errors, FF22 is set to close AND gates 16 and 17 through OR circuit 20, thereby freezing the access acception of address acception circuit 18 while the set output of fault detection FF22 is supplied to the fault processor. Consequently, the fault processor reads out the states of acception detection FF19 of circuit 1 and a register and stores them in an external memory. Then, the fault processor resets FF22 to release the acception freeze of access of circuit 1. Those operations are carried out automatically and when a temporarily fault occurs, status data at the time of the fault of the memory controller can be collected while the operation of a system including CPU is carried on. COPYRIGHT: (C)1980,JPO&Japio

Fault point decision system

Abstract: PURPOSE: To secure an accurate decision for the fault point of the transmission line based on the observation quantity of the self-end and the known value by deciding the virtual fault point where the phase coincidence is secured between the voltage of the virtual fault point and the current of the calculated fault point. CONSTITUTION: Fault point current ID of the self-end is decided by the current of before and after occurrence of the fault of the transmission line, and then fault point current IF is calculated based on current ID and phase θ. On the other hand, voltage VD of the virtual fault point featuring distance X is decided based on self-end voltage V, current I, the line constant and other factors, and then the virtual fault point where the phase has an agreement between voltage VD and current IF is selected. Thus distance X from the self-end of the virtual fault point coincides with the fault point. As a result, the fault point of the transmission line can be decided accurately at the self-end based on the observation quantity of the self-end and the known value. COPYRIGHT: (C)1980,JPO&Japio

MNFP — a new technique for efficient digital fault simulation

Abstract: Since digital fault simulation is a costly process, it is important to use very efficient techniques to perform this function. To this end, this study suggests that parallel fault simulators couldbe implemented with a new fault-simulation technique, called MNFP (multiple number of faults per pass). The technique intends to partition the total fault set into a number of fault groups which can be simulated as multiple faults. The fault group mentioned above should be structured such that ‘a test that detects any single fault in the group will detect the group, and conversely, a test that detects a group will detect at least one single fault in the group’. Thus, an initial attempt is made to detect a faulty group, then the single faults inside the group are located. During the required fault-partitioning process, such erratic phenomena as fault-masking effects and fictitious multiple-fault generation must be eliminated for the fault groups to have the required property. Two approaches to fault partitioning are made for this technique of fault simulation: PFP (probabilistic fault partitioning) and MFP (modular fault partitioning). Significant savings in simulation time are expected to be realized from the MNFP technique of fault simulation.

An algorithm for minimum length fault tests for combinational circuits

Abstract: One of the important problems in the area of fault tolerant computing is the generation of optimal fault-test seta for the combinational logic circuits. Most methods require generation of tests for all possible faults before the choice of an optimal test set is made. This necessitates large computer space and time. In this paper an efficient algorithm is presented for the generation of a minimum length fault test directly. Moreover, the algorithm conveniently partitions the test set into two subsets corresponding to the output being zero or one for the fault-free network. An example is given to illustrate the procedure.