Showing papers on "Stuck-at fault published in 1979"

Detection of Faults in Programmable Logic Arrays

Abstract: A new fault model is proposed for the purpose of testing programmable logic arrays. It is shown that a test set for all detectable modeled faults detects a wide variety of other faults. A test generation method for single faults is then outlined. Included is a bound on the size of test sets which indicates that test sets are much smaller than would be required by exhaustive testing. Finally, it is shown that many interesting classes of multiple faults are also detected by the test sets.

Online digital fault locator for overhead transmission line

Abstract: The ability to determine quickly and accurately where faults have occured on a transmission line has long been an operating man's dream. This paper describes a completely digitalised online fault locator which takes input signals from existing c.t.s and p.t.s and works on a reactance-ratio-measurement principle. It operates in less than two cycles from the instant that the relay delivers a trip output, and is therefore capable of locating transient as well as permanent short-circuit faults. Furthermore, a suitable compensation in fault-locator inputs is proposed which results in increased resistive coverage for the suggested fault locator when applied to double-end feed lines.

A theory and an algorithm for analog circuit fault diagnosis

Abstract: A theory for the study of the analog circuit fault diagnosis problem is developed. Sufficient conditions are presented such that the value of each of the network elements is uniquely determinable from the network's behavior as seen from its external terminals. It is shown how one can determine-considering only the circuit's topology-whether or not it is possible to compute the element values of a resistive network from the test-terminal measurements, before going through the process of actually attempting to solve for element values. The implications of the results are discussed when applied to networks containing solid-state devices such as diodes and transistors. Finally, an algorithm for the actual computation of the element values is proposed and its global convergence is proved. Furthermore, several examples are included to illustrate the applications of the theory developed in this paper.

Fault dictionary based upon stimulus design

Abstract: A method of fault signature generation is presented that is based upon state space analysis of linear circults. An input control sequence is designed to reduce a nontrivial initial state of the circuit under test to the zero state in finite time. The realization of this stimulus as a piecewise constant waveform has step amplitudes that are exponential functions of the poles of the circuit under test. Perturbations of these amplitudes, engendered by element drift failure, constitute a fault signature. Single element value perturbations engender fault signature trajectories in signal space, and the fault dictionary is constructed by defining disjoint decision regions (hypervolumes) around each fault signature trajectory in the signal space. Circuit zeros of transmission allow the dimension of the signal space to be augmented with perturbation of such response waveform parameters as zero crossings. The theory of stimulus design for fault isolation in linear networks and a generalized matrix inverse method for computing the stimulus amplitudes from the pulse response of strictly proper circuits are presented. Examples of response waveforms and fault signature trajectories are given for several circuits.

Structure for physical fault simulation of digital logic

Abstract: A shift register connected to elementary gates is added to a digital network to form a fault simulator. The shift register and the additional gates can select a connection from the digital network and simulate a fault on the selected connection. Connection selection is done at a speed comparable to that at which the digital network operates and fault simulation is nondestructive. By resetting the shift register the fault simulator performs as if the digital network were fault-free. To simulate certain faults in the digital network a predetermined fault injection pattern for the faults to be simulated is entered into the shift register.

Fault detecting system for locating a fault point with a fault resistance separately measured

Abstract: At an end (11) of a power transmission line (10), a fault detecting system monitors variations resulting from a fault in voltage and current being transmitted through the line and calculates the distance between the end and location (20) of the fault by the use of the variations and a line constant inherent to the line, such as that given by the characteristic impedance and the propagation constant, to thereby locate the fault with a sufficient accuracy by directly using the commercial frequency and without affected by the impedance that accompanies the fault. The system can calculate the fault impedance from the distance and those backward impedances seen at the end and an opposing end (12) of the line backwardly of the location of fault.

Multiple Fault Diagnosis in Combinational Networks

Abstract: The concept of prime faults is introduced for the study of multiple fault diagnosis in combinational logic networks. It is shown that every multiple fault in a network can be represented by a structurally equivalent fault with prime faults as its only components. Functional and structural masking and covering relations among faults are defined. These relations can be exploited to greatly simplify multiple fault analysis and their test generation. We present an efficient algorithm that generates a multiple fault detection test set and identifies redundancies. Suggestions for designing networks to yield a minimum number of tests in the multiple fault detection test set are also included.

Method for locating a fault point on a transmission line

Abstract: A fault component current is obtained in response to a fault at a fault point within a protective section on a transmission line at one end of the protective section. Assuming that a phase difference between the fault component current and a fault point current flowing through the fault point is known, the fault point current is obtained on the basis of the fault component current and the phase difference. Then, a voltage at an assumed fault point is obtained by using voltage and current at the one end of the protective section and the line constants of the protective section. An assumed fault point is then obtained to permit the voltage at the assumed fault point to be in phase with the fault point current. The assumed fault point is assumed to be a true fault point.

Generalised polyphase fault-analysis program: calculation of cross-country fault

Abstract: A general computer program using the phase co-ordinate technique has been developed for analysing series, shunt and simultaneous faults on balanced and unbalanced polyphase electrical networks. The program eliminates the need for maintaining numerous fault analysing subroutines, one for each kind of fault, and makes the solution of many difficult and previously unsolvable problems possible. It is employed to analyse the cross-country fault involving different phases. The solution method, program outlines and postfault results of voltages, currents and apparent power of an actual power system are given.

On Necessary and Sufficient Conditions for Multiple Fault Undetectability

Abstract: This correspondence states necessary and sufficient conditions for a multiple stuck-at fault in a combinational network to be undetected by a test set. The conditions are given in terms of fault masking relationships. It is shown that several other statements on this subject which have appeared in the literature are invalid.

Optimum fault isolation by statistical inference

Abstract: Fault Isolation is always based on a statistical model of fault occurrence and measurement error. Usually the statistical assumptions are impilcit and unstated. Making them explicit and systematically exploring their consequences proves to be an extremely powerful method of developing optimum fault isolation techniques. A criterion is developed here for optimum isolation of catastrophic faults. The technique evolved serves, in fact, to determine the actual probability of each fault based on the observed values of the measured quantities. These probabilities provide ambiguity statistics for the degree of isolation attained. A method is also developed for optimally employing the measurements to detect and isolate noncatastrophic faults when catastrophic faults are absent. Information theoretic criteria are derived for the optimum selection and sequencing of candidate tests. These can be applied at test time in a refined version of branched "go-no go" logic, and also at test-development time to screen a large set of candidate tests down to a small efficient subset.

Systematic fault simulation in an analog circuit simulator

Abstract: With the recent increase in both fault isolation and fault tolerant design, automated and systematic methods of analyzing fault situations and their impact on the operation of solid-state circuitry are becoming increasingly important. In this paper we will explore the philosophy and techniques behind the design of a system for simulating various catastrophic failures in integrated circuits which is being implemented in a commercially available nodal circuit simulator ISPICE. We address the issues of how certain failure conditions can be identified and simulated, how certain sets of such conditions can be identified and used to reduce the cost of such a simulation without impacting the results, and how well structured reports can reduce large volumes of data to easily interpreted results. Finally, we also explore some of the more elaborate analysis and reporting techniques we expect to include in future implementations of automated fault diagnosis software.

A switching circuit

Abstract: A switching circuit (1) has a solid state power switch (9) which is either a PNP or NPN transistor or a VMOS p-or n-channel device. Three individual sensing circuits (2, 3, 4) are set to indicate whether a predetermined operating characteristic of the switch (9) is greater or less than a given threshold value and thus to indicate if a fault is present in the switch (9) or the load (L) it supplies. Digital logic circuit means comprising three logic circuits (5, 6, 8) produce two digital signals (D, P) from the output signals of the sensing circuits respectively indicating if a fault exists and if it is a serious fault or not. A circuit (7) comprising gating means disables the switch (9) in the event of a serious fault and a delay circuit (33, 34) is provided associated with the logic circuit means to prevent current surges due to short circuit faults being confused with normal operating current surges in switch on.

A pragmatic approach to automatic test generation and failure isolation of analog systems

Abstract: Digital automatic test generation has been successful due to simplified modeling at the logic gate or higher level, rather than the component level, and to logic simulation performed for the stuck-at failure mode only. Analog automatic test generation generally requires modeling and simulation at the component level and continuous failure modes over a certain range of parameter values. As a result, most analog automatic test generation and fault isolation techniques demand a large computational capability on the ATE or off-line computers. Any practical analog automatic test generation solution must eventually address this problem. All analog automatic test generation techniques presently under investigation assume the availability of all or certain designated nodes as test points for stimulus injection and/or response measurement. This assumption suggests the possibility of GO-NO-GO tests to fault isolate to a "primitive," which may contain several circuit components. The "complementary signal" design suggested by Schrelher, appears well suited for providing an effective GO-NO-GO test; the signal and its response are determined by the poles and zeros of the circuit.

A Functional Form Approach to Test Set Coverage in Tree Networks

Abstract: To efficiently perform the fault analysis of digital networks it is necessary that pertinent fault interrelationships be utilized. However, to determine these fault interrelationships can entail an analysis which is quite complex and thereby reduces the overall advantage of utilizing the gained insights in a fault analysis process. In this paper we suggest an approach to establishing the existence of a certain fault interrelationship relative to test set coverage in tree networks which is based only on the form of the output function. A procedure is given for generating a form expression (called an L-expression) corresponding to that function. A theorem is stated regarding the interpretation of these form expressions relative to test set coverage.

Design Of A Fault-Tolerant Microprocessor

Abstract: Following an overview of the general practice in the reliable design of digital systems and the discussion of those design considerations for selfchecking and fault tolerant machines, the Self- Checking Microprocessor proposed by Maki (3) is brought to the readers' attention. Then the posibility of using this self-checking design in a hybrid-redundant microprocessor system is explored. In this paper, the self-checking processor and the main memory unit are triplicated for the purposeof error detection and momentary fault masking. Reconfiguration, allowing stand by units to replace failed unit, is possible due to the intelligence of the individual processors. Similarly the memory modules can be switched ON/OFF line by an additional self-checking processor incorporated into the design assuming the task of the majority voter of this TMR system.

Power semiconductor protection circuit with fault detection

Abstract: A protection and fault detection circuit for an electrically isolated semiconductor power driver acting as a switch to connect a load such as a relay coil to a source of voltage employs logic circuitry responsive to input signals indicative, respectively, of the desired state of driver operation and the conductive condition of the driver itself to effect a rendering of the device to the nonconducting state when an overload or other fault condition exists. A monitoring circuit responsive to specified operating parameters of the semiconductor power driver and its associated circuitry provides an output fault signal which is indicative of a fault condition and may be employed for remedial and/or indicating purposes.

Ground fault protective circuit interrupter

Abstract: A fault current protection interrupter which is also sensitive to direct current operates less well in the presence of a strong A.C. fault current. According to the invention, the magnetic circulation resulting from an A.C. component of the fault current is compensated for in a core 12, by means of a suitable circuit, which is shown in dotted lines in Figure 7, in that a corresponding current is directed via a coil 1 of this core, as shown in Figures 1 and 7. This compensation current is a measure of the A.C. component. The core, in which there is no interfering, changing magnetic flux, is used to establish the D.C. component. The components of the D.C. fault current and of the A.C. fault current established in this way are transferred to a suitable evaluation circuit which initiates a disconnection if the values arising are not permissible.

Detecting system for junctor fault

Abstract: PURPOSE:To secure the detection with discrimination for the multiplex fault patterns and thus secure a quick and accurate countermeasure to the fault, fractionating the parity check section and furthermore blocking the transmission of the error information to the subsequent positions. CONSTITUTION:Both the parity checker PC1 and the parity generator PG1 are installed at the output side of the time-divisionswitch 200. And in the case of the fault (a), the parity checker PC on the incoming side corresponding junctor highway of the space switch module 20 detects the parity error. In addition, the parity checker PC at the outgoing side also detects the error. Thus the fault can be processed en bloc under the control of the checkers PC since the fault process is carried out through the control circuit 201. In the case of the fault (b), the error is checked through the checker PC1 not by the checker PC for easy distinction. In the case of the fault (c), just one unit of the outgoing side checker PC1 carries out the error detection. And in the case of the fault (d), the error is checked only by the incoming side checker PC of the switch 104. In such way, the fault report is given to the central process module 30 through one unit of the control circuit for one unit of the fault.

On-line Fault Detection And Correction In Microprocessor Systems

Abstract: In most on-line diagnostic schemes whenever a fault is detected in a system, a rather involved system recovery routine is initiated irrespective of whether the fault is caused by a failure inside a chip, or by a failure outside a chip, say, on the bond connecting a pin to the chip. Failures of the latter type cause errors only when some information is being transferred from one chip to another chip. In this paper, 'two new techniques to system recovery are described for the case when an error is on any such data transfer path. These schemes are implementable locally, and the system is ensured to recover from any single stuck-at fault, single AND-bridge fault, or single OR-bridge fault in a single retry. The system- recovery from faults internal to chips can be per- formed using sophisticated routines. Thus, two- level approach to on-line system diagnosis seems to be more efficient.

Trends in reliability modeling technology for fault tolerant systems

Abstract: Reliability modeling for fault tolerant avionic computing systems was developed. The modeling of large systems involving issues of state size and complexity, fault coverage, and practical computation was discussed. A novel technique which provides the tool for studying the reliability of systems with nonconstant failure rates is presented. The fault latency which may provide a method of obtaining vital latent fault data is measured.

Generation of Hazard Free Tests Using the D-Algorithm in a Timing Accurate System for Logic and Deductive Fault Simulation

Abstract: It is described how a timing accurate system for logic and deductive fault simulation can be used in the forward tracing part of the D-algorithm. The logic simulation is used for the forward implication and the verification phases. The deductive fault simulator is used for D-propagation. Some results from executions of the test generation program are presented.

Diagnosis of Faults in Modular Trees

Abstract: Diagnosis of stuck-at faults (s-a-f's) in modular trees is studied. Detection conditions for each distinguishable s-a-f in a module are derived. For single s-a-f's, the detection conditions are easily partitioned to achieve fault location by performing a small number of additional tests. A multiple s-a-f that produces the same test result as a single s-a-f can be located by applying additional tests whose number grows with the tree depth. All other multiple s-a-f's are detected but cannot be located. In this paper location algorithms for combinational modular trees are presented in detail. They are then modified to locate faults in modular trees which realize arbitrary definite machines. Since a pair of these tree structures can be connected to realize arbitrary sequential machines, the results derived here are useful in diagnosing sequential machines. The ability to diagnose faults, combined with the fact that the function of the tree is easily altered, makes this structure attractive in reconfiguration applications. In particular, application to array processors is suggested.

Machine tool fault recognition system - uses comparison of actual and desired value signals using acquisition unit and quantifier

Abstract: The machine tool fault recognition system has a fault-signal acquisition unit with a quantifier. Applied to the unit's inputs are actual-stage signals and trend-value signals. These are transmitted at the outputs as evaluated fault signals directly or via a fault-signal summing unit to a fault-signal logic circuit. The circuit outputs are connected to hierarchy levels of the fault and primary-fault display. The logic circuit control signals belonging to the hierarchy levels are connected to the machine-tool control.

Fault location in a noisy multiple-nonlinearity servosystem

Abstract: In certain applications it is desirable to isolate faults in a nonlinear system using dynamic measurements at a limited number of access points. This can be achieved by stimulating the system with a serial mode sinusoidal signal and using the fundamental and higher harmonic responses at the access points to form the system "signature." The fault signature is then compared with a restricted number of stored signatures of known faults via the nearest neighbor rule.

Fault analysis of analog electronic systems: Algorithms based on fuzzy sets

Abstract: : There are essentially three fundamental problems involved in achieving effective automatic generation of fault isolation tests for analog electronic systems: feature extraction, fault classification and diagnosis. For practical electronic circuits having component drifts and measurement noise, how are we able to introduce fuzzy set concepts and provide methods to achieve fault classification and diagnosis? Along with the feature extraction problem, given an electrical network of known topology, what are the conditions for testability? To attack the long standing fault isolation problem in analog electronic circuits, we have focused on two of the major problems. One is the presence of uncertainties such as indeterminacy, vagueness, randomness, and so on that naturally arise during the solution procedure of analog fault isolation. The other is the presence of topological restrictions inherent in specific circuit configurations.

Single fault equivalence classes and minimal test sets in combinational networks

Abstract: This paper deals with two important related problems in the area of detection of single faults in combinational logic networks. The first is to determine the different equivalence classes of all possible single faults in the given network and this has been achieved by introducing the concept of a new typo of fault graph. Algorithms have been developed to construct the fault graph of a given combinational network from the fault graphs of the component gates and to enumerate the equivalence classes of faults from the fault graph of the network. The second problem, dealt with in this paper, is to enumerate the minimal complete test set to detect single faults in the network and this has been carried out by utilizing the concept of boolean difference in a new manner, so that the computational complexity has been greatly reduced compared to the existing procedures of fault detection by boolean difference

The cell method, a new approach to multiple stuck-at-fault test generation

Abstract: A new concept for generating test sets for detecting multiple faults in combinational networks will be introduced in this paper. A procedure which will be called the ‘cell method’ allows near optimal test generation with case of computation for most combinational networks. This procedure involves breaking down complex networks into cells, solving the test generation problem for each cell and then correctly integrating these results into the complete test set for the original network. Various modifications to the cell method are also included. These modified procedures allow the generation of test sets for large classes of single and multiple output networks. A simple way of predicting the maximum number of tests needed for complete testing of various types of networks has also been introduced. This determines the number of tests without actually generating the tests.