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Showing papers on "Stuck-at fault published in 1980"


Journal ArticleDOI
TL;DR: In this paper, a general graph-theoretic model is developed at the register transfer level which takes the microprocessor organization and the instruction set as parameters and generate tests to detect all the faults in the fault model.
Abstract: The goal of this paper is to develop test generation procedures for testing microprocessors in a user environment. Classical fault detection methods based on the gate and flip-flop level or on the state diagram level description of microprocessors are not suitable for test generation. The problem is further compounded by the availability of a large variety of microprocessors which differ widely in their organization, instruction repertoire, addressing modes, data storage, and manipulation facilities, etc. In this paper, a general graph-theoretic model is developed at the register transfer level. Any microprocessor can be easily modeled using information only about its instruction set and the functions performed. This information is readily available in the user's manual. A fault model is developed on a functional level quite independent of the implementation details. The effects of faults in the fault model are investigated at the level of the graph-theoretic model. Test generation procedures are proposed which take the microprocessor organization and the instruction set as parameters and generate tests to detect all the faults in the fault model. The complexity of the test sequences measured in terms of the number of instructions is given. Our effort in generating tests for a real microprocessor and evaluating their fault coverage is described.

380 citations


Journal ArticleDOI
TL;DR: At the end of an IC production line, integrated circuits are generally submitted to three kinds of tests: 1) parametric tests to check electrical characteristics (voltage, current, power consumption), 2) dynamic tests to Check response times under nominal operating conditions, and 3) functional tests toCheck its logical behavior.
Abstract: At the end of an IC production line, integrated circuits are generally submitted to three kinds of tests: 1) parametric tests to check electrical characteristics (voltage, current, power consumption), 2) dynamic tests to check response times under nominal operating conditions, and 3) functional tests to check its logical behavior.

350 citations


Journal ArticleDOI
Savir1
TL;DR: This paper focuses on classical testing of combinational circuits and the large storage requirement for a list of the fault-free response of the circuit to the test set.
Abstract: Classical testing of combinational circuits requires a list of the fault-free response of the circuit to the test set. For most practical circuits implemented today the large storage requirement for such a list makes such a test procedure very expensive. Moreover, the computational cost to generate the test set increases exponentially with the circuit size.

219 citations


Journal ArticleDOI
TL;DR: A linear feedback shift register can be used to compress a serial stream of test result data and it is possible for an erroneous bit stream and the correct one to result in the same signature.
Abstract: A linear feedback shift register can be used to compress a serial stream of test result data. The compressed erroneous bit stream caused by a fault is said to form the "signature" of the fault. Since the bit stream is compressed, however, it is possible for an erroneous bit stream and the correct one to result in the same signature.

194 citations


Journal ArticleDOI
TL;DR: The main vehicle of this approach is the deduction of internal line values in a circuit under test N*.
Abstract: In this paper we present a new approach to multiple fault diagnosis in combinational circuits based on an effect-cause analysis. The main vehicle of our approach is the deduction of internal line values in a circuit under test N*. The knowledge of these values allows us to identify fault situations in N* (causes) which are compatible with the applied test and the obtained response (the effect). A fault situation specifies faulty as well as fault-free lines. Other applications include identifying the existence of nonstuck faults in N* and determination of faults not detected by a given test, including redundant faults. The latter application allows for the generation of tests for multiple faults without performing fault enumeration.

125 citations


Proceedings ArticleDOI
23 Jun 1980
TL;DR: This paper presents the basic concepts of a new fault diagnosis technique which has the following features: is applicable to both single and multiple faults, does not require fault enumeration, and can identify faults which prevent initialization.
Abstract: This paper presents the basic concepts of a new fault diagnosis technique which has the following features: 1) is applicable to both single and multiple faults, 2) does not require fault enumeration, 3) can identify faults which prevent initialization, 4) can indicate the presence of nonstuck faults in the D.U.T., 5) can identify fault-free lines in the D.U.T. Our technique, referred to as effect-cause analysis, does not require a fault dictionary and it is not based on comparing the obtained response of the D.U.T. with the expected response, which is not assumed to be known. Effect-cause analysis directly processes the actual response of the D.U.T. to the applied test (the effect) to determine the possible fault situations (the causes) which can generate that response.

67 citations


Journal ArticleDOI
TL;DR: For a new class of fault situations called hybrid fault situations, the fault diagnosing capabilities of systems which for testing/monitoring purposes can be viewed as being composed of independent units are considered.
Abstract: For a new class of fault situations called hybrid fault situations, we consider the fault diagnosing capabilities of systems which for testing/monitoring purposes can be viewed as being composed of independent units. The classical Preparata, Metze, and Chien model (PMC model) is used to specify the various testing assignments among the units. Hybrid fault situations are described as explicitly bounded combinations of permanently and intermittently faulty units. This new concept of a hybrid fault situation includes as special cases the all permanent fault case and the unrestricted intermittent fault case which have both been previously considered with PMC models. A general characterization of the so-called connection assignment of a PMC model is established for a diagnosing capability which is referred to as hybrid fault diagnosability without repair. This diagnosing capability is compatible with the well-known permanent fault diagnosability without repair concept, and the quality of this diagnosing capability is shown to be correct, but sometimes an incomplete diagnosis where the incompleteness is solely a consequence of intermittently faulty units. The characterization for hybrid fault diagnosability without repair is seen to encompass as extreme cases the previously known special characterizations for permanent and unrestricted intermittent diagnosability without repair. Fundamental interrelationships are determined among parameter bounds used to describe the hybrid fault cases which can be diagnosed for a given PMC model.

62 citations


Journal ArticleDOI
Agarwal1
TL;DR: This paper develops a model of PLA's which allows one to represent a contact fault in a PLA as a stuck-at fault in the model of the PLA, and shows that more than 98 percent of all multiple contact faults of size 8 and less are inherently covered by every complete single contact fault test set in aPLA.
Abstract: The increasing recognition of PLA's as efficient and viable modules for such purposes as microprogramming and design of sequential controllers has led to a growing interest in the development of optimum fault detection test sets for these modules. It is now well known that a fault type which is unique to PLA's is the class of contact faults. A single contact fault is the spurious presence or absence of a contact between a row and a column of a PLA. We consider in this paper the problem of determining the capability of complete single contact fault test sets to cover multiple contact faults of PLA's. Our approach consists of developing a model of PLA's which allows one to represent a contact fault in a PLA as a stuck-at fault in the model of the PLA. Using this model, it is shown that more than 98 percent of all multiple contact faults of size 8 and less are inherently covered by every complete single contact fault test set in a PLA. Applications of this model to stuck-at fault diagnosis are also discussed.

61 citations


Journal ArticleDOI
TL;DR: The study of bridging faults (or short circuits that occur between conducting paths) has become increasingly important with the advent of LSI technology, but what has yet to be explored are the effects of undetectable bridges faults on the tests designed to detect stuck-at faults.
Abstract: The study of bridging faults (or short circuits that occur between conducting paths) has become increasingly important with the advent of LSI technology To date, only a very few papers have been published on this topic Specifically, little is known regarding undetectable bridging faults More importantly, what has yet to be explored are the effects of undetectable bridging faults on the tests designed to detect stuck-at faults

45 citations


Journal ArticleDOI
TL;DR: Self-checking approaches developed so far deal with a gate level representation of logical circuits but do not account for constraints which may result from an implementation by integrated circuits.
Abstract: Self-checking approaches developed so far deal with a gate level representation of logical circuits. They do not account for constraints which may result from an implementation by integrated circuits. This paper is concerned with such practical problems and their respective significance.

42 citations


Proceedings ArticleDOI
23 Jun 1980
TL;DR: The balance achieved here, in part dictated by the demands of fault simulation, emphasizes execution speed, adequate accuracy, and a simple modeling method.
Abstract: Basic goals for logic and fault simulation are accuracy, execution speed, and modeling ease. Accuracy means that adequate state and timing detail must be maintained, and that good and faulted networks must be simulated with equal accuracy. High speed simulation is desirable to perform massive fault simulations of large networks, and modeling ease is desirable to build models easily and quickly.It should be observed that some of the above goals are in mutual conflict. For example, modeling ease and high execution speed are normally only achievable by a sacrifice in accuracy, and high accuracy is only possible by more elaborate modeling efforts or slower execution speeds, or both. As a consequence it becomes important to achieve a balance between these goals. The balance achieved here, in part dictated by the demands of fault simulation, emphasizes execution speed, adequate accuracy, and a simple modeling method.A new logic and fault simulator, VOTE (Verification of Test Effectiveness) is described. The specifics to be described here fall into two categories: those which are of general interest, and those which are strictly implementation items.

Patent
04 Apr 1980
TL;DR: In this paper, a ring-configured network of multiple inter-communicating data stations is considered, where each data station includes a fault sensing circuit, a test-pulse generating circuit and a switching circuit as well as a transmitter and a receiver circuit, and the test pulse generating circuit responds to a sensed fault to transmit, sequentially, in opposite directions along the ring.
Abstract: A ring-configured network of multiple inter-communicating data stations in which each data station includes a fault sensing circuit, a test-pulse generating circuit and a switching circuit as well as a transmitter circuit and a receiver circuit, and the test pulse generating circuit responds to a sensed fault to transmit, sequentially, in opposite directions along the ring, test signals which, in combination with the fault sensing circuit, indicate the direction of any fault and terminate the line in the direction of the fault at the characteristic impedance of the line. Thus, normal communications can continue between the stations despite the fault.

Journal ArticleDOI
TL;DR: The capability of the method of phase coordinates to extend the range of power system network analysis beyond the scope of transformation methods, such as the symmetrical component method, without incurring any increase in model complexity is illustrated.

Journal ArticleDOI
Savir1
TL;DR: Intermittent faults in combinational circuits may appear and disappear randomly; hence, their detection requires many repeated applications of test vectors, which requires efficiently minimizing the time required for a test, while still achieving a high degree of fault detection.
Abstract: Intermittent faults in combinational circuits may appear and disappear randomly; hence, their detection requires many repeated applications of test vectors. Since testing reduces the time available for computation, it is necessary to efficiently minimize the time required for a test, while still achieving a high degree of fault detection.

Journal ArticleDOI
TL;DR: Conditions for the equivalence and nonequivalence of two fault classes are obtained and these results are applied to the problem of equivalence identification in two-level logic networks where they provide a substantial reduction in the amount of computation required.
Abstract: The properties of combinational logic functions and networks that influence equivalence among stuck-type faults are investigated. It is shown that the equivalence of certain types of faults depends only on the function being realized. For instance, the fault classes among primary input/output faults are of this type. It is shown that every irredundant realization of the two-variable EXCLUSIVE-OR function has a unique set of ten fault classes. A fault class F in a module M contained in a network N is called intrinsic, if F can be determined from M alone, i. e., F is independent of N. Using the concepts of intrinsic equivalence and inversion parity, conditions for the equivalence and nonequivalence of two fault classes are obtained. These results are applied to the problem of equivalence identification in two-level logic networks where they provide a substantial reduction in the amount of computation required.

Proceedings ArticleDOI
06 May 1980
TL;DR: An analysis of the fault tolerance of β-networks intended for multicomputer applications and it is shown that there is a one-to-one correspondence between minimal critical faults and the cutsets of the circuit adjacency graphs derived from the β-network.
Abstract: Several proposals have been made for using a class of connecting networks called b-networks in multicomputer systems, such as systems containing large numbers of microprocessors. A b-network is a network of 2 × 2 crossbar switches called b-elements. This paper presents an analysis of the fault tolerance of b-networks intended for multicomputer applications. A fault model is used which allows b-elements to be stuck in either of their two normal states. A new connectivity property called dynamic full access (DFA) is introduced which serves as the criterion for fault tolerance. A b-network is said to have the DFA property if each of its inputs can be connected to any of its outputs in a finite number of passes through the network. A fault is called critical if it destroys the DFA property. Two graph-theoretical characterizations of the critical faults of a b-network are presented. It is shown that there is a one-to-one correspondence between minimal critical faults and the cutsets of the circuit adjacency graphs derived from the b-network. It is further shown that a fault is critical if and only if it is incompatible with all Eulerian circuits associated with the b-network. Some applications of the theory are discussed.

Journal ArticleDOI
Agarwal1, Masson
TL;DR: The basis of this approach is the development of a generic perspective to multiple faults which uses a representation of such faults called an L-expression which leads to a technique for obtaining the greatest lower bound on the multiple fault coverage capability of an SFDTS by means of a simple table look-up process.
Abstract: Given any combinational, internal fan-out-free network and any complete single fault detection test set (SFDTS) for the network, we consider in this paper the problem of determining the minimal extent to which that SFDTS will cover multiple faults in the network. The basis of our approach is the development of a generic perspective to multiple faults which uses a representation of such faults called an L-expression. This perspective leads to a technique for obtaining the greatest lower bound on the multiple fault coverage capability of an SFDTS by means of a simple table look-up process. In addition to generalizing previously known results regarding multiple fault coverage, two particularly interesting results obtained from this approach are as follows: 1) On the average, every SFDTS for an internal fan-out-free network covers 92 percent of all multiple faults of sizes 8 and less. 2) On the average, every SFDTS for an internal fan-out-free network covers at least 46.1 percent of all multiple faults.

Journal ArticleDOI
TL;DR: It is shown that every function has a TFLAONE network, that is, a realization where all equivalence classes can be identified by inspection, containing at most one control point or extra input.
Abstract: The design of combinational logic networks is considered in which equivalent or indistinguishable stuck-type faults are confined to a small region of the network. A general type of fault equivalence called S-equivalence is introduced, which defines fault equivalence with respect to an arbitrary set of modules S. A network N is called totally fault locatable with respect to module set S, denoted TFLS, if all specified faults in N are S-equivalent. Some general structural properties of TFLS networks are derived. The problem of designing TFLS networks is investigated for S = {AND, OR, NAND, NOR, NOT} denoted AON, and S = {AON, EXCLUSIVE- OR} denoted AONE. All equivalent fault classes in TFLAON and TFLAONE networks can be identified by inspection. It is shown that every function has a TFLAONE network, that is, a realization where all equivalence classes can be identified by inspection, containing at most one control point or extra input. A method for constructing a TFLAONE realization of an arbitrary function is presented using at most one control point.

Patent
30 May 1980
TL;DR: In this article, a fault cause tree is used to analyze the cause of a fault in a fault detection system and the change of data before the fault is detected in the occurrence of the fault.
Abstract: PURPOSE:To treat a fault effectively while relieving an operator from the load of investigating the cause, by obtaining information effective to the investigation on the cause of the fault from the change of data before the fault is detected in the occurrence of the fault. CONSTITUTION:Data of each plant up to the detection of a fault by a fault detector 3 is stored previously as a fault cause tree 10, and a data change table 9 containing the tree 10 and the change of data before the fault is detected, and a secular value table 8 recording data in the detection of the fault are used to analyze the cause of the fault. Then, a fault cause deciding device 6 analyzes the cause of the fault from the tree 10 and the result of it is displayed 7. Here, the tree is displayed to display the change and path of the plant data understandably. Since the time when the data changed is also stored in the table 9, it is displayed simultaneously. Consequently, a plant fault is treated rapidly and adequately.

Journal ArticleDOI
TL;DR: The types of event/fault information required are reviewed and the techniques of providing the information are discussed with special reference to two types of model, functional equation models and mini-fault trees.

Journal ArticleDOI
TL;DR: In this paper, a method of locating a single fault in a linear analogue system by determining the consistency of the inaccessible nodal voltage vectors is proposed, which does not require the assumption of an invariable sensitivity matrix, and can thus be applied to catastrophe faults as well.
Abstract: A method of locating a single fault in a linear analogue system by determining the consistency of the inaccessible nodal voltage vectors is proposed. It does not require the assumption of an invariable sensitivity matrix, and can thus be applied to catastrophe faults as well.

Patent
14 Oct 1980
TL;DR: In this article, the authors propose a self-verifying chip, which consists of a data processing chain and a plurality of fault detecting circuits coupled to the chain, and the output of the fault detectors are applied to a system fault generator monitoring the occurrence of faults.
Abstract: VLSI chips contain a very high density of logic elements and have only a limited number of pin connections making complete testing by conventional means impracticable. The invention provides a self-verifying chip. The chip includes a data processing chain (10) and a plurality of fault detecting circuits (13,14,15) coupled to the data processing chain. A plurality of internal stimulus generators (18,19,20) generate test signal patterns in response to a supervisory control (21) which are applied to intermediate points of the data processing chain. Outputs from the fault detecting circuits (13,14,15) are applied to an error status generator (16) which provides error signals indicating fault conditions at various points of the data processing chain. Fault detecting circuits (18A.21A) may also monitor the internal stimulus generators and the supervisory control means. The devices of the data processing chain may normally operate in a parallel-load mode, but may be loaded with the test signal patterns in serial mode. The chip may include duplicate functional or complementary logic for the data processing chain, and the fault detecting circuits may be arranged to check the operation of the two logic chains against each other. A number of chips according to the invention may be mounted on a card, with a card fault detector receiving the outputs of the error status generators of the chips and providing an output indicating the faults detected in the chips and in the card wiring, and, in turn, in a complete system the outputs of the card fault detectors may be applied to a system fault generator monitoring the occurrence of faults in the whole system.

Proceedings ArticleDOI
23 Jun 1980
TL;DR: Methods for generalized deductive fault simulation of digital networks are described by introducing the notion of unknown fault list, and the propagation algorithm through gates modelized with rise and fall times are simplified with the same accuracy.
Abstract: In this paper, the authors describe methods for generalized deductive fault simulation of digital networks. By introducing the notion of unknown fault list, the propagation algorithm through gates modelized with rise and fall times are simplified with the same accuracy.

Patent
23 Apr 1980
TL;DR: In this article, the authors proposed to reduce the number of signal lines by assigning a signal line to each device when a fault of a certain device is informed to each other among plural devices and then sharing the signal line as a fault information line from the relevant device to another one and vice versa.
Abstract: PURPOSE:To reduce the number of signal lines, by allotting a signal line to each device when a fault of a certain device is informed to each other among plural devices and then sharing the signal line as a fault information line from the relevant device to another one and vice versa. CONSTITUTION:The processors 1-4 are connected in a multiplex way via the signal lines A-D provided as many as the processors. A signal line is allotted to each processor to be used as a fault line which is used in common when the fault is informed from a relevant processor to another one and vice versa. Now in case the processor 1 has a fault, the output of the fault detecting circuit 15 changes from ''1'' to ''0'' to set the correspondence bit of the fault display register 16 at ''1''. At the same time, the bits of the registers 26-46 of processors 2-4 that cprrespond to the processor 1 are set at ''1'' through the signal line A. Each of processors 2-4 reads the contents of registers 26-46 to identify the fault of processor 1. Thus the number of the fault information lines is reduced among plural devices (processors).

Proceedings ArticleDOI
Samiha Mourad1
23 Jun 1980
TL;DR: A hierarchical approach to the detection of the critical faults of a digital board, i.e., those most likely to occur, is described, which introduces a new definition of fault coverage and allows for continual incorporation of field data, thus improving the estimation of the failure probabilities.
Abstract: This paper describes a hierarchical approach to the detection of the critical faults of a digital board, i.e., those most likely to occur. The failure probabilities of the nodes of a board are estimated and used as weights in selecting the nodes for fault detection. The study has indicated both a saving in pattern generation and a higher fault detection per pattern. This approach introduces a new definition of fault coverage. The approach is also applicable to analog circuits. In addition, it allows for continual incorporation of field data, thus improving the estimation of the failure probabilities.

Proceedings ArticleDOI
23 Jun 1980
TL;DR: The design and implementation of a high level fault insertion mechanism for the Instruction Set Processor Specification (ISPS) simulator is described and incorporated as a standard feature in the latest release of the ISPS simulator.
Abstract: Fault tolerance is an important attribute of most computer systems, and to be effective it must be an explicit objective from the beginning of the design process. Inserting faults into a simulation of the machine and observing its behavior is a thorough and economical technique for evaluating prospective fault detection, diagnosis, recovery, and repair mechanisms. As systems become larger due to rising semiconductor integration, the expense of these fault simulations increasingly necessitates that they be performed at higher levels of abstraction (such as the register transfer level) rather than lower (such as the gate level). This can achieve major cost savings without significantly compromising fault coverage. This paper describes the design and implementation of a high level fault insertion mechanism for the Instruction Set Processor Specification (ISPS) simulator. The ISPS simulator was chosen because it is an interactive, high level simulator which is capable, mature, and widely used and accepted. The faults which can be simulated include hard and transient, deterministic and probabilistic, stuck-at and bridged, data, control, and operation types. These facilities have been implemented and demonstrated to be sound in both concept and implementation. They have been incorporated as a standard feature in the latest release of the ISPS simulator.

Journal ArticleDOI
Coy1
TL;DR: It is shown that the algorithms by Bossen and Hong and the algorithm by Yang and Yau may generate test sets with an exponential number of tests (relative to the number of inputs) where a linear number of Tests is sufficient for a complete multiple fault detection test set.
Abstract: Poage has constructed a complex fault detection algorithm which generates a complete and minimal test set of all multiple stuck-at faults of a given combinational network. Several authors have derived from his method fast and simple multiple fault detection algorithms, which are claimed to generate complete test sets with a "near-minimal" or "near-optimal" number of tests. We show that the algorithms by Bossen and Hong and the algorithm by Yang and Yau may generate test sets with an exponential number of tests (relative to the number of inputs) where a linear number of tests is sufficient for a complete multiple fault detection test set.

Patent
30 Oct 1980
TL;DR: In this paper, the authors proposed a tool fault detection and monitoring system based on the working information of a tool and the data of a machine tool, based on this tool data, the tool fault discrimination data is produced and then compared with the working data givin from the machine tool.
Abstract: PURPOSE:To perform the monitor for a fault of a tool without giving no modification to a machine, by installing a transmission circuit to a numerical controller to transmit the working information to a fault monitor device with each block. CONSTITUTION:An arithmetic executing part 42 transmits the working information of each block to a fault monitor device 6 via a transmission circuit 43. The device 6 consists of a reception circuit 61, a received data storage circuit 62, a block contents decoder 63, a tool setting circuit 64 and a tool fault detection circuit 65. Thus the device decodes the working information of a block and discriminates the selected tool to set the data of the tool which is actually used by the execution end signal of block which is given from a numerical controller 4. Based on this tool data, the tool fault discrimination data is produced and then compared with the working data givin from a machine tool 5 of detect the presence or absence of a tool fault.

Journal ArticleDOI
TL;DR: In this paper, a method is developed for obtaining a highly compressed fault table for two-level combinational circuits, where a set of operations is defined through which the minimal test set for detecting stuck-at faults is obtained from the compressed fault tables.
Abstract: A method is developed for obtaining a highly compressed fault table for two-level combinational circuits. A set of operations is defined through which the minimal test set for detecting stuck-at faults is obtained from the compressed fault table. The method is equally suitable for sum of products form or product of sums form realization of logic functions and generates the test set directly from the algebraic expression of the logic function.