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Showing papers on "Stuck-at fault published in 1982"


Journal ArticleDOI
Cristian1
TL;DR: A unified point of view on programmed exception handling and default exception handling based on automatic backward recovery based onautomatic backward recovery is constructed, finding a class of faults for which default exception Handling can provide effective fault tolerance.
Abstract: Some basic concepts underlying the issue of fault-tolerant software design are investigated. Relying on these concepts, a unified point of view on programmed exception handling and default exception handling based on automatic backward recovery is constructed. The cause–effect relationship between software design faults and failure occurrences is explored and a class of faults for which default exception handling can provide effective fault tolerance is characterized. It is also shown that there exists a second class of design faults which cannot be tolerated by using default exception handling. The role that software verification methods can play in avoiding the production of such faults is discussed.

207 citations



Journal ArticleDOI
TL;DR: In this article, a microcomputer-based prototype relay was constructed and installed on a typical utility feeder to detect most staged faults while not indicating a false trip during a three month demonstration.
Abstract: This paper describes work performed by Texas A&M University on the detection of high impedance faults on distribution primary conductors. Some grounded distribution primary conductors may exhibit a very low fault current such that they may not be cleared by over-current protection. These faults may persist indefinitely, possibly causing a fire hazard or a hazard to humans by contact with an energized line. The paper begins with an examination of the high impedance fault problem from the perspective of system protection. The fault detection theory is presented next. The system utilizes a fault-generated increase in the 2-10 kHz component of feeder current for fault detection. EPRI funding enabled the verification and demonstration of this fault detection concept. Measurements were made on several faulted and unfaulted feeders to develop a representative data base of signals to which a relay would be subject. Analysis of these data provided a time and frequency domain signature of these faults. A microcomputer-based prototype relay was constructed and installed on a typical utility feeder. It successfully detected most staged faults while not indicating a false trip during a three month demonstration.

153 citations


Journal ArticleDOI
TL;DR: A technique is described for evaluating the effectiveness of production tests for large scale integrated (LSI) circuit chips based on a model for the distribution of faults on a chip, which implicitly takes into account such variables as fault simulator characteristics, the feature size, and the manufacturing environment.
Abstract: A technique is described for evaluating the effectiveness of production tests for large scale integrated (LSI) circuit chips. It is based on a model for the distribution of faults on a chip. The model requires two parameters, the average number (n/SUB 0/) of faults on a faulty chip and the yield (y) of good chips. It is assumed that the yield either is known or can be calculated from the available formulas. The other parameter, n/SUB 0/, is determined from an experimental procedure. Once the model is fully characterized, it allows calculation of the field reject rate as a function of the fault coverage. The technique implicitly takes into account such variables as fault simulator characteristics, the feature size, and the manufacturing environment. An actual LSI circuit is used as an example.

111 citations



Journal ArticleDOI
TL;DR: In this article, a unified approach for the solution of all types of short-circuit problems is presented, which is particularly useful for system-wide studies, in which specified fault conditions at a set of specified fault locations are analyzed sequentially, on large systems.
Abstract: This paper reports on the development of a unified approach for the solution of all types of short circuit problems. The basic approach is to consider a fault condition -- a fault type or combination of fault types and associated line outages -- as modifications to the parameters of the branches of the prefault network. An extension, referred to as the two-step compensation method, of the conventional compensation scheme was developed to account for the balanced and unbalanced nature of-the modifications that networks undergo when faulted. The computationally efficient solution scheme was derived by using a decomposition of the modifications according to their balanced and unbalanced nature and exploiting the structural properties of the short circuit problem, notably sparsity. The solution approach is particularly useful for system-wide studies, in which specified fault conditions at a set of specified fault locations are analyzed sequentially, on large systems. A noteworthy feature of the proposed methodology is the natural manner in which mutuals are handled. Results of the application of this approach to investigate a variety of fault conditions on several systems, including a 2278 bus network, are presented.

44 citations


Journal ArticleDOI
TL;DR: Band faults can be used to create a fault dictionary that is supposed to isolate single element catastrophic faults, and when applied to several example linear circuits nonetheless has yielded promising results.
Abstract: "Band faults," the approximate movements of nominal worstcase boundaries with catastropic faults, are much more efficiently computed than the "fault bands" that they approximate. Derived from a simulation before test, band faults can be used to create a fault dictionary that is supposed to isolate single element catastrophic faults. By no means general, the approach when applied to several example linear circuits nonetheless has yielded promising results.

39 citations


Proceedings ArticleDOI
01 Jan 1982
TL;DR: It is shown that such a test set can be derived using a set of simple, easily implementable algorithms and be derived from the product term specification of the PLA.
Abstract: The problem of fault detection and test generation for programmable logic arrays (PLAs) is investigated. The effect of actual physical failures is viewed in terms of the logical changes of the product terms (growth, shrinkage, appearance and disappearance) constituting the PLA. Methods to generate a minimal single fault detection test set (T /sub S/) from the product term specification of the PLA, are presented. It is shown that such a test set can be derived using a set of simple, easily implementable algorithms. Methods to augment Ts in order to obtain a multiple fault detection test set (T /sub M/) are also presented.

38 citations


Journal ArticleDOI
Abramovici1, Breuer
TL;DR: The main tool of the approach is the Deduction Algorithm, which deduces internal values in the circuit under test based upon the test results that are used for fault diagnosis, which encompasses both fault detection and location.
Abstract: In this paper we present a new approach to fault diagnosis in sequential circuits based on an effect–cause analysis. This represents an extension of our previous work dealing with combinational circuits [1]. The main tool of our approach is the Deduction Algorithm, which deduces internal values in the circuit under test based upon the test results. The deduced values are used for fault diagnosis, which encompasses both fault detection and location.

31 citations


Patent
13 May 1982
Abstract: In a triplex redundant digital control system, one of three computer units is selected for controlling a digital flight control system by using fault scoring and selection logic circuitry that responds to discrete signals produced by the computer units that represent both self-test and cross-test information on the health of the three available units. The self-test and cross-test discrete information signals are received and processed by the selection logic circuit in accordance with a fault-scoring scheme in which the self-test scores are accorded different and, in particular, greater weight than the cross-test scores and a computer unit exhibiting the lowest combined self- and cross-test fault score is selected as the computer in control. The circuitry also includes memory devices for storing the fault scores associated with previous fault conditions so that a previously unfailed computer unit is selected over a previously failed but currently healthy computer. The memory devices are cleared whenever all three computer modules have scored a fault condition of equal weight such that transient failures do not cause permanent disablement of a computer unit, rather the temporarily faulty unit is allowed to recover and to be brought back on line if needed. To minimize switching, the selection logic causes a new selection only if a computer unit with a lower fault score is available. For simplicity and reliability, the fault scoring and selection logic functions of the circuitry are performed by read-only memories (ROMs) and the memory function is implemented by resettable latches.

30 citations


Journal ArticleDOI
El-Ziq1, Su
TL;DR: This two-part series discusses the testing of computer algorithms for designing diagnosable metal oxide semiconductor networks with and without fan-in, fan-out constraints.
Abstract: The increasing difficulties in testing large logic networks have generated the need for designing logic networks for testability. Computer algorithms for designing diagnosable metal oxide semiconductor (MOS) networks with and without fan-in, fan-out constraints were described in previous papers by the authors. In this two-part series, we discuss the testing of these designed networks.

Proceedings ArticleDOI
01 Jan 1982
TL;DR: A new approach to test pattern generation which is particularly suitable for self-test is described, and all irredundant multiple as well as single stuck faults are detected.
Abstract: A new approach to test pattern generation which is particularly suitable for self-test is described. Required computation time is much less than for present-day automatic test pattern generation (ATPG) programs. Fault simulation is not required. More patterns may be obtained than from standard ATPG programs. However, fault coverage is much higher - all irredundant multiple as well as single stuck faults are detected. Test length is easily controlled. The test patterns are easily generated algorithmically either by program or hardware.

Proceedings ArticleDOI
01 Jan 1982
TL;DR: It is shown that many fault types, including stuck-line faults, short circuits, open circuits, and delay faults can be modeled in a uniform and efficient manner in a fault simulation approach based on CSA theory.
Abstract: Some deficiencies of existing simulators in the context of VLSI design and testing are considered. A fault simulation approach based on CSA (connector-switch-attenuator) theory is defined which overcomes many of these deficiencies. The CSA circuit elements and logic values needed to model combinational circuits are described and applied to the analysis of various types of MOS circuits. A charge-storage element called a well is introduced to simulate sequential behavior. It is shown that many fault types, including stuck-line faults, short circuits, open circuits, and delay faults can be modeled in a uniform and efficient manner.

Journal ArticleDOI
Abramovici1
TL;DR: This work extends the effect–cause analysis method to circuits consisting of interconnected modules that are assumed to be internal fault-free, and introduces a hierarchical approach that repeats the analysis every time with a suspected module replaced by its gate model, while the rest of the circuit remains modeled at the module level.
Abstract: We present several extensions of the effect–cause analysis method [1] for fault diagnosis in combinational circuits. First, we extend the analysis to circuits consisting of interconnected modules that are assumed to be internal fault-free. To handle the situation in which the obtained response is incompatible with a fault domain restricted to the I/O pins of modules, we introduce a hierarchical approach that repeats the analysis, every time with a suspected module replaced by its gate model, while the rest of the circuit remains modeled at the module level.

Journal ArticleDOI
TL;DR: In this paper, the authors present an analysis of the effect of three-phase short-circuit short circuit current on the performance of inductive motors in a faulted bus or downstream buses.
Abstract: One of the major factors to be considered in selecting the ratings of electrical equipment (circuit breakers, bus bar bracing, etc.) is the level of three-phase short circuit current available at the equipment location in the system. The total three-phase short circuit current at a faulted point includes both the currents from the power source (such as electric utility company or in-plant generators) and contribution from electrical motors in the system. Presently, the calculation of three-phase fault current in a system is based on the method outlined in IEEE Standard 141-1976 in which the calculation of motor contribution within the system is defined. It will be pointed out that during a three-phase fault, only motors directly connected to the faulted bus or downstream buses will contribute fully to the fault. Other induction motors (with transformers connected between the motors and the fault) may or may not contribute current to the fault point. These motors will continue to receive power from the supply and act as motors. Therefore lower fault current values will be the result. This finding will have a significant bearing on borderline equipment selection with consequent savings in equipment cost. The conclusion is drawn that the calculated short circuit current based on IEEE Standard 141-1976, is higher than the actual value. This leads to unnecessarily high fuse and breaker interrupting ratings, bus bracing, etc. Computer studies and an analysis of this phenomenon are presented.

Journal ArticleDOI
TL;DR: The predominant existing software specification and implementation techniques for sequential control are not adequate for the creation of correct software of the complexity required for redundant systems.
Abstract: Redundant control systems require more than a single redundant construct to serve the six basic functions of fault tolerance: test, detection, diagnosis, masking, reconfiguration, and recovery. Software usually constitutes or supports one or more such constructs. Additionally, software must be correct, since it is seldom, if ever, protected by redundancy. A redundant sequential control system requires intricate software constructs. The predominant existing software specification and implementation techniques for sequential control are not adequate for the creation of correct software of the complexity required for redundant systems. This complexity is illustrated by an example.

Proceedings Article
01 Jan 1982
TL;DR: This work presents the core part of the AMPE which supports multiple theories and a fast context switching among theories in the MetaProlog system and describes how to compute proofs, how to shrink the search space of a goal using partially instantiated proofs, and how to represent other control knowledge in a WAM-based system.
Abstract: METAPROLOG ENGINE ILYAS CICEKLI. A compiler-based meta-level system for MetaProlog language is presented. Since MetaProlog is a meta-level extension of Prolog, the Warren Abstract Machine (WAM) is extended to get an eecient implementation of meta-level facilities and this extension is called the Abstract MetaProlog Engine (AMPE). Since theories and proofs are main meta-level objects in MetaProlog, we discuss their representations and implementations in detail. First, we describe how to eeciently represent theories and derivability relation. At the same time, we present the core part of the AMPE which supports multiple theories and a fast context switching among theories in the MetaProlog system. Then, we describe how to compute proofs, how t o shrink the search space of a goal using partially instantiated proofs, and how to represent other control knowledge in a WAM-based system. In addition to computing proofs which are just success branches of search trees, fail branches can also be computed and used in the reasoning process.

Journal ArticleDOI
TL;DR: In this article, an alternative to existing fault locating procedures based upon the concept of the adjoint circuit and the recently derived theorem on the maximum number of independent simulations in N-port circuits is presented.
Abstract: Fault location in electric power transmission or distribution systems is essential to the maintenance of reliable and continuous service. As a result, increased effort is being focused on fault locating procedures in distribution systems such that faults may be automatically isolated and unfaulted feeders restored to service in a short time. Presented is an^ alternative to existing fault locating procedures based upon the concept of the adjoint circuit and the recently derived theorem on the maximum number of independent simulations in N-port circuits. The theoretical approach is described for open circuit, short circuit, and mixed open and short circuit faults, followed by a numerical example applied to fault location in radial distribution feeders.

Patent
09 Mar 1982
TL;DR: In this paper, a method of determining the location of a fault in a complex industrial installation is described, where information corresponding to each component of the installation and the correct operating parameters of each component part is stored in a memory and a computer is used to produce on a visual display unit schematic diagrams and indicates tests which are to be carried out to locate where the fault lies.
Abstract: In a complex industrial installation, it is usually very difficult to locate the position of a fault when one occurs. In a method of determining the location of a fault, information corresponding to each component part of the installation and the correct operating parameters of each component part is stored in a memory and a computer is used to produce on a visual display unit schematic diagrams of at least part of the installation and indicates tests which are to be carried out, the operator causes the test results to be supplied to the computer and, after comparing the results with the stored information, the computer indicates on the display either where the fault lies or further schematic diagrams and tests which are to be carried out to locate where the fault lies. Apparatus for carrying out the fault location is also described.

01 Jan 1982
TL;DR: Containment set techniques are applied to 8085 microprocessor controllers so as to transform a typical control system into a slightly modified version, shown to be crashproof: after the departure of the intermittent/transient fault, return to one proper control algorithm is assured, assuming no permanent faults occur.
Abstract: Containment set techniques are applied to 8085 microprocessor controllers so as to transform a typical control system into a slightly modified version, shown to be crashproof: after the departure of the intermittent/transient fault, return to one proper control algorithm is assured, assuming no permanent faults occur.

Journal ArticleDOI
Glaser1, Masson1
TL;DR: A new approach is taken which combines faults, hardware, and software together into one overall model which supports a new method, based on the novel concept of a containment set, for realizing transient fault tolerance without massive redundancy.
Abstract: Fault analysis of digital systems is highly dependent upon the fault model employed. Much previous work utilizes fault models known to contain inaccuracies in order to permit mathematically tractable analysis. In this correspondence a new approach is taken which combines faults, hardware, and software together into one overall model. This new model is shown to be useful for the consideration of intermittent/transient faults. It supports a new method, based on the novel concept of a containment set, for realizing transient fault tolerance without massive redundancy. It also allows for a new approach to system fault tolerance evaluation and validation which uses a transition matrix which is defined in terms of the containment set.

Journal ArticleDOI
TL;DR: In this paper, the authors consider that a fault is actually a change in relationship between some variables, and they use on-line identification and thus observe model parameters to detect faults.

Patent
24 Mar 1982
Abstract: In a method of locating the position of a fault (F) occurring in an electric power transmission system an indication of the position of the fault with respect to a monitoring point (A) is obtained from the time taken (TRW2-TFW1) for a transient component of fault signal to travel from the monitoring point to the fault and back to the monitoring point after reflection at the fault. Apparatus for carrying out the method is also described.

DOI
W.R. Moore1
01 Nov 1982
TL;DR: It is shown that faults can be corrected efficiently by bypassing the faulty column of the array, and a novel technique is described which detects processor faults with a very modest increase in circuitry.
Abstract: The paper addresses the problems of detecting and correcting faults that may occur in arrays of processors used for image processing. The variety of useful hardware and software solutions is reviewed. It is shown that faults can be corrected efficiently by bypassing the faulty column of the array, and a novel technique is described which detects processor faults with a very modest increase in circuitry. The addition of a parity check on the memory is sufficient to give an effective and efficient detection and correction of all permanent and many transient faults. Additionally, the use of a full parity processor increases the proportion of transient faults detected.

01 Jan 1982
TL;DR: In this article, it was shown that in case of single redundancy in the network, the stuck-Open fault on the redundant line cannot be detected, when there is a one-one correspondence between the conditions for stuck-at fault and stuck-open fault detectability.
Abstract: Recently it has been found that a class of failure related to a particular technology (CMOS) cannot be modelled as the conventional stuck-at fault model. These failures change the combinational behavior of CMOS logic gates into a sequential one. Such a failure is modelled as a fault, called the Stuck-Open fault (SOP). The object of this paper is to develop a procedure to detect single SOPs in combinational circuits. It is shown, that in general, tests generated for stuck-at faults when applied in a particular sequence will detect all single SOP faults. In case of single redundancy in the network, the SOP fault on the redundant line cannot be detected. When there is reconvergent fan-out in the network, there is a one-one correspondence between the conditions for stuck-at fault and stuck-open fault detectability.

Proceedings ArticleDOI
14 Jun 1982
TL;DR: A procedure for fault diagnosability in the design of instrumentation is described and the circumstances under which complete diagnosis is possible are indicated, namely that the model parameters are uniquely (globally) identifiable.
Abstract: If the fault modes of a process instrumentation system can be related to the coefficients in the mathematical model of the system, then isolation of causes of system malfunction may be possible. We describe a procedure for fault diagnosability in the design of instrumentation and indicate the circumstances under which complete diagnosis is possible, namely that the model parameters are uniquely (globally) identifiable. An example of a feedback control system is used to illustrate the basic concepts.