Showing papers on "Stuck-at fault published in 1983"

Functional Testing of Semiconductor Random Access Memories

Abstract: This paper presents an overview of the problem of testing semiconductor random access memories (RAMs). An important aspect of this test procedure is the detection of permanent faults that cause the memory to function incorrectly. Functional-level fault models are very useful for describing a wide variety of RAM faults. Several fault models are &scussed throughout the paper, including the stuck-at-0/1 faults, coupled-cell faults, and single-cell pattern-sensitive faults. Test procedures for these fault models are presented and their fault coverage and execution times are discussed. The paper is intended for the general computer scmnce audience and presupposes no background in the hardware testing area.

Test Generation for MOS Circuits Using D-Algorithm

Abstract: An application of the D-algorithm in generating tests for MOS circuit faults is described. The MOS circuits considered are combinational and acyclic but may contain transmission gates and buses. Tests are generated for both, the stuck type faults and the transistor faults (open and short). A logic model is derived for the MOS circuits. In addition to the conventional logic gates, a new type of modeling block is used to represent the "memory" state caused by the "open" transistors. Every fault, whether a stuck type fault or a transistor fault, is represented in the model as a stuck fault at a certain gate input. For generating tests, however, the D-algorithm needs modification. The singular cover and the D-cubes for the new gate include some memory states. To handle the memory state, an initialization procedure has been added to the consistency part of the D-algorithm. The procedure of modeling and test generation is finally extended to transmission gates and buses.

Accurate fault impedance locating algorithm

Abstract: Fault resistances affect the accuracy of short-circuit location, when distance to the fault is determined by means of measuring reactance at one end of the transmission line. This is because the current which flows through the fault resistance is slightly shifted in phase with respect to the current measured at the end of the line in question, due to the effect of the prefault load current. As a result, the fault resistance is recognised as an apparent impedance with both resistive and reactive components. The latter produces an error in the fault location, as it affects the measured reactance. The paper presents a simple algorithm which compensates for the error, and makes it possible to locate short circuits accurately; even if fault resistances are comparatively high.

Node-fault diagnosis and a design of testability

Abstract: A concept of k -node-fault testability is introduced. A sufficient and almost necessary condition for testability as well as the test procedure is presented. This condition is further evolved to a necessary and almost sufficient topological condition for testability. A unique feature of this condition is that it depends only on the graph of the circuit, not on the element values. Based on this condition, a design of testability can be established.

On Fault Detection in CMOS Logic Networks

Abstract: This paper considers the problem of detecting faults in CMOS combinational networks. Effects of open and short faults in CMOS networks are analyzed. It is shown that the test sequence must be properly organized if the effects of all open faults are to be observable at the network output terminal. A simple and efficient heuristic method for organizing the test sequence to detect all single faults in a CMOS network is suggested.

Analog multifrequency fault diagnosis

Abstract: This paper develops the multifrequency fault diagnosis problem in the context of a tableau approach based on the use of the Component Connection Model. This method avoids the computation of the composite system transfer function matrix. The resulting fault diagnosis equations have a regular structure with fixed polynomial order (often quadratic) which is exploited in the solution process. The development includes a test for diagnosability as well as a set of bounds on the number of test frequencies necessary to conduct a diagnosis. An iteration scheme to solve the fault diagnosis equations is proposed and is shown to be locally convergent. A sample diagnosis problem and solution concludes the paper.

Distributed fault isolation and recovery system and method

Abstract: There is disclosed a system and a method for isolating faults and recovering a distributed system of the type including a plurality of modules to optimized operation. At least some of the modules are active fault recovery modules and include fault detecting means for initializing a fault check routine and sensing faults within the distributed system. Voting means are associated with each active module for placing a vote during each fault check routine in response to a detected fault. Collective vote determining means record the votes of the active modules after each fault check routine and recovery sequence initializing means initializes a fault isolation and recovery sequence in response to a given number of consecutive collective votes exceeding a predetermined value.

Generalized fault reporting system

Abstract: The present disclosure describes a system for handling detected error signals, providing the circuit elements for processing fault reports and implementing automatic fault isolation. More specifically, the system develops a fault report for each component based upon error signals derived therefrom. Changes in the fault report are detected and selector circuits are actuated to automatically isolate the fault to the particular component or components, or to reset the system in response to previous fault correction. The present system is advantageous in that it is independent of the equipment technology and applies to all design levels, from the unit itself to the individual components of which it is comprised.

Testing CMOS: a challenge

Abstract: CMOS technology poses a multi-faceted challenge in testing. Since 1978, researchers have recognized that the stuck-open transistor fault requires special test procedures. Other faults, such as transistors stuck-on or shorted, likewise involve complications. However, these fault types have received comparatively little attention. This article reviews results on the testing of stuck-open faults, develops procedures for testing stuck-on faults, and discusses problems in testing for short faults. Through this analysis, the authors arrive at recommendations for investigating `design for CMOS testability'.

Relay for pilot protection of electrical power lines

Abstract: New logic circuitry for a directional comparison blocking protective relay scheme. A forward-reaching and a reverse-reaching protective relay located at the local and remote terminals of a protected line segment determine whether a fault is internal or external to the protected line segment. To carry out this function, the protective relays produce signals representative of fault location and communicate with each other via a communications channel. A fault detector and logic circuitry is provided at each terminal for processing the produced signals to determine the fault location and avoid tripping when the fault character changes. By using fault detectors to determine the existence of a fault, the logic at each terminal for combining the signals is simplified and security against false tripping is improved.

Test-generation system for digital circuits

Abstract: In a system for generating tests for digital circuits, a fault simulator (16) simulates a fault-free version of the circuit and all expected faulty versions of it concurrently, basing its operation on information contained in a data base (12) that contains information about the structure and possible defects of the circuits to be tested. A waveform system (14) carries high-level information regarding the general structure of the test waveform that ultimately is to be derived, such as clock signals, timing constraints, and other restrictions that the designer of the circuit under test has placed on the signals to be applied to it. At each point in this outline waveform at which the system needs to insert input signals, a test generator (18) is called by the waveform system (14) to derive a test vector based on information concerning the layout of the circuit, its possible defects, and its current state, the current state having been communicated to the data base (12) by the fault simulator (16), which determines the states that result from application of a waveform received from the waveform system (14). Even for non-scan-type circuits under test, the test generator derives only one test vector at a time, without searching through sequences of test vectors to find which sequences of test vectors might cause propagation of faults to the output ports of the circuit under test. It nonetheless efficiently derives test waveforms because it chooses among the fault effects of all faulty versions of the circuit concurrently for those effects that are likely candidates for propagation.

Multiport approach to multiple-fault location in analog circuits

Abstract: This paper deals with the multiport method for multiple-fault location in linear analog circuits. A hybrid multiport description of the linear network has been used in the presentation, which generalizes and explains proposals made by Biernacki and Bandler. The problem of consistency of the chosen set of equations used for fault identification is discussed. The restrictions of the method are explained on the basis of network topology.

A review of fault models for lsi/vlsi devices

Abstract: The review paper deals with problems concerning fault modelling for LSI/VLSI devices. Both random and regular logic are considered, and different fault classes are discussed for each, including stuck-at, bridging, functional and time-dependent faults. Specific fault models are then considered for microprocessors, RAMs and PLAs

Fault diagnosing device for sequence machine

Abstract: PURPOSE: To detect assuredly the presence or absence of a fault by storing all normal working states during a cycle of a sequence machine and comparing these working states with a memory every time the working state of the sequence machine varies. CONSTITUTION: The working state of a sequence machine A is fetched to a fetching means B for each change of said working state. While a memory means C stores previously all normal working states during a cycle of the machine A. A comparing means D compares the data of the means C with that of the means B. When the coincidence is obtained from this comparison, it is decided that the machine A is normally working. While a fault is decided when no coincidence of comparison is obtained. Then a fault signal is delivered to detect early the fault. Thus it is possible to detect a fault early by a simple device and to recover the fault in a short time. This improves the working efficiency of a fault diagnosing device. Such a device is suitable used to a lift, conveyor, etc. COPYRIGHT: (C)1984,JPO&Japio

Fault tree data array

Abstract: A fault tree data array converts the logic of a fault tree into software bysing a data base technique. Each array element of a data array contains a decision or termination of the fault tree, and a relative exponential addressing expression provides the data elements with a unique position in the array. The next position in the data array to be examined is calculated by the relative exponential addressing expressions. For unsymmetrical fault trees on additional data array is generated to provide a sequential list of tests to be examined until a fault is found. Then the relative exponential addressing technique is used. The result is a more compact method of storing data in computer memory, hence providing an efficient method for implementing fault trees into software.

A Data Structure for MOS Circuits

Abstract: This paper describes a data structure to represent the driver-load configurations in MOS circuits, which is used universally in the MOTIS simulation environment. In particular, the data structure is used in mixed-mode evaluation including timing, and multiple/unit delay. Other applications include automatic delay calculation, transistor fault modeling, fault collapsing, and fault simulation.

An On-Line Algorithm for the Location of Cross Point Faults in Programmable Logic Arrays

Abstract: An on-line algorithm is developed for the location of single cross point faults in a PLA (FPLA). The main feature of the algorithm is the determination of a fault set corresponding to the response obtained for a failed test. For the apparently small number of faults in this set, all other tests are generated and a fault table is formed. Subsequently, an adaptive procedure is used to diagnose the fault. Functional equivalence test is carried out to determine the actual fault class if the adaptive testing results in a set of faults with identical tests. The large amount of computation time and storage required in the determination, a priori, of all the fault equivalence classes or in the construction of a fault dictionary are not needed here. A brief study of functional equivalence among the cross point faults is also made.

Abstractions for Node Level Passive Fault Detection in Distributed Systems

Abstract: We introduce a scheme for passive node-level fault detection in a distributed system. With each system node associate a low-cost, low-complexity observer which monitors the pattern of incoming and outgoing messages and compares it against an abstracted model of the node's behavior. We develop a fault detection procedure, which is probabilistic because of nondeterminism in the simplified node model. Abstraction reduces model complexity, but renders some errors undetectable by the observer. In the paper we characterize these undetectable errors. Succeeding studies show how to select model abstractions to lower the number of undetectable errors.

Total Stuck-at-Fault Testing by Circuit Transformation

Abstract: We present a new approach to the production testing of VLSI circuits. By using very structured design for testability, we achieve 100% single stuck-at fault coverage with under 20 test vectors and no search. The approach also detects most multiple faults.

A Self-Test Hardwired Control Section

Abstract: A fault detect mechanism is described for hardwired control logic. The mechanism takes advantage of inherent redundancy in the control logic design style which assigns a unique flip-flop to each machine state. The mechanism is capable of detecting all single stuck-at faults, as well as many multiple faults and intermittents within the control section.

Anomalous effect of a stuck-at fault in a combinational logic circuit

Abstract: An example of an irredundant combinational network realizing a Boolean function F 0 is presented which depicts a peculiar phenomenon that even a single stuck-at fault can change the function F 0 to a faulty funetion F f , such that F 0 and F f belong to the same P-equivalence class, i.e., F 0 can be transformed into F f by permuting the input literals. In addition, the reversibility of fault behavior in irredundant networks is also exemplified.

Test circuit for fault current protection circuits

Abstract: Method for testing fault current protection circuits in permanently earthed systems by producing by means of two mutually opposed Zener diodes a constant AC voltage whose magnitude is equal to the given maximum contact voltage which it is permissible to apply to the fault current protection circuits. This AC voltage, corresponding to the RMS value of a sinusoidal voltage, is applied to the resistance of the protective circuit, causing a fault current which, depending on the value of the earth contact resistance, will trip the fault current breaker if the current exceeds the fault current breaker tripping current. In order to limit the energy developed in the circuit a timer element is included which automatically breaks the test voltage as soon as the test has been completed. A safety device against wrong connection is also included.

Breaker Contact Behavior with Rapid Sequential Switching Above Fault Rating

Abstract: This paper is concerned with the behavior of closed circuit breaker contacts of diverse types when subjected to peak fault currents which for one cycle exceed rating by 60 to 100 percent. The problem is crucial to the feasibility of a proposed simplified method of meeting transmission needs for fault current limiting devices [3]. High current tests have been run on components representative of the important transmission class circuit breakers employed in the U.S. A specific application of the proposed fault limiting concept is described.

A fault tolerant MOS-LSI for train controller applications

Abstract: Fault-tolerant design techniques, which have resulted in the development of a fail-safe LSI circuit for train control applications, will be discussed. The design is based on bit-serial, time-sharing and frequency domain operation, as well as a layout method to restrict possible MOS failure modes.

Detector of faulty part

Abstract: PURPOSE:To discriminate easily troubleshooting at failure by storing an input state before and after fault generation to a storage device based on a fault generating signal generated from a preceding priority circuit so as to display the content. CONSTITUTION:A discriminating circuit 3 discriminates whether plural input signals from a system are normal or faulty, the part generated with a fault at first is discriminated by the preceding priority circuit 4 by a discrimination signal to the input signal discriminated as a fault at first and displayed by a priority display device 5. An output of the circuit 3 is inputted normally to a storage device 8 at the same time, stored for a prescribed time, the input state before and after the generation of fault is stored permanently in the device 8 based on the fault generating signal outputted from the circuit 4 when the fault is generated, the output of the device 8 is inputted to the device 5 and a printer 11 so as to display or store the input state before and after generation of fault. Thus, the troubleshooting of the faulty part is made easy.

Pmpa: a fault-tolerant multi-microprocessor system based on autonomous decentralization concept.

Abstract: FM PA, a fault-tolerant multi-microprocessor system based on the autonomous decentralization concept is proposed. Fault tolerance can be attained by a hexagonal array of homogeneous processing units autonomously decentralized using software switching buses. Each homogeneous processing unit, called a cell> has three symmetrical Fault Tolerant Buses. In case of failure, the hexagonalarrayisautonomouslyreconfiguredin order to achieve fault isolation, and alternate routing is done for fault recover y. In order to gain autonomous com municat ion control, messages are sent in a broadcast mode. Using this system, dynamical determined voting logic, termed threshold voting is realized. An experimental system composed of seven M-68000 cells shows that the proposed system works with high reliability.