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Showing papers on "Stuck-at fault published in 1985"


Proceedings Article
01 Jan 1985
TL;DR: A procedure is described which identifies paths which are tested for path faults by a set of patterns, independent of the delays of any individual gate of the network, which is a global delay fault model.
Abstract: Delay testing of combinational logic in a clocked environment is analyzed. A model based upon paths is introduced for delay faults. Any path with a total delay exceeding the clock interval is called a "path fault." This is a global delay fault model because it is associated with an entire path. The more familiar slow-to-rise or slow-to-fall gate delay fault, on the other hand, is a local fault model. A procedure is described which identifies paths which are tested for path faults by a set of patterns. It does not involve delay simulation. The paths so identified are tested for path faults independent of the delays of any individual gate of the network.

762 citations


Journal ArticleDOI
TL;DR: Given the layout of an IC, a fault model and a ranked fault list can be automatically generated which take into account the technology, layout, and process characteristics.
Abstract: Inductive Fault Analysis (IFA) is a systematic Procedure to predict all the faults that are likely to occur in MOS integrated circuit or subcircuit The three major steps of the IFA procedure are: (1) generation of Physical defects using statistical data from the fabrication process; (2) extraction of circuit-level faults caused by these defects; and (3) classification of faults types and ranking of faults based on their likelihood of occurrence Hence, given the layout of an IC, a fault model and a ranked fault list can be automatically generated which take into account the technology, layout, and process characteristics. The IFA procedure is illustrated by its applications to an example circuit. The results from this sample led to some very interesting observations regarding nonclassical faults.

487 citations


Journal ArticleDOI
TL;DR: The various linear-feedback shift register designs for pseudorandom or pseudoexhaustive input test pattern generation and for output response signature analysis are presented.
Abstract: A system that includes self-test features must have facilities for generating test patterns and analyzing the resultant circuit response. This article surveys the structures that are used to implement these self-test functions. The various techniques used to convert the system bistables into test scan paths are discussed. The addition of bistables associated with the I/O bonding pads so that the pads can be accessed via a scan path (external or boundary scan path) is described. Most designs use linear-feedback shift registers for both test pattern generation and response analysis. The various linear-feedback shift register designs for pseudorandom or pseudoexhaustive input test pattern generation and for output response signature analysis are presented.

417 citations


Journal ArticleDOI
TL;DR: In this paper, a microprocessor based fault locator is described, which uses novel compensation techniques to improve accuracy and display the distance to the fault in percent of transmission line length, for facilitating repair and restoration following a permanent fault.
Abstract: A microprocessor based fault locator is described, which uses novel compensation techniques to improve accuracy. It displays the distance to the fault in percent of transmission line length, for facilitating repair and restoration following a permanent fault. Also, it pinpoints weak spots following transient faults.

297 citations


Journal ArticleDOI
TL;DR: Among Stafan's advantages, fault coverage and the undetected fault data obtained for actual circuits are shown to agree within five percent of fault simulator results, yet CPU time and memory demands fall far short of those required in fault simulation.
Abstract: Statistical Fault Analysis, or Stafan, is proposed as an alternative to fault simulation of digital circuits. This method defines Controllabilities and observabilities of circuit nodes as probabilities estimated from signal statistics of fault-free simulation. Special Procedures deal with these quantities at fanout and feedback nodes. The computed probabilities are used to derive unbiased estimates of fault detection probabilities and overall fault coverage for the given set of input vectors. Among Stafan's advantages, fault coverage and the undetected fault data obtained for actual circuits are shown to agree within five percent of fault simulator results, yet CPU time and memory demands fall far short of those required in fault simulation. The Computational complexity added to a fault-free simulator by Stafan grows only linearly with the number of circuit nodes.

151 citations


Journal ArticleDOI
TL;DR: In this article, the authors present the use of several techniques to enhance the capability of the d.c. fault dictionary for diagnosing hard failures (open circuits and short circuits) in non-linear analogue circuits.
Abstract: The d.c. fault dictionary approach has been found very useful for diagnosing hard failures (open circuits and short circuits) in non-linear analogue circuits. In this paper we present the use of several techniques to enhance the capability of the d.c. fault dictionary. These include (1) modelling all non-linearities by piecewise linear characteristics, (2) solving the piecewise linear resistive network by Lemke's complementary pivot algorithm, (3) using multilevel logic operation to compile an integer-code fault dictionary which totally eliminates any post-test calculations. the automatic generation of a fault dictionary for a video amplifier by the use of the computer program HAFDIC is described.

119 citations


Journal ArticleDOI
Abramovici1, Menon
TL;DR: This approach is based on extending fault simulation and test generation for stuck faults to cover bridging faults as well, and shows that adequate bridging fault coverage can be obtained in most cases without using sequences of vectors.
Abstract: In this correspondence we prepent a practical approach to fault simulation and test generation for bridging faults in combinational circuits. Unlike previous work, we consider Unrestricted bridging faults, including those that introduce feedback. Our approach is based on extending fault simulation and test generation for stuck faults to cover bridging faults as well. We consider combinational testing only, and show that adequate bridging fault coverage can be obtained in most cases without using sequences of vectors.

98 citations


Journal ArticleDOI
TL;DR: An NMOS implementation of a new built-in self-test PLA design is presented, which results in significantly better overhead than that of any existing scheme.
Abstract: An NMOS implementation of a new built-in self-test PLA design is presented. The layouts for its additional test circuitry result in appoximately 15-percent overhead for most large PlAS, a significantly better overhead than that of any existing scheme. Both the input test patterns and the output responses, which are compressed intoastring of parity bits, are independent of the functions that the PLA realizes, and the 15-percent overhead includes the storage needed for the fault-free compressed output data. The fault coverage of this approach consists of all single and (1-2 -( 2n + m)) of all multiple stuck, crosspoint, and bridging faults in the original PLA and the additional test circuitry (n and m are the number of input variables and product terms, respectively). The article begins with a short review of existing design schemes.

86 citations


Journal ArticleDOI
Jain1, Agrawal
TL;DR: An application of the D-algorithm in generating tests for MOS circuit faults is described, where every fault, whether a stuck type fault or a transistor fault, is represented as a stuck fault at a certain gate input.
Abstract: An application of the D-algorithm in generating tests for MOS circuit faults is described. The MOS circuits considered are combinational and acyclic but may contain transmission gates and buses. Tests are generated for both the stuck type faults and the transistor faults (open and short). A logic model is derived for the MOS circuits. In addition to the conventional logic gates, a new type of modeling block is used to represent the "memory" state caused by the "open" transistors. Every fault, whether a stuck type fault or a transistor fault, is represented in the model as a stuck fault at a certain gate input. For generating tests, however, the D-algorithm needs modification. The singular cover and the D-cubes for the new gate include some memory states. To handle the memory state, an initialization procedure has been added to the consistency part of the D-algorithm. The procedure of modeling and test generation is finally extended to transmission gates and buses.

65 citations


Journal ArticleDOI
TL;DR: A novel approach to making very large dynamic RAM chips self-testing is presented, based on two main concepts on-chip generation of regular test sequences with very high fault coverage, and concurrent testing of storage-cell arrays to reduce overall testing time.
Abstract: A novel approach to making very large dynamic RAM chips self-testing is presented. It is based on two main concepts on-chip generation of regular test sequences with very high fault coverage, and concurrent testing of storage-cell arrays to reduce overall testing time. The failure modes of a typical 64K RAM employing one-transistor cells are analyzed to identify their test requirements. A comprehensive test generation algorithm that can be implemented with minimal modification to a standard cell layout is derived. The self-checking peripheral circuits necessary to implement this testing algorithm are described, and the self-testing RAM is briefly evaluated.

64 citations


Journal ArticleDOI
TL;DR: This paper presents a necessary and sufficient condition for the existence of a test set, which cannot be invalidated under arbitrary delays, for an AND-OR or OR-AND CMOS realization for any given function.
Abstract: The sequential behavior of CMOS logic circuits in the presence of stuck-open faults requires that an initialization input followed by a test input be applied to detect such a fault. However, a test set based on the assumption that delays through all gates and interconnections are zero, can be invalidated in the presence of arbitrary delays in the circuit. In this paper, we will present a necessary and sufficient condition for the existence of a test set, which cannot be invalidated under arbitrary delays, for an AND-OR or OR-AND CMOS realization for any given function. We will also introduce a Hybrid CMOS realization which, for any given function, is guaranteed to have a valid test set under arbitrary delays.

Proceedings ArticleDOI
01 Jun 1985
TL;DR: Measurements obtained while performing fault simulations of MOS circuits modeled at the switch level obtain a performance level comparable to fault simulators using logic gate models, and indicate that fault simulation times grow as the product of the circuit size and number of patterns.
Abstract: This paper presents measurements obtained while performing fault simulations of MOS circuits modeled at the switch level. In this model the transistor structure of the circuit is represented explicitly as a network of charge storage nodes connected by bidirectional transistor switches. Since the logic model of the simulator closely matches the actual structure of MOS circuits, such faults as stuck-open and closed transistors as well as short and open-circuited wires can be simulated. By using concurrent simulation techniques, we obtain a performance level comparable to fault simulators using logic gate models. Our measurements indicate that fault simulation times grow as the product of the circuit size and number of patterns, assuming the number of faults to be simulated is proportional to the circuit size. However, fault simulation times depend strongly on the rate at which the test patterns detect the faults.

Patent
22 Apr 1985
TL;DR: A ground fault module is designed for ease of assembly within a ground fault circuit breaker as discussed by the authors, which contains the pre-assembled signal processor module, along with the mechanical components required for translating the trip initiating response from the signal processor solenoid to the circuit breaker operating mechanism.
Abstract: A ground fault module is designed for ease of assembly within a ground fault circuit breaker. The module houses the pre-assembled signal processor module, which contains the ground fault circuit interruption logic, along with the mechanical components required for translating the trip initiating response from the signal processor solenoid to the circuit breaker operating mechanism. The ground fault test button and related circuitry are also supported within the ground fault module.

Journal ArticleDOI
TL;DR: An algorithm is introduced which is able to construct fault trees of non-reconfigurating systems, using simple component models that allow bi-directional fault propagation.

Journal ArticleDOI
TL;DR: A new algorithm for functional test generation of VLSI systems based on the reduced fault model using machine symbolic execution, which is appropriate for test generation in top-down Computer-Aided Design process.
Abstract: We present a new algorithm for functional test generation of VLSI systems. This algorithm for functional test generation for each testable register-transfer (RT) level fault defined in our established fault model. The technique developed is appropriate for test generation in top-down Computer-Aided Design process. The development of the algorithm is based on two foundations: the RT-level fault model and symbolic execution technique. A well-defined RT-language for the functional representation of a digital system is described. Based on this language, the RT-level fault modeling and fault collapsing analysis are performed. The fault model is established to lay an analytical foundation for the investigation of faulty behavior among RT-level fault types. The RT-level symbolic execution technique is used to derive test patterns during test generation. Major problem areas are defined and appropriate solutions are presented. The whole test generation process is divided into three stages: preprocess, the S-algorithm, and post-process. "Divide and conquer" principle is used throughout the test generation process for systematic problem solving. The S-algorithm is the heart of the overall algorithm. It performs test pattern generation based on the reduced fault model using machine symbolic execution. This test generation algorithm has been implemented in PASCAL on IBM 370/168.

Patent
Arthur James Edwards1
04 Dec 1985
TL;DR: In this article, three possible types of "faults" may be detected in the ignition system of a vehicle, using simple combinational logic to provide an essentially error-free activation of an indicator (58) when a true fault is present.
Abstract: Three possible types of "faults" may be detected in the ignition system of a vehicle, using simple combinational logic to provide an essentially error-free activation of an indicator (58) when a true fault is present. "Fault" signals which mean non-rotation of the alternator, broken cables or short circuits and the like are distinguished from transient and less significant conditions. The latter conditions are prevented from activating the indicator. A single indicator lamp (58) serves to alert the user to a serious fault requiring service.

Proceedings ArticleDOI
01 Jun 1985
TL;DR: Conclusions are drawn as to the effectiveness of the technique and how amenable it is to automation.
Abstract: Functional fault modeling and simulation for VLSI devices is described(*). A functional fault list is compiled using model perturbation and mapping of circuit defects into functional faults. A set of test vectors is then derived which detects all faults in the functional fault list. This same test vector set is then applied to a gate level model of the device. For the test case analyzed, a very high level of equivalent gate coverage was achieved. Conclusions are drawn as to the effectiveness of the technique and how amenable it is to automation.

Journal ArticleDOI
TL;DR: A method of fault diagnosis of power systems based on a knowledge-based approach that makes use of information on relays and circuit breakers, where the relay sequence is represented by a logical circuit.
Abstract: This paper proposes a method of fault diagnosis of power systems based on a knowledge-based approach. It makes use of information on relays and circuit breakers. The feature of this method is that the relay sequence is represented by a logical circuit. In this circuit the following two relations are represented; a logical relation between inputs and output of a gate and a connective relation between logical gates. These two relations are expressed by production rules in the knowledge base. When the information from relays and circuit breakers is given to the logical circuit, faulty components are pointed out.

Journal ArticleDOI
TL;DR: In this paper, a fault detection and fault diagnosis of technical processe becomes more important in the course of progressive automation and computer based fault supervision methods are developed which allow the early detection and localization of process faults during normal operation.

Journal ArticleDOI
TL;DR: The method enables us to determine the coverage ratio, which is defined as the ratio of the number of multiple contact faults detected by a single fault test Tc to the total number of all multiple faults, which shows that the multiple fault coverage ratio of Tc drops with an increasing size of faults, and most unexpectedly, the ratio increases with anincreasing number of rows.
Abstract: The increasing number of applications of programmable logic arrays (PLA's) has evoked the development of test generation methods for these circuits. There are known methods for complete single contact fault detection test set generation. These test sets fail to detect all multiple faults in a PLA due to the phenomenon of masking. In this correspondence, we present a method to quantitively predict the multiple fault coverage capability of a single fault detection test set in a PLA. The method enables us to determine the coverage ratio, which is defined as the ratio of the number of multiple contact faults detected by a single fault test T c to the total number of all multiple faults. It is shown that the multiple fault coverage ratio of T c drops with an increasing size of faults, and most unexpectedly, the ratio increases with an increasing number of rows. The number of crosspoints in one product line has very little influence on the ratio.

Journal ArticleDOI
Shigehiro Funatsu1, Masato Kawai1
TL;DR: A new test-generation system (FUTURE) for large digital circuits (more than 10K gates) is based on a nine-valued FAN algorithm that can be a powerful CAD tool and effectively generate test patterns for large sequential circuits with Scan Path.
Abstract: A new test-generation system (FUTURE) for large digital circuits (more than 10K gates) is based on a nine-valued FAN algorithm. Fault simulation adopts a concurrent simulation adopts a concurrent simulation technique. The system consists of four major modules: fault modeling, random pattern generation, algorithmic pattern generation, and fault simulation. The system can be a powerful CAD tool and effectively generate test patterns for large sequential circuits with Scan Path.

Proceedings ArticleDOI
01 Mar 1985
TL;DR: Techniques for simulating directly from a hierarchical circuit description without flattening to the level of primitives are presented, indicating that hierarchical fault simulation is superior to traditional techniques.
Abstract: This paper presents techniques for simulating directly from a hierarchical circuit description without flattening to the level of primitives. An overview of traditional fault simulation techniques is followed by details of the hierarchical techniques. The fault model is shown to be decoupled from the simulator programs through the use of a fault library. The fault library allows the user to mix both functional and technology-dependent fault models, which allows fault simulation and consequently test coverage estimation early in the design, with refinements in the fault model and test coverage as the design progresses. Thus testing problems can be detected early in the design process while they are much easier to correct. The circuit description language, SCALD, and the fault library language are described and illustrated with examples. The simulator initialization and execution phases are discussed in detail with emphasis on the unique data structures necessary for hierarchical simulation. The hierarchy provides a framework for an adaptive evaluation technique that speeds the evaluation of faulty machines. Initial performance measurements and experiences with the simulator indicate that hierarchical fault simulation is superior to traditional techniques.

Journal ArticleDOI
TL;DR: This paper demonstrates that the process of modularizing can be organised by a simple computer program which can roughly analyse the fault tree prior to further analysis by a more sophisticated minimizing program.
Abstract: The analysis of a fault-tree by Locks showed that computation could be eased by modularizing the fault-tree. His process involves hand calculation and insight from the analyst. Many computer algorithms for minimizing a fault tree rely on a brute force method which leads to computational buildup. Approaches which simplify a tree by inspection and hand calculation can often be programed and form a useful tool for pre-analysis of a fault tree. This paper demonstrates that the process of modularizing can be organised by a simple computer program which can roughly analyse the fault tree prior to further analysis by a more sophisticated minimizing program. The methods allow some of the benefits of inspection to be incorporated into a computer program.

Patent
08 Jul 1985
TL;DR: In this paper, a built-in test (BIT) system is used to provide fault isolation for the rotor suspension electronics of an electrostatic gyro suspension system and the test circuitry is built into the navigation system electronics and integrated with the system program.
Abstract: The rotor suspension electronics of an electrostatic gyro suspension system is required to perform flawlessly to sustain the life of the gyro Transient abnormalities as short as one millisecond duration will cause the spinning rotor to come in contact with the surrounding electrodes and result in destruction of the gyro Thus, not infrequently after a catastrophic dropped rotor incident no trace of the fault is evident upon ensuing check of the system To remedy this problem a built in test (BIT) system is used to provide fault isolation The test circuitry is built into the navigation system electronics and integrated with the system program The fault isolation electronics comprise sensor circuits to monitor functional subdivisions of the electronic suspension system for signal abnormality and a processing circuit which receives the sensor circuit outputs and identifies the primary source of the fault The faults are detected and the source is flagged at the time of occurance The output of the fault isolation electronics is a latched coded readout which is fed to the nagivation computer for memory storage and any appropriate follow-up system action, such as power shutdown After initialization by the computer, the fault isolation function is an automatic operation by the electronic circuitry

Journal ArticleDOI
01 Jun 1985
TL;DR: Software simulations of faults in simple NMOS logic circuits are described showing that not all fault effects in NMOS circuits are modellable as ‘stuck’ nodes, indicating an improved fault model which would better reflect MOS fault effects has yet to be defined.
Abstract: VLSI circuits currently being designed are so complex that it is now extremely difficult to test them adequately to determine whether or not they have been processed correctly. Design for testability (DFT) techniques are often used in an attempt to ease this problem by identifying and redesigning potentially ‘difficult-to-test’ parts of the circuits. The ‘testability’ of the circuit is usually evaluated in terms of the stuck-at fault model. However, there have been growing doubts over the ability of this model to cover certain common faults that can occur in MOS processing (at present, the dominant VLSI technology). The paper describes software simulations of faults in simple NMOS logic circuits showing that not all fault effects in NMOS circuits are modellable as ‘stuck’ nodes. An improved fault model which would better reflect MOS fault effects has yet to be defined. Until such an improved model is available, DFT rules for MOS circuits are best regarded as provisional. We therefore conclude with a discussion of ad hoc ‘physical design for testability’ techniques that exploit current understanding of the relation between MOS faults and their fault effects.

Journal ArticleDOI
J.P. Robinson1
TL;DR: It is shown that the expected time to error detection and the probability of an undetected double error can be reduced and the amount of reduction is dependent on the shape of the fault coverage curve.
Abstract: The fraction of faults detected for a digital network is frequently high for the first few input combinations applied out of a set of test vectors. For on-line testing, there appears to be an advantage to splitting the test into segments which are applied at different times. It is shown that the expected time to error detection and the probability of an undetected double error can be reduced. The amount of reduction is dependent on the shape of the fault coverage curve. This approach may be applicable in fault-tolerant systems.

Patent
20 Jun 1985
TL;DR: In this article, the authors used conversion means (PR) and computing means (D) for locating the distance of a fault on a power supply line from a substation in an electricity reticulation system.
Abstract: of EP0013104For locating the distance of a fault on a power supply line from a substation in an electricity reticulation system, primarily conversion means, (PR) are used, adapted to provide DC signals whose magnitudes are proportional to the AC values of current and voltage related to the fault and computing (D) means adapted to compute a quotient of those DC signals. The computing means also is adapted to apply an earth fault compensation factor and a line angle correction factor to the DC quotient and to thus provide a measure of the distance to the fault. A sample-and-hold means (S-H) is included, adapted to relay a value of the quotient to provide a measure of distance to fault only after a predetermined time during which transient effects may subside to some extent. An analogue to digital convertor (A-D) relays the signal to a printer (P) to provide a record of fault history. This locator is thus adapted to solve the problem of excessive technical complexity of certain existing apparatuses and so provide a less costly device which can be installed in larger numbers in a reticulation system for more comprehensive monitoring.

Journal ArticleDOI
01 Jun 1985
TL;DR: A dynamic CMOS design style supersedes that of the NMOS bit-serial cells, and the problem of generating tests for stuck-open faults is removed, thus permitting fault tolerance.
Abstract: The paper presents a system of random pattern/signature analysis self-test in NMOS bit-serial signal processing chips, designed by a silicon compiler. Fault coverage is very high, and is determined without full fault simulation. A trial design shows that the cost in silicon, power, complexity and design difficulty is extremely low. A hierarchical system test can be performed, thus permitting fault tolerance. A dynamic CMOS design style supersedes that of the NMOS bit-serial cells. The problem of generating tests for stuck-open faults is removed. This is proved analytically and fault simulation results are presented.

Journal ArticleDOI
TL;DR: In this article, a direct approach for single and multiple fault test set generation on any number of lines of a logical circuit has been described, for which only some visual inspections are needed rather than going through tedious steps of algebraic manipulations.
Abstract: A direct approach for single and multiple fault test set generation on any number of lines of a logical circuit has been described in this paper. The present paper simplifies the results of Ku and Masson [2] for which only some visual inspections are needed rather than going through tedious steps of algebraic manipulations. This method is thus easily applicable to arbitrarily large combinational circuits, whether it is fan-out free or with fan-out nodes.

Journal ArticleDOI
TL;DR: A new approach to fault diagnosis of stored program controlled (SPC) switching systems is presented, which uses the functional behaviour of SPC systems to model faults.
Abstract: The paper presents a new approach to fault diagnosis of stored program controlled (SPC) switching systems. It uses the functional behaviour of SPC systems to model faults. This method uses circuit, structure descriptions and call processing programs to generate automatically the data required for fault analysis and avoids fault simulation.