Showing papers on "Stuck-at fault published in 1990"

A theory of fault-based testing

Abstract: A theory of fault-based program testing is defined and explained. Testing is fault-based when it seeks to demonstrate that prescribed faults are not in a program. It is assumed that a program can only be incorrect in a limited fashion specified by associating alternate expressions with program expressions. Classes of alternate expressions can be infinite. Substituting an alternate expression for a program expression yields an alternate program that is potentially correct. The goal of fault-based testing is to produce a test set that differentiates the program from each of its alternates. A particular form of fault-based testing based on symbolic execution is presented. In symbolic testing, the output from the system is an expression in terms of the input and the symbolic alternative. Equating this with the output from the original program yields a propagation equation whose solutions determine those alternatives which are not differentiated by this test. Since an alternative set can be infinite, it is possible that no finite test differentiates the program from all its alternates. Circumstances are described as to when this can be decided. >

Fault injection experiments using FIAT

Abstract: The results of several experiments conducted using the fault-injection-based automated testing (FIAT) system are presented. FIAT is capable of emulating a variety of distributed system architectures, and it provides the capabilities to monitor system behavior and inject faults for the purpose of experimental characterization and validation of a system's dependability. The experiments consists of exhaustively injecting three separate fault types into various locations, encompassing both the code and data portions of memory images, of two distinct applications executed with several different data values and sizes. Fault types are variations of memory bit faults. The results show that there are a limited number of system-level fault manifestations. These manifestations follow a normal distribution for each fault type. Error detection latencies are found to be normally distributed. The methodology can be used to predict the system-level fault responses during the system design stage. >

A realistic fault model and test algorithms for static random access memories

Abstract: Testing static random access memories (SRAMs) for all possible failures is not feasible and one must restrict the class of faults to be considered. This restricted class is called a fault model. A fault model for SRAMs based on physical spot defects, which are modeled as local disturbances in the layout of the SRAM, is presented. Two linear test algorithms that cover 100% of the faults under the fault model are proposed. A general solution is given for testing word-oriented SRAMs. The practical validity of the fault model and the two test algorithms are verified by a large number of actual wafer tests and device failure analyses. >

Accurate fault location technique for power transmission lines

Abstract: The authors describe a very accurate fault location technique which uses post-fault voltage and current derived at both line ends. Fault location is independent of fault resistance and the method does not require any knowledge of source impedance. It maintains high accuracy for untransposed lines and no fault type identification is required. The authors present the theory of the technique and the results of simulation studies to determine its performance.< >

CMOS bridging fault detection

Abstract: The authors compare the performance of two test generation techniques, stuck fault testing and current testing, when applied to CMOS bridging faults. Accurate simulation of such faults mandated the development of several new design automation tools, including an analog-digital fault simulator. The results of this simulation are analyzed. It is shown that stuck fault test generation, while inherently incapable of directly expressing many of the likely CMOS faults, was still able to generate a set of effective test patterns. Current monitoring, however, by virtue of its more accurate model and less stringent detection criterion, was able to generate tests of measurably higher quality. It is concluded that the selection of one technique over the other becomes a cost tradeoff. Current testing produced test patterns that were consistently more effective in detecting bridging faults. This higher quality comes at higher start-up costs aid higher costs per chip design. >

Diagnosing CMOS bridging faults with stuck-at fault dictionaries

Abstract: It is shown that the traditional approach to diagnosing stuck-at faults with fault dictionaries generated for stuck-at faults is not appropriate for diagnosing CMOS bridging faults. A novel technique for using stuck-at-fault dictionaries to diagnose bridging faults is described. Teradyne's LASAR was used to simulate bridging and stuck-at faults in a number of combinational circuits, including parity trees, multiplexers, and the 74ASCI181 4-b, 16-function ALU (arithmetic and logic unit). When the traditional technique was used, between 30%-50% of the bridging faults were mis-diagnosed, with the presence of a failure indicated on a fault-free node. In addition, as the stuck-at-fault diagnostic ability of a test increased, the bridging fault diagnostic ability decreased. By use of the new technique. over 92% of the bridging faults in the circuits used for this research were diagnosed correctly and less than 4% led to misleading diagnoses. >

PROOFS: a fast, memory efficient sequential circuit fault simulator

Abstract: A super-fast fault simulator for synchronous sequential circuits, called PROOFS, is described. PROOFS achieves high performance by combining all the advantages of differential fault simulation, single fault propagation, and parallel fault simulation, while minimizing their individual disadvantages. PROOFS minimizes the memory requirements, reduces the number of events that need to be evaluated, and simplifies the complexity of the software implementation. PROOFS requires an average of one fifth the memory required for concurrent fault simulation and runs 6 to 67 times faster on the ISCAS sequential benchmarks. >

Test generation for current testing (CMOS ICs)

Abstract: Current testing is useful for testing CMOS ICs because it can detect a large class of manufacturing defects, including defects that traditional stuck-at fault testing misses. The effectiveness of current testing can be enhanced if built-in current sensors are applied on-chip to monitor defect-related abnormal currents in the power supply buses. Such sensors have proved effective for built-in self-test. However, current testing requires the use of a special method to generate test vectors. The authors describe this method, which differs from that for traditional voltage-oriented testing, and postulate a test-generation algorithm for both on-chip and off-chip current testing. The algorithm uses realistic fault models extracted directly from the circuit layout. >

Effects of transient gate-level faults on program behavior

Abstract: Effects of gate-level faults on program behavior are described and used as a basis for fault models at the program level. A simulation model of the IBM RT PC was developed and injected with 18900 gate-level transient faults. A comparison of the system state of good and faulted runs was made to observe internal propagation of errors, while memory traffic and program flow comparisons detected errors in program behavior. Results show several distinct classes of program-level error behavior, including program flow changes, incorrect memory bus traffic, and undetected but corrupted program state. Additionally, the dependencies of fault location, injection time, and workload on error detection coverage are reported. For the IBM RT PC, the error detection latency was shown to follow a Weibull distribution dependent on the error detection mechanism and the two selected workloads. These results aid in the understanding of the effects of gate-level faults and allow for the generation and validation of new fault models, fault injection methods, and error detection mechanisms. >

Increased CMOS IC stuck-at fault coverage with reduced I DDQ test sets.

Abstract: Simplified ATPG and fault simulation algorithms, reduced test set sizes, and increased fault coverage are achieved with I, testing for stuck-at faults. In addition, IDm testing will detect logically redundant and multiple stuck-at faults and improve the detection of non-stuck-at fault defects.

Optimal test set design for analog circuits

Abstract: Given the high cost of testing analog circuit functionality, it is proposed that tests for analog circuits should be designed to detect faults. An algorithm is presented that reduces functional test sets to only those that are sufficient to find out whether a circuit contains a parametric fault. Examples demonstrate that drastic reductions in test time can be achieved without sacrificing fault coverage. >

Diagnosis for wiring interconnects

Abstract: The authors address the problem of generating minimum test sets for diagnosing faults in wiring interconnects on printed circuit boards. It is assumed that all the nets can be accessed in parallel or through a boundary-scan chain on the board. The fault model includes multiple stuck-at and short faults. Three methods for three different diagnosis mechanisms are presented. It is also pointed out that the self-diagnosis problem is the same as the concurrent error detection problem for asymmetric errors. Thus, the diagnostic methods considered are similar to the coding methods used in concurrent error detection. All the diagnostic methods can be extended to structural tests by taking advantage of the geometry of a circuit board to produce an efficient test. >

ATPG for ultra-large structured designs

Abstract: A ATPG (automatic test pattern generation) system that can efficiently create a high-coverage test for extremely large scan designs is described This system is formed by optimally combining a fast fault simulator with a powerful test generator For the ISCAS85 and ISCAS89 circuits, this ATPG system created a test for all testable faults and identified all redundant faults without a single aborted fault This represents the first time this has been achieved for the ISCAS89 designs, and the performance of this ATPG system is significantly better than published results Performing ATPG for the largest ISCAS89 designs, which contained about 25000 gates, required only 3 min of CPU time on an Apollo DN3550 workstation The data collected for the ISCAS designs showed that the ATPG CPU time increased linearly with gate count This strongly suggests that ATPG can be efficiently performed for circuits of 100000 and even one million gates >

A method of fault simulation based on stem regions

Abstract: An exact fault simulation can be achieved by simulating only the faults on reconvergent fan-out stems, while determining the detectability of faults on other lines by critical path tracing within fan-out-free regions. The authors have delimited, for every reconvergent fan-out stem, a region of the circuit outside of which the stem fault does not have to be simulated. Lines on the boundary of such a stem region, called exit lines, have the following property: if the stem fault is detected on the line and the line is critical with respect to a primary output, then the stem fault is detected at that primary output. Any fault simulation technique can be used to simulate the stem fault within its stem region. The fault simulation complexity of a circuit is shown to be directly related to the number and size of stem regions in the circuit. The concept of stem regions has been used as a framework for an efficient fault simulator for combinational circuits. The concept allows a static reduction of the circuit area of explicit analysis for single- as well as multiple-output circuits. A dynamic reduction of processing steps is also achieved as the fault simulation progresses and fault coverage increases. The simulation algorithm is described, and experimental results are shown for the well-known benchmark circuits. >

Functional test generation for finite state machines

Abstract: A functional test generation method for finite-state machines is described. A functional fault model, called the single-transition fault model, on the state transition level is used. In this model, a fault causes a single transition to a wrong destination state. A fault-collapsing technique for this fault model is also described. For each state transition, a small subset of states is selected as the faulty destination states so that the number of modeled faults for test generation is minimized. On the basis of this fault model, the authors developed an automatic test generation algorithm and built a test generation system. The effectiveness of this method is shown by experimental results on a set of benchmark finite-state machines. A 100% stuck-at fault coverage is achieved by the proposed method for several machines, and a very high coverage (>97%) is also obtained for other machines. In comparison with a gate-level test generator STG3, the test generation time is speeded up by a factor of 100. >

Automatic test generation for model-based real-time fault diagnostic systems

Abstract: In a real-time diagnostic system, an alarm sequence generator is used to test the correctness of a fault model. The fault model describes an industrial process being monitored. The alarm sequence generator reads the fault model and generates a user interface, from which specific components can be selected for failure at specified times. The alarm sequence generator assembles all alarms that are causally downstream from the selected set of faulty components and determines which alarms should be turned on based on probabilistic and temporal information in the fault model. The timed alarm sequence can be used by an expert to measure the correctness of a particular model, or can be used as input into a diagnostic system to measure the correctness of the diagnostic system.

Diagnosis oriented test pattern generation

Abstract: This paper addresses the generation of test patterns having diagnostic properties. The authors goal is to produce patterns able not only to detect, but also to distinguish faults in combinational circuits. A general formalization of the problem is first given; a new technique is then introduced to improve the diagnostic capabilities of a traditional automatic test pattern generation (ATPG); the experimental results showing its effectiveness are finally presented. >

Increased CMOS IC stuck-at fault coverage with reduced I/sub DDQ/ test sets

Abstract: The authors discuss the significant improvements that were achieved when a conventional ATPG (automatic test pattern generation) algorithm was modified to generate test sets suitable for I/sub DDQ/ testing. These improvements include increased SAF (stuck-at-fault) coverage, reduced vector set sizes, coverage of logically redundant SAFs and multiple SAFs, increased coverage of CMOS IC non-SAF defects, and reduced CPU cost for ATPG and fault simulation. This reduction in computational complexity for I/sub DDQ /based ATPG enables test generation for much larger circuits than previously possible. Additionally untestable faults can be further categorized to identify SAFs that are truly 'don't-care faults,' thereby offering a more realistic assessment of actual fault coverage. >

Why is less information from logic simulation more useful in fault simulation

Abstract: The authors propose a novel linear-time algorithm for identifying, in a large combinatorial circuit, a large set of faults that are undetectable by a given test vector. Although this so-called X-algorithm does not identify all the undetectable faults, empirical evidence is offered to show that the reduction in the number of remaining faults to be simulated is significant. The algorithm is intended as a simple, fast preprocessing step to be performed after a test vector has been generated, but before the (often lengthy) process of fault simulation begins. The empirical results indicate that the X-algorithm is both useful (indicated by the utility factor) and good (indicated by the effectiveness factor). It provides as much as a 50% reduction in the number of faults that need to be simulated. Moreover, the algorithm seems to identify a large fraction of the undetectable faults. >

Efficient generation of test patterns using Boolean satisfiability

Abstract: A combinational circuit can be tested for the presence of a single stuck-at fault by applying a set of inputs that excite a verifiable output response in that circuit. If the fault is present, the output will be different than it would be if the fault were not present. Given a circuit, the goal of an automatic test pattern generating system is to generate a set of input sets that will detect every possible single stuck-at fault in the circuit. This dissertation describes a new method for generating test patterns: the Boolean satisfiability method. The new method generates test patterns in two steps: First, it constructs a formula expressing the Boolean difference between the unfaulted and faulted circuits. Second, it applies a Boolean satisfiability algorithm to the resulting formula. This approach differs from most programs now in use, which directly search the circuit data structure instead of constructing a formula from it. The new method is quite general and allows for the addition of any heuristic used by the structural search methods. The Boolean satisfiability method has produced excellent results on popular test pattern generation benchmarks.

Fault detection and diagnosis in manufacturing systems: a behavioral model approach

Abstract: An approach to online fault detection and diagnosis in automated manufacturing systems with discrete controls and sensing is described. The approach is based on the concept of behavioural models of the individual system components. These models, which can be developed while the system is being designed, characterize the responses of the devices in the system to arbitrary input signals over the range of acceptable operating conditions. The expected flow of signals through the system, from control inputs to sensor outputs, is captured in the behavioural model dynamics. This model provides the basis for online fault detection by generating expected system response signals which are compared online, in real-time, to the actual sensor signals from the system. Fault diagnosis is accomplished by maintaining a current set of operational assumptions which identify the system components which could cause deviations from the expected behavior. >

A single-state-transition fault model for sequential machines

Abstract: A fault model in the state transition level of finite state machines is studied. In this model, called a single-state-transition (SST) fault model, a fault causes a state transition to go to a wrong destination state while leaving its input/output label intact. An analysis is given to show that a test set that detects all SST faults will also detect most multiple-state-transition (MST) faults in practical finite state machines. It is shown that, for an N-state M-transaction machine, the length of the SST fault test set is upper-bounded by 2*M*N/sup 2/ while the length is exponential in terms of N for a checking experiment. Experimental results show that the test set generated for SST faults achieves not only a high single stuck-at fault coverage but also a high transistor fault coverage for a multilevel implementation of the machine. >

PROOFS: a super fast fault simulator for sequential circuits

Abstract: This paper describes PROOFS, a super fast fault simulator for synchronous sequential logic circuits. PROOFS achieves high performance by combining all the advantages in differential fault simulation, single fault propagation, and parallel fault simulation to minimize the memory requirements, to reduce events that need to be simulated, and to simplify the complexity of the software implementation. The experimental results of PROOFS and other available fault simulators on 20 benchmark circuits showed that PROOFS is the best. >

BiCMOS fault models: is stuck-at adequate?

Abstract: The adequacy of the stuck-at fault model for BiCMOS logic is investigated. Realistic failures in basic logic blocks are examined, and their coverage by the stuck-at model is explored. It is shown that the static stuck-at model cannot cover the complete range of possible failures, and more importantly, tests for stuck-at faults will not detect realistic features in BiCMOS technology. This is because most open faults manifest themselves as delay failures. Through the use of transient analysis it is shown that the only way to insure proper functioning of BiCMOS circuits is to test for delay faults. >

Contest: a fast ATPG tool for very large combinational circuits

Abstract: Contest (cone-oriented test pattern generator), an ATPG (automatic test pattern generation) tool for very large combinational digital circuits, is presented. Contest is based on four major ideas. Cone-oriented circuit partitioning reduces the circuit complexity and increases the number of dominators. The propagation graph is a dynamic data structure that keeps track of all paths from the fault location to a primary output. The multiple backtrace procedure reduces contradictory node assignments by examination of fanout nodes and dynamic implications. The pattern parallel fault dropping technique is based on Hamming distance variations of generated test patterns. Experimental results for benchmark circuits containing up to 40000 nodes illustrate the superiority of the ATPG system. For these circuits a 100% fault coverage for all detectable stuck-at faults and a 100% redundancy identification are achieved. >

Faulted circuit indicator

Abstract: Error-free, reliable registration of a fault in a power distribution circuit is achieved by a faulted circuit indicator that measures the current in the circuit after a discrete time delay following the detection of an overcurrent condition. A fault is registered only if the measured current is less than a prescribed level, evidencing that the overcurrent has operated a protection device (such as a fuse), upstream from the faulted circuit indicator, to interrupt the circuit and clear the fault. Hence, only actual (true) faults, resulting in circuit interruption and isolation of the fault, will be indicated, thereby precluding false registrations that may otherwise occur from non-faults such as transient currents, momentary overloads, inrush currents, and the like.

A hierarchical test generation methodology for digital circuits

Abstract: A new hierarchical modeling and test generation technique for digital circuits is presented. First, a high-level circuit model and a bus fault model are introduced—these generalize the classical gate-level circuit model and the single-stuck-line (SSL) fault model. Faults are represented by vectors allowing many faults to be implicitly tested in parallel. This is illustrated in detail for the special case of array circuits using a new high-level representation, called the modified pseudo-sequential model, which allows simultaneous test generation for faults on individual lines of a multiline bus. A test generation algorithm called VPODEM is then developed to generate tests for bus faults in high-level models of arbitrary combinational circuits. VPODEM reduces to standard PODEM if gate-level circuit and fault models are used. This method can be used to generate tests for general circuits in a hierarchical fashion, with both high- and low-level fault types, yielding 100 percent SSL fault coverage with significantly fewer test patterns and less test generation effort than conventional one-level approaches. Experimental results are presented for representative circuits to compare VPODEM to standard PODEM and to random test generation techniques, demonstrating the advantages of the proposed hierarchical approach.

Empirical failure analysis and validation of fault models in CMOS VLSI

Abstract: A methodology for the experimental evaluation of fault models, using fault diagnosis as the basic approach, is developed. The methodology includes a way of determining the defect level of test sets, in addition to determining the adequacy of the fault models used to generate them. The key elements of the method are the design and fabrication of an easily diagnosable test chip, representative of the class of circuits being studied, the CAD (computer-aided-design) tools used in its design, and its fabrication process; the derivation of an extremely robust test set, capable of detecting faults from within a wide range of fault models; the development of a set of diagnostic tools to perform automated diagnosis on faulty circuits and the use of the results to get measures of 'effectiveness' of the fault models considered; the validation of the results of the diagnosis by means of an electron-beam voltage-contrast circuit prober. Experimental results from a large number of samples of the test circuit are presented. >

New approach to power line protection based upon the detection of fault induced high frequency signals

Abstract: The authors outline the salient features of a protection technique for transmission lines which utilises the high frequency components of fault generated noise. The approach is based on the nonunit type scheme, which makes use of a stack-tuner circuit connected to the coupling capacitor of a capacitor voltage transformer. The stack-tuner is tuned to a certain frequency bandwidth and is arranged to act as a high frequency switch. The signals derived from the stack-tuner are used to determine whether the fault is inside or outside the protected zone.