Showing papers on "Stuck-at fault published in 1991"

Neural networks in process fault diagnosis

Abstract: Fault detection and diagnosis is an important problem in process automation. Both model-based methods and expert systems have been suggested to solve the problem, along with the pattern recognition approach. A number of possible neural network architectures for fault diagnosis are studied. The multilayer perceptron network with a hyperbolic tangent as the nonlinear element seems best suited for the task. As a test case, a realistic heat exchanger-continuous stirred tank reactor system is studied. The system has 14 noisy measurements and 10 faults. The proposed neural network was able to learn the faults in under 3000 training cycles and then to detect and classify the faults correctly. Principal component analysis is used to illustrate the fault diagnosis problem in question. >

Compactest: a method to generate compact test sets for combinational circuits

Abstract: Heuristics to aid the derivation of small test sets that detect single stuck-at faults in combinational logic circuits are proposed. The heuristics can be added to existing test pattern generators without compromising fault coverage. Experimental results obtained by adding the proposed heuristics to a simple PODEM procedure and applying it to the ISCAS-85 and fully-scanned ISCAS-89 benchmark circuits are presented to substantiate the effectiveness of the proposed heuristics. >

An efficient, forward fault simulation algorithm based on the parallel pattern single fault propagat

Abstract: In this paper, we present a fast fault simulator, FSIM, for combinational circuits. FSIM is based on the parallel pattern single fault propagation (PPSFP) technique. The essential idea of FSIM is to simulate the circuit in the forward levelized order and to prune off unnecessary gates in the early stages. In this way, FSIM performs fault simulations only for the gates which are affected by 'the injected faults. Another key feature employed in FSIM is the use of multiple last-in first-out (L,IFO) stacks instead of the commonly used priority queue [9]. The propagation time of the mult,iple LIFO stacks is O(n) and that of the priority queue O(n log n), where n is the number of gates in the propagation zone of the fault under consideration. The two features achieve a substantial reduction of the processing time. Experimental results for ten benchmark circuits show that FSIM outperforms other competing PPSFP fault simulators, Moreover, the efficiency of FSIM is less dependent on the circuit structure than other fault simulators. Experimental results of FSIM for various packet sizes, i.e., the number of test patterns simulated at a time, are also presented.

Test Pattern Generation for Realistic Bridge Faults in CMOS ICs

Abstract: Two approaches have been used to balance the cost of generating effective tests for IC's and the need to increase the quality level of shipped IC's. The first approach favors using high-level fault models to reduce test generation costs, and the second approach favors the use of low-level, technology-specific fault models that lead to high test generation costs, but increased defect coverage in the tested circuits. In this paper we simulate complete single stuck-at test sets against a low-level model of bridge defects showing that an unacceptably high percentage of such defects are not detected by the complete stuck-at test sets. Next, we show how low-level bridge fault models can be incorporated into high-level test generation. Finally, we describe our system for generating effective tests for bridge faults and report on its performance.

Predicting where faults can hide from testing

Abstract: Sensitivity analysis, which estimates the probability that a program location can hide a failure-causing fault, is addressed. The concept of sensitivity is discussed, and a fault/failure model that accounts for fault location is presented. Sensitivity analysis requires that every location be analyzed for three properties: the probability of execution occurring, the probability of infection occurring, and the probability of propagation occurring. One type of analysis is required to handle each part of the fault/failure model. Each of these analyses is examined, and the interpretation of the resulting three sets of probability estimates for each location is discussed. The relationship of the approach to testability is considered. >

DIATEST: a fast diagnostic test pattern generator for combinational circuits

Abstract: The authors present an efficient algorithm for the generation of diagnostic test patterns which distinguish between two arbitrary single stuck-at faults. The algorithm is able to extend a given set of test patterns which is generated from the viewpoint of fault detection to a diagnostic test pattern set with a diagnostic resolution down to a fault equivalence class. The difficult problem of identifying the equivalence of two faults, analogous to the problem of redundancy identification in ATPG, has been solved. The efficiency of the algorithm is demonstrated by experimental results for a set of benchmark circuits. DIATEST, the implementation of the algorithm, either generates diagnostic test patterns for all distinguishable pairs of faults or identifies pairs of faults as being equivalent for each of the benchmark circuits. >

A fault oriented partial scan design approach

Abstract: The authors propose a fault oriented partial scan design methodology to be performed as a sequel to test generation. Given the cost of converting each flip-flop to a scanned flip-flop and an overall bound on the cost of the scan design, the program OPUS-2 selects a set of flip-flops which are most likely to improve the quality of test generation. The expected improvement in testability is modeled by profit functions quantifying the reduction in weighted cycles, or the reduction in SCOAP values at hard-to-detect fault sites. Experiments performed on ISCAS89 sequential benchmark circuits show that, by analytically selecting only 10-20% of the flip-flops, the circuits can be tested to the same level of quality as a fully scanned circuit. The advantages of the proposed method are that the highest possible fault coverage can be achieved while limiting the cost of scan to a user-specified limit. >

Timing analysis and delay-fault test generation using path-recursive functions

Abstract: The authors introduce an efficient method for generating the functional forms of path analysis problems. They demonstrate that the resulting function is linear in the size of the circuit. The functions are then tested for satisfiability either using a Boolean network satisfiability algorithm suggested by T. Larrabee (1989) or through the construction of BDDs. The effectiveness of the proposed approach is shown for timing analysis and robust path delay-fault test generation. This method also holds promise for both static and dynamic hazard analysis, and for test generation using all other delay-fault models, tau -irredundant fault models, and stuck-open fault models. >

Fault recovery system of a ring network

Abstract: A fault recovery system of a ring network based on a synchronous transport module transmission system, having a fault data writing unit for writing, when an input fault is detected by a node, fault data in a predetermined user byte in an overhead of a frame flowing through both a working line and a protection line running in opposite directions to each other. By detecting the fault data in a supervision node or a node just before the fault position, the supervision node or the node just before the fault position executes a loopback operation.

Fault modeling for the testing of mixed integrated circuits

Abstract: The goal of the research described in this paper is to introduce a fault-modeling technique for simulating defective analog components in Mixed Analog/Digital Integrated Circuits. The proposed fault- modeling strategy has been implemented to develop analog fault models representing the effect of spot defects in CMOS circuits. Results from an initial study of opamps are summarized and detailed results from onc example are included as an illustration of the fault- modeling process. 1 Introduction Application of analog components within large digital systems - a typical configuration in modern mixed analog/digital IC's - generates many new challenges in both design and testing areas (l), (2), (3), (4). EspccialIy difficult to solve are testing problems due to the observability limitations caused by the nature of the boundary between the digital and analog components of mixed IC's. Although there are many mixcd IC testing problems, this paper focuses on only one of them - a strategy of fault simulation. More specifically, this paper introduces a fault- modeling methodology which could be applied to capture the malfunctioning of analog components in mixed IC's. The goal of the reported research is to develop fault models that enable efficient simulation of the entire mixed IC by using a technique that is as close as possible to traditional digital circuit simulation techniques. Hence, this paper concentrates solely on the fault- modeling technique. It is organized in the following way. In Section 2, the general fault-modeling methodology developed for analog components of mixed IC's is introduced. In Section 3, an implementation of this methodology for CMOS technology is described in morc detail. Finally, in Section 4, an attempt to generalize obtained results is made in order to determine the practicality of the proposed fault-modeling methodology. This section also gives a list of problems to be solved in the subsequent research dealing with testing of mixcd analog/digital integrated circuits.

High impedance fault detection utilizing incremental variance of normalized even order harmonic power

Abstract: A novel method for the detection of high-impedance faults is proposed which uses the incremental variance of a normalized even order ratio measure. Staged fault tests were extensively carried out in Korean electric power systems. From the analysis of the staged fault test data, it was found that there exists an intermittent arcing phenomenon in most high-impedance faults and that the waveforms of this arcing fault current have an asymmetrical shape in each cycle. Based on these facts, three criteria, (even-order power, even-order ratio, and even-order incremental variance) for fault detection are presented, all of which are based on the changes of normalized even-order harmonic power in fault currents. These criteria are compared through the analysis of staged fault data and normal switching event data. It is shown that the even-order incremental variance criterion is superior to the other two criteria and that, with this criterion, high-impedance faults can be distinguished from normal switching events, including special loads such as electric furnaces and subways. Microprocessor-based protective relays, which can detect high-impedance faults by using the proposed methods, have been constructed, installed in Korea Electric Power Corporation substations, and tested during the last two years. Details of these field tests are given. >

Testing delay-insensitive circuits

Abstract: A method is developed to test delay-insensitive circuits, using the single stuck-at fault model. These circuits are synthesized from a high-level specification. Since the circuits are hazard-free by construction, there is no test for hazards in the circuit. Most faults cause the circuit to halt during test, since they cause an acknowledgement not to occur when it should. There are stuck-at faults that do not cause the circuit to halt under any condition. These are stimulating faults; they cause a premature firing of a production rule. For such a stimulating fault to be testable, the premature firing has to be propagated to a primary output. If this is not guaranteed to occur, then one or more test points have to be added to the circuit. Any stuck-at fault is testable, with the possible addition of test points. For combinational delay-insensitive circuits, finding test vectors is reduced to the same problem as for synchronous combinational logic. For sequential circuits, the synthesis method is used to find a test for each fault efficiently, to find the location of the test points, and to find a test that detects all faults in a circuit. The number of test points needed to fully test the circuit is very low, and the size of the additional testing circuitry is small. A test derived with a simple transformation of the handshaking expansion yields high fault coverage. Adding tests for the remaining faults results in a small complete test for the circuit.

Fault Location with Current Monitoring

Abstract: Recently there has been renewed interest in fault detection in static CMOS circuits through current monitoring (“Iddq testing”). It is shown that accurate defect (diagnosis miay be performed with a combination of current and voltage observations. The proposed system combines a simple single fault model for test generation with a more realistic multiple defect model for diagnosis. ‘The associated hardware is sufficiently simple that on-board implementation is possible.

On behavior fault modeling for digital designs

Abstract: A critical aspect of digital electronics is the testing of the manufactured designs for correct functionality. The testing process consists of first generating a set of test vectors, then applying them as stimuli to the manufactured designs, and finally comparing the output response with that of the desired response. A design is considered acceptable when the output response matches the desired response and is rejected otherwise. Fundamental to the process of test vector generation is the assumption of an underlying fault model that is a model of the failures introduced during manufacture. The choice of the fault model influences the accuracy of testing and the computer CPU time required to generate test vectors for a given design. The most popular fault model in the industry today is the single stuck-at fault at the gate level that requires exorbitantly large CPU times for moderately complex digital designs. This article introduces new high-level behavior fault models that are associated with high-level hardware descriptions of digital designs. The derivation of these faults is based on the failure modes of the language constructs of the high-level hardware description language. Behavior faults include multiple input stuck-at faults and this article also reasons the nature of test vectors for such faults. The potential advantages of behavior fault modeling include early estimates of fault coverage in the design process prior to the synthesis of the gate-level representation of the design, faster fault simulation, and results that may be more comprehensible to the high-level architects. The behavior-fault-modeling approach is evaluated through a study of correlation of the results of behavior fault simulation of several representative digital designs with the results of gate-level single stuck-at fault simulation of equivalent gate-level representations.

An accurate bridging fault test pattern generator

Abstract: Test pattern generation for bridging faults has been considered impractical. This paper presents an accurate bridging fault test pattern generator Lhat requires only a gate-level implementation of the circuit. No transistorlevel simulations are required during test pattern generation. Results presented for the ISCAS'85 benchmark circuits indicate that this test pattern generator is 8 practical solution to a problem that must be solved in order to detect the failures that occur in modern VLSI circuits.

Two-stage fault location

Abstract: A two-stage procedure for locating VLSI faults is presented. The approach utilizes dynamic fault dictionaries, test set partitioning, and reduced fault lists to achieve a reduction in size and complexity over classic static fault dictionaries. An industrial implementation is reported in which faults were injected and diagnosed in a VLSI chip and the perjiormunce of two-stage fault location was measured.

Stuck fault and current testing comparison using cmos chip test

Abstract: This paper compares the effectiveness of Stuck Fault and Current Testing, as applied to CMOS ICs. The comparison is performed by testing sequential CMOS chips using patterns developed via both methodis, and evaluating their ability to identify faulty prciduct. The test results are then contrasted to a previous study in which a smaller, combinatorial chip was tested by the same means. The results indicate that, for the investigated set of chips, Current Testing provides a better screen of defective product for some classes of defects, while Stuck Fault Testing is more effective on others.

Optimal ordering of analog integrated circuit tests to minimize test time

Abstract: This paper describes an algorithm that uses dynamic programming to order IC tests so that faulty circuits are detected early in the test sequence and the average test time is minimized. An accurate estimate of the probabilities of individual tests failing, and the joint probabilities of several tests failing is required. These probabilities can be estimated using statistical simulation techniques or from actual circuits. The ordering algorithm is O(mn2") where n is the number of tests to be ordered, and m is the number of data points.

An experimental approach to analog fault models

Abstract: A comprehensive approach to model faults in analog circuits and systems based on experimental statistics of manufacturing defects is presented. A case study based on a simple sample-and-hold circuit is discussed with specific results. It is shown that the digital fault models are applicable to analog and mixed-signal circuits but they account only for catastrophic faults. Out-of-specification faults occur as often as catastrophic faults and must be addressed in any DFT (discrete Fourier transform) technique or test generation algorithm. >

Delay testing of digital circuits by output waveform analysis

Abstract: A new method for delay fault testing of digital circuits is presented. Unlike catastrophic failures that simply have incorrect steady-state logic values at the circuit outputs, delay faults change the shape of the output waveforms by moving the signal transitions in time. Therefore, since the output waveforms contain information about the circuit delays, instead of only latching the outputs at the sampling time, the output waveforms between samples are analyzed as well. Two classes of output waveform analysis are discussed. In the first technique, the output waveform is observed for any changes after the sampling time, since in a fault-free circuit, the outputs are expected to have stabilized at the desired logic values. In the second technique, information is extracted from the faulty and fault-free waveforms before the sampling time, and compared for any differences. Circuits for the waveform analyzers are presented to show that the method is feasible, and experimental results are given.

Maximal diagnosis for wiring networks

Abstract: Previous work on the diagnosis of faults in a wiring network has been based on the assumption that both open and short faults do not exist on the same net. When this assumption is relaxed, these results fail to identify all diagnosable faults. The non-diagnosability of these faults, including shorts between nets, represents a deficiency. In this paper we analyze and explain the causes for this deficiency. In addition, we provide new theoretical results and test algorithms, and show how these deficiencies can be overcome. A test set, which is generated based on these results, can identify all diagnosable faults in a wiring network with arbitrary open and short faults. Two adaptive diagnosis algorithms are also presented which can reduce the number of test vectors while retaining the same level of diagnostic resolution. Another algorithm that can reduce the number of vectors by exploring the structure information of the network is also presented.

PARIS: a parallel pattern fault simulator for synchronous sequential circuits

Abstract: The authors describe PARIS, a parallel-pattern fault simulator for synchronous sequential circuits. PARIS is based on the well-known approach of parallel pattern single fault propagation for combinational circuits and features several new techniques. Every single pattern packet is simulated by an iterative, event-driven method. Heuristic look-ahead of signal values minimizes the number of events that must be tracked. Clever circuit partitioning prevents multiple evaluation of the feedback free parts of the circuit, thus reducing the required simulation effort. Experiments show that PARIS runs at a substantially higher asymptotic speed compared with a state-of-the-art fault simulator for synchronous sequential circuits. >

Minimal Test Sets for Combinational Circuits

Abstract: Generating minimal test sets for combinational circuits is a NP-hard problem. In this paper it will be shown that for a class of circuits with a high fnult compatibility well-known test set compaction methods such as dynamic compaction and reverse order fault simulation do not effectively minimize the test set. Furthermore it will be shown for a number of benchmark circuits that it is possible to generate test sets that are significantly smaller than test sets generated by conventional test set compaction methods. This paper will also present an algorithm based on finding a maximal clique in a graph to estimate the size of a minimum test set.

Self-diagnosis and self-repair system for image forming apparatus

Abstract: The system of the present invention has a plurality of sensors 1a, 1b and 1c and a system control circuit which includes a case memory portion and a work script memory portion. In response to application of state data from the sensors 1a, 1b and 1c, the system converts the state data into symbolic data. Then the symbolic data is evaluated to judge whether or not a fault exists and to specify a fault symptom. As a result of the judgement, a fault symptom and a fault in the objective machine are determined. Thereafter, cases stored in the case memory portion are retrieved on the basis of the results of the fault diagnosis and a fault simulation. A case which closely resembles the present state of the objective machine is selected. Then, repair work described in the selected case is executed.

Automatic test point insertion for pseudo-random testing

Abstract: A combination of techniques for efficiently inserting test points is proposed. These techniques refer to three complementary abstraction levels: algorithms, circuits, and layout. The authors deal with pseudo-random testing and present a method of condensing test points based on the notion of fault sector. Based on a set of proposed heuristics, a tool for automatically inserting test points was developed. Experimental results obtained with the tool are presented to indicate that excellent pseudo-random testability can be achieved with few test points. This technique leads to the lowest reported number of test points while significantly reducing the number of random patterns which are required to achieve very close to 100% fault coverage. >

Performance trade-offs in a parallel test generation/fault simulation environment

Abstract: Heuristics are proposed to partition faults for parallel test generation with minimization of both the overall run time and test length as an objective. For efficient utilization of available processors, the work load has to be balanced at all times. Since it is very difficult to predict how difficult it will be to generate a test for a particular fault, the authors propose a load balancing method which uses static partitioning initially and then uses dynamic allocation of work for processors which become idle. A theoretical model is presented to predict the performance of the parallel test generation/fault simulation process. Experimental results based on an implementation of the Intel IPSC/2 hypercube multiprocessor using the ISCAS combinational benchmark circuits are presented. >

Fault models for artificial neural networks

Abstract: The author describes a method by which fault models can be developed for neural networks visualized at the abstract level, thus allowing their inherent fault tolerance to be probed. The derivation of such fault models has two stages: the location of where faults can occur, and the definition of the faults' characteristics. As an example, a fault model for the multilayer perceptron neural network model is developed for each stage. The abstract nature of such fault models increases the possibility of their being generic in nature due to the independence of implementation. Also, they will allow the inherent fault tolerance of a neural network to be constructively and realistically investigated. >

Test generation for synchronous sequential circuits using multiple observation times

Abstract: The test generation problem for synchronous sequential circuits is considered in the case where hardware reset is not available. The observations which form the motivation for the work are given. On the basis of the observations, the use of multiple fault free responses as well as multiple time units for fault detection is suggested. Application to gate level synchronous sequential circuits is then considered. Experimental results are given to support the claim that a small number of observation times is required, and that a small number of fault free responses need be stored for every fault. 100% fault efficiency is achieved. >

Two fault injection techniques for test of fault handling mechanisms

Abstract: Two fault injection techniques for experimental validation of fault handling mechanisms in computer systems are investigated and compared. One technique is based on irradiation of ICs with heavy-ion radiation from a 252Cf source. The other technique uses voltage sags injected in the power supply rails to ICs. Both techniques have been used for fault injection experiments with the MC6809E microprocessor. Most errors generated by the 252Cf method were seen first in the address bus, while the power supply disturbances most frequently affected the control signals. An error classification shows that both methods generate many control flow errors, while pure data errors are infrequent. Results from a simulation experiment show that that the low number data errors in the 252Cf experiments can be explained by the fact that many errors in data registers are overwritten owing to the normal program execution.