Showing papers on "Stuck-at fault published in 1992"

Investigation of fault modes of voltage-fed inverter system for induction motor drive

Abstract: The reliability of power electronics systems is of paramount importance in industrial, commercial, aerospace, and military applications. The knowledge about the fault mode behavior of a converter system is extremely important from the standpoint of improved system design, protection, and fault tolerant control. This paper describes a systematic investigation into the various fault modes of a voltage-fed PWM inverter system for induction motor drives. After identifying all the fault modes, a preliminary mathematical analysis has been made for the key fault types, namely, input supply single line to ground fault, rectifier diode short circuit, inverter transistor base drive open, and inverter transistor short-circuit conditions. The predicted fault performances are then substantiated by simulation study. The study has been used to determine stresses in power circuit components and to evaluate satisfactory post-fault steady-state operating regions. The results are equally useful for better protection system design and easy fault diagnosis. They will be used to improve system reliability by using fault tolerant control. >

PROOFS: a fast, memory-efficient sequential circuit fault simulator

Abstract: The authors describe PROOFS, a fast fault simulator for synchronous sequential circuits, PROOFS achieves high performance by combining all the advantages of differential fault simulation, single fault propagation, and parallel fault simulation, while minimizing their individual disadvantages. The fault simulator minimizes the memory requirements, reduces the number of gate evaluations, and simplifies the complexity of the software implementation. PROOFS requires an average of one fifth the memory required for concurrent fault simulation and runs six to 67 times faster on the ISCAS-89 sequential benchmark circuits. >

Analog circuit fault diagnosis based on sensitivity computation and functional testing

Abstract: An approach based on functional testing and on sensitivity calculation of many output parameters for diagnosis of defective elements in analog circuits is presented. A sensitivity matrix that gives the relation between the deviation of output parameters and the deviation of defective components in a circuit forms the basis of the test equations. Diverse types of measurement help improve the diagnostic resolution. Experimental results are presented to clarify the algorithm and prove its efficiency in a practical case. >

Delay fault models and test generation for random logic sequential circuits

Abstract: The authors study the problem of delay fault modeling and test generation for any random logic sequential circuit. The proposed test generation method, based on transition and hazard states of signals, is applicable to any sequential circuit of either non-scan, scan or scan-hold type of design. Three fault models based on different initial state assumptions during the propagation of the fault effect to a primary output are proposed and analyzed using the proposed delay fault test generation method. A novel thirteen-value algebra is considered to simplify the analysis of robust and nonrobust tests during fault simulation of path delay faults. >

Test generation by environment emulation

Abstract: Generation, validation and fault-grading of test patterns, and test and debug of logic circuits, are enhanced by emulation of the logic circuits in programmable gate arrays. Two emulations of the logic circuit are preferably created, one of which is a "good" model containing no faults and the other of which is a "faultable" model into which possible faults may be selectively introduced. A fault is introduced in the faultable model, and the two models are exercised in parallel by applying the same pattern of test vectors to both models. The test vector pattern may be generated by an emulation of the intended operating environment of the logic circuit. Differences in the output signals of the two models indicate that the fault has been detected by the applied test pattern. Application of the test pattern is repeated for each of a sequence of possible faults, to determine the extent to which the test pattern enables detection of faults in the logic circuit. A fault dictionary is produced which includes an indication of the test vector at which each fault is detected, the output signal differences indicative of fault detection, and a log of the faults detected. The faultable emulation is also used for device testing by comparing its outputs to those of a logic circuit, and injecting selected faults (for example, those indicated by comparing failure patterns to fault dictionary entries) to aid in device debug. Techniques are described for modeling faults, sequentially activating the faults in hardware time, preparing a fault dictionary, and extracting a test program in a format adaptable to standard ATE systems, and testing a debugging devices by comparing their behavior to that of a faultable emulation model of the device.

An image forming apparatus provided with self-diagnosis system

Abstract: In an image forming machine, an objective model storage device stores parameter data that represent elements of the machine and relationships among such parameters, and parameter membership functions, and fault diagnosis knowledge A degradation storage device stores a fuzzy qualitative value for a parameter changed by degradation of an element of the machine Preferably, degradation indicative data are converted into fuzzy qualitative values, and the value of the parameter changed by degradation is represented by a fuzzy qualitative value The machine includes sensors for sensing functional states thereof, and providing state data representative of such states The state data sensed by the sensors are converted into fuzzy qualitative values Then, a fault judgement device determines whether or not a fault exists by comparing the obtained fuzzy qualitative values with the parameter data stored in the objective model storage device If the fault judgement device determines that a fault exists, a fault diagnosis device performs fault diagnosis by utilizing, as an initial value, the value of the parameter changed by degradation A specification device specifies fault causes by comparing the result of the diagnosis with the state data which was converted into the fuzzy qualitative values Then, a repair device operates actuators of the machine to overcome the specified fault

HOPE: an efficient parallel fault simulator

Abstract: The authors present an efficient sequential circuit parallel fault simulator, HOPE, which simulates 32 faults at a time. HOPE is a parallel fault simulator based on single fault propagation. It adopts the zero gate delay model. The key idea incorporated in HOPE is to screen out faults with short propagation paths, and prevent them from being simulated in parallel. The screening process drastically reduces the number of faults simulated in parallel to achieve substantial speedup. The experimental results presented show that HOPE is about two times faster than PROOFS for most ISCAS89 sequential benchmark circuits. >

Fault Model Evolution For Diagnosis: Accuracy vs Precision

Abstract: This paper describes the evolution of accurate fault models, especially with respect to integrated circuit diagnosis. The difference between accuracy and precision is described. The solution to the Byzantine General's problem is described using the voting model for CMOS bridging faults.

HOPE: an efficient parallel fault simulator for synchronous sequential circuits

Abstract: HOPE is an efficient parallel fault simulator for synchronous sequential circuits that employs the parallel version of the single fault propagation technique. HOPE is based on an earlier fault simulator railed PROOFS, which employs several heuristics to efficiently drop faults and to avoid simulation of many inactive faults. In this paper, we propose three new techniques that substantially speed up parallel fault simulation: (1) reduction of faults simulated in parallel through mapping nonstem faults to stem faults, (2) a new fault injection method called functional fault injection, and (3) a combination of a static fault ordering method and a dynamic fault ordering method. Based on our experiments, our fault simulator, HOPE, which incorporates the proposed techniques, is about 1.6 times faster than PROOFS for 16 benchmark circuits.

The multiple observation time test strategy

Abstract: The authors consider the test generation problem, for synchronous sequential circuits in the case where hardware reset is not available (or cannot be assumed to be fault free). It is shown that the conventional testing approach, in which a fault is detected at a single predetermined time unit along the test sequence and in which the response of the circuit under test is compared against a single fault-free response, valid for all initial states of the circuit, can cause detectable faults to be declared undetectable. The use of a small number of different observation times and a small number of fault-free responses can allow the fault to be detected. Based on this observation, the use of multiple fault free responses and multiple time units for observation of the response of the circuit under test is suggested and test generation algorithms under the multiple observation time test strategy are given. Experimental results demonstrate the effectiveness and practicality of the multiple-observation-time strategy in increasing the fault coverage. >

On the generation of small dictionaries for fault location

Abstract: Fault location based on a fault dictionary is considered. To justify the use of a precomputed dictionary in terms of computation time, the computational effort invested in computing a dictionary is first analyzed. The number of circuit diagnoses that need to be performed dynamically, without the use of precomputed knowledge, before the overall effort exceeds the effort of computing a dictionary, is studied. Experimental results on ISCAS85 circuits show that for relatively small numbers of diagnoses, a precomputed dictionary is more efficient. A method to derive small dictionaries without losing resolution of modeled faults is then proposed. Methods to compact the resulting dictionary further, using compaction techniques generally applied to fault detection, are then described. Experimental results are presented to demonstrate the effectiveness of the methods presented. Internal observation points to increase the resolution of the test set are also considered.

Diagnostic Fault Simulation of Sequential Circuits

Abstract: In this work we describe a diagnostic fault simulator for sequential circuits which evaluates the effectiveness of a given test set in distinguishing between faults. Diagnostic fault simulation is performed on several ISCAS89 sequential benchmark circuits using two diferent deterministic test sets for each circuit. Several diagnostic measures are reported, including the diagnostic resolution, the diagnostic power, and the sizes of the indistinguishable fault classes. In addition, lists of indistinguishable faults are generated. Use of the diagnostic fault simulator to diagnose faults, given the output responses of failing devices, is also described.

Principles of fault current limitation by a resonant LC circuit

Abstract: The reduction of fault current is one of the oldest problems of power systems engineering. Fault current reduction permits the interconnection of large networks without replacing circuit breakers, improves transient stability, and reduces the cost of equipment. The paper investigates the reduction of fault current by the insertion of a resonant LC circuit into the transmission line. The device consists of a capacitor and a thyristor-switched inductance, tuned to the supply frequency. The thyristor switches are operated at zero-current-crossing to eliminate the generation of harmonics. The system operation is analysed using analytic methods and transient simulation techniques. A parametric study determines the effect of components and network parameters on the current limiter operation. Design methods and component selection criteria are developed. The results demonstrate that the device can reduce both transient and steady-state fault current significantly. It can be built with commercially available components. The significant operation improvement is expected to justify the cost of the new device.

ROTCO: a reverse order test compaction technique

Abstract: In this paper, the authors consider the problem of reducing the test set sizes for single stuck-at faults in combinational logic circuits. They report on an alternative to the conventional reverse order fault simulation, called reverse order test compaction (ROTCO). The proposed procedure processes a test set obtained by an existing test generator, with the sim of reducing the test set size. Unlike reverse order fault simulation, the proposed procedure allows the test vectors to be changed in order to increase the flexibility in detecting faults detected by earlier vectors, thereby potentially removing tests that cannot be removed by reverse order fault simulation. Experimental results for ISCAS-85 and PLA benchmark circuits are presented to demonstrate the effectiveness of the proposed procedure. >

Hierarchical fault modeling for analog and mixed-signal circuits

Abstract: Presents a comprehensive approach, based on functional error characterization, for modeling faults in analog and mixed-signal circuits. A case study based on a CMOS and an nMOS operational amplifier is discussed, and a full listing of derived behavioral fault models is presented. These fault models are then mapped to the faulty behavior at the macro-circuit level. >

E-PROOFS: a CMOS bridging fault simulator

Abstract: The problem of bridging fault simulation under the conventional voltage testing environment is considered. A method to provide electrical-level simulation accuracy, without paying the associated performance penalties, is proposed. A three-level simulation model is used, balancing the tradeoffs among gate-level, switch-level, and electrical-level simulation. Large memory overheads are avoided by localizing the fault, and by performing electrical-level simulation only in the area around the fault. This approach is sufficiently flexible to model feedback faults, BiCMOS circuits, stuck-open faults, and any fault that can be described with a circuit netlist. Tests were run on several ISCAS combinational and sequential benchmark circuits, using realistic cells and transistor parameters; results show that accurate simulations can be performed in reasonable time.<>

A functional fault model for sequential machines

Abstract: A fault model at the state transition level is proposed for finite state machines. In this model, a fault causes the destination state of a state transition to be faulty. Analysis shows that a test set that detects all single-state-transition (SST) faults will also detect most multiple-state-transition (MST) faults in practical finite state machines. The quality of the test set generated for SST faults is close to that of the sequences derived from the checking experiment. It is also shown that the upper bound of the length of the SST fault test is 2MN/sup 2/ for an N-state M-transition machine, while that of the checking sequence is exponential. An automatic test generation algorithm and a test generation system, FTG, based on the model show that the test set generated for SST faults achieves high single stuck-at-fault coverage as well as high transistor fault coverage for multilevel implementations of the machine. >

A novel approach to delay-fault diagnosis

Abstract: The authors discuss possibilities of delay fault diagnosis based on fault simulation. They detail the proposed approach based on critical path tracing. A path tracing process is presented with information provided by a logic simulation. Due to the limitations induced by such a simulation, a reliable approach is described based on a six-valued logic simulation. It requires no delay size based fault models and considers only the fault-free circuit. This method is an alternative to fault simulation based approaches and provides perfectly reliable results. It does not require timing evaluations and can be very accurate. >

Equivalence of robust delay-fault and single stuck-fault test generation

Abstract: A link between the problems of robust delay-fault and single stuck-fault test generation is established. In particular, it is proved that all the robust test vector pairs for any path delay-fault in a network are directly obtained by all the test vectors for a corresponding single stuck-fault in a modified network. Since single stuck-fault test generation is a well solved problem, this result yields an efficient algorithm for robust delay-fault test generation. Experimental results demonstrate the efficiency of the proposed technique. >

Dynamic fault tree models: techniques for analysis of advanced fault tolerant computer systems

Abstract: There is a need for the development of methods for evaluating the vulnerability to failure of goods or systems produced using advanced technology. In particular, the systems for which this evaluation is most critical tend to be complex fault tolerant systems intended for applications where a catastrophic failure can mean loss of life. We contribute to this development of evaluation methods by extending the traditionally combinatorial fault tree evaluation method in such a way that it becomes capable of modeling the full range of system behavior that can be expressed with Markov chains for non-repairable systems. The resulting new modeling technique is called dynamic fault trees and combines the best characteristics of both the fault tree and Markov chain modeling methods. This modeling method requires a two-step procedure that is usually needed for analytical modeling methods: model generation followed by model solution. To further extend the dynamic fault tree method, we develop a one-step algorithm in which the model can be solved as it is generated. This helps ease the use of certain approximation methods for reducing model size and helps optimize the use of computation resources.

Diagnosis of leakage faults with I DDQ

Abstract: Recently there has been renewed interest in fault detection in static CMOS circuits through I DDQ monitoring. This work shows that, in addition to fault detection, accurate fault diagnosis may be performed using a combination of current and voltage observations. The proposed system combines a simple single fault model for test generation with a more realistic multiple defect model for diagnosis, and as a result requires only minor modifications to existing stuck-at fault ATPG software. The associated hardware is sufficiently simple that on-board implementation is possible. Experimental results demonstrate the effectiveness of the method on a standard-cell ASIC.

Test Suite Generation from a FSM with a Given Type of Implementation Errors

Abstract: The general model of functional faults in FSM implementations is proposed. It is called a fault function and allows to represent in a concise way all mutants of a reference FSM with a given type of implementation errors. It is shown that existing fault models correspond to particular (constant) forms of fault function. A new method (FF-method) for test suite derivation from a reference FSM, which is complete for all faults defined by arbitrary given fault function, is presented in this paper. This method is a generalization of the whole group of methods based on characterization (sub)sets or state identification.

Fault location techniques for radial and loop transmission systems using digital fault recorded data

Abstract: The authors present digital fault location techniques for transmission systems when digital fault recorded data are available at one terminal or two terminals. The systems under consideration are a 115 kV loop transmission system with data available at two terminals and a 69 kV radial transmission system with data available at one terminal. The data under consideration were recorded using digital fault recorders. The conversion of the data to workable data files and the techniques developed to achieve the highest accuracy in determining the fault location are discussed. Intermediate load buses and loads are considered in determining the fault location. An example of the effect of neglecting the presence of these loads is discussed. The fault location techniques are based on both the apparent impedance concept and the use of the three-phase voltage and current phasors. A test case with the exact fault location is presented. The techniques were developed on an IBM PC. >

An efficient non-enumerative method to estimate path delay fault coverage

Abstract: A method to estimate the coverage of path delay faults of a given test set, without enumerating paths, is proposed. The method is polynomial in the number of lines in the circuit, and thus allows circuits with large numbers of paths to be considered under the path delay fault model. Several levels of approximation, with increasing accuracy and increasing polynomial complexity, are proposed. Experimental results are presented to show the effectiveness and accuracy of the estimate in evaluating the path delay fault coverage. Combining this nonenumerative estimation method with a test generation method for path delay faults would yield a cost effective method to consider path delay faults in large circuits, which are beyond the capabilities of existing test generation and fault simulation procedures, that are based on enumeration of paths.

Fault injection for the formal testing of fault tolerance

Abstract: The authors address the issue of the use of fault injection for explicitly removing design/implementation faults in fault tolerance algorithms and mechanisms. A formalism is introduced that represents the fault tolerance algorithms and mechanisms by means of a set of assertions. This formalism enables the execution tree to be presented, where each path from the root to a leaf of the tree is a well-defined formula. It provides a framework for the generation of a functional deterministic test for programs implementing complex fault tolerance algorithms and mechanisms. This methodology has been used to extend a debugging tool aimed at testing fault tolerance protocols developed by BULL France. It has been successfully applied to the injection of faults in the inter-replica protocol supporting the application-level fault tolerance features of the architecture of the ESPRIT-funded Delta-4 project. The results of these experiments are discussed and analyzed. >

Advanced fault collapsing (logic circuits testing)

Abstract: The partitioning of faults into equivalence classes so that only one representative fault per class must be explicitly considered in fault simulation and test generation, called fault collapsing, is addressed. Two types of equivalence, which are relevant to the work reported, are summarized. New theorems on fault equivalence and dominance, forming the basis of an algorithm that collapses all the structurally equivalent faults in a circuit, plus many of the functionally equivalent faults, are presented. Application of the algorithm to a set of benchmark circuits establishes that identification of functionally equivalent faults is feasible, and that, in some cases, they are a large fraction of the faults in a circuit. The collapsing algorithm applies not only to combinational designs but to synchronous sequential circuits as well. >

Parallel-processing techniques for automatic test pattern generation

Abstract: Some of the more widely used serial automatic test pattern generation (ATPG) algorithms and their stability for implementation on a parallel machine are discussed. The basic classes of parallel machines are examined to determine what characteristics they require of an algorithm if they are to implement it efficiently. Several techniques that have been used to parallelize ATPG are presented. They fall into five major categories: fault partitioning, heuristic parallelization, search-space partitioning, functional (algorithmic) partitioning, and topological partitioning. In each category, an overview is given of the technique, its advantages and disadvantages, the type of parallel machine it has been implemented on, and the results. >

Delay-fault diagnosis by critical-path tracing

Abstract: A delay fault diagnosis process consisting of simulation of the fault-free circuit with a four-valued logic algebra and critical-path tracing from primary outputs to primary inputs is presented. An alternative to fault simulation, the method requires no delay-size-based fault models and considers only the fault-free circuit. A sensitivity analysis process for improving diagnosis accuracy is also presented. >