Showing papers on "Stuck-at fault published in 1993"

Carafe: an inductive fault analysis tool for CMOS VLSI circuits

Abstract: Traditional fault models for testing CMOS VLSI circuits do not take into account the actual mechanisms that precipitate faults in CMOS circuits. As a result, tests based on traditional fault models may not detect all the faults that occur in the circuit. This paper discusses the Carafe software package which determines which faults are likely to occur in a circuit based on the circuit's physical design, defect parameters, and fabrication technology. >

Transition fault testing for sequential circuits

Abstract: Addresses the problem of simulating and generating tests for transition faults in nonscan and partial scan synchronous sequential circuits. A transition fault model for sequential circuits is first proposed. In this fault model, a transition fault is characterized by the fault site, the fault type, and the fault size. The fault type is either slow-to-rise or slow-to-fall. The fault size is specified in units of clock cycles. Fault simulation and test generation algorithms for this fault model are presented. The fault simulation algorithm is a modification of PROOFS, a parallel, differential fault simulation algorithm for stuck faults. Experimental results show that neither a comprehensive functional verification sequence nor a test sequence generated by a sequential circuit test generator for stuck faults produces a high fault coverage for transition faults. Deterministic test generation for transition faults is required to raise the coverage to a reasonable level. With the use of a novel fault injection technique, tests for transition faults can be generated by using a stuck fault test generation algorithm with some modifications. Experimental results for ISCAS-89 benchmark circuits and some AT&T designs are presented. Modifications to test generation and fault simulation algorithms required for partial scan circuits are presented. Experimental results on large benchmark circuits show that a high transition fault coverage can be achieved for the partial scan circuits designed using the cycle breaking technique. >

Fault-based automatic test generator for linear analog circuits

Abstract: Recognizing that specification testing of analog circuits involves a high cost and lacks any quantitative measure of the testing process, we adopt a fault-based technique. With the help of hierarchical fault models for parametric and catastrophic faults, and a very efficient fault simulator, our simulation-assisted technique automatically determines the test frequencies to detect AC faults in linear analog circuits. By a suitable choice of parameters in the test generator, we can either determine the best test (maximize the error between the good and the faulty responses) for every fault (resulting in a large test set), or generate the smallest test set for all the faults. Finally, fault coverage values provide a quantitative evaluation of the final test set.

An analysis of test data selection criteria using the RELAY model of fault detection

Abstract: RELAY is a model of faults and failures that defines failure conditions, which describe test data for which execution will guarantee that a fault originates erroneous behavior that also transfers through computations and information flow until a failure is revealed. This model of fault detection provides a framework within which other testing criteria's capabilities can be evaluated. Three test data selection criteria that detect faults in six fault classes are analyzed. This analysis shows that none of these criteria is capable of guaranteeing detection for these fault classes and points out two major weaknesses of these criteria. The first weakness is that the criteria do not consider the potential unsatisfiability of their rules. Each criterion includes rules that are sufficient to cause potential failures for some fault classes, yet when such rules are unsatisfiable, many faults may remain undetected. Their second weakness is failure to integrate their proposed rules. >

Computational complexity issues in operative diagnosis of graph-based systems

Abstract: Systems that can be modeled as graphs, such that nodes represent the components and the edges represent the fault propagation between the components, are considered. Some components are equipped with alarms that ring in response to faulty conditions. In these systems, two types of problem are studies: fault diagnosis and alarm placement. The fault diagnosis problems deal with computing the set of all potential failure sources that correspond to a set of ringing alarms. Single faults, where exactly one component can become faulty at any time, are primarily considered. Systems are classified into zero-time and non-zero-time systems on the basis of fault propagation time. The latter are further classified on the basis of knowledge of propagation times. For each of these classes algorithms are presented for single fault diagnosis. The problem of detecting multiple faults is shown to be NP-complete. An alarm placement problem that requires a single fault to be uniquely diagnosed is examined. >

Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits

Abstract: New cost-effective heuristics for the generation of small test sets are introduced, and heuristics proposed previously are enhanced. An improved procedure is also proposed for computing independent fault sets which are used to selecet target faults in test generation. The procedure results in large lower bounds on the minimum test set size. Experimental results of test generation demonstrate the effectiveness of the heuristics.

Delay Fault Coverage and Performance Tradeoffs

Abstract: The main disadvantage of the path delay fault model is that to achieve 100% testability every path must be tested. Since the number of paths is usually exponential in circuit size, all known analysis and synthesis techniques for 100% path delay fault testability are infeasible on most circuits. In this paper, we show that 100% delay fault testability is not necessary to guarantee the speed of a combinational circuit. There exist path delay faults which can never impact the circuit delay (computed using any correct timing analysis method) unless some other path delay faults also affect it; hence these delay faults need not be considered in delay fault testing. Next, assuming only the existence of robust delay fault tests for a very small set of paths, we show how the circuit speed can be selected such that 100% robust delay fault coverage is achieved.

Automatic fault location system

Abstract: A fault location system comprises voltage/current transducers 10A, 10B located at terminals A and B, respectively; digital relays 12A and 12B respectively coupled to transducer blocks 10A and 10B; and a fault location estimation processor 14, which may comprise a substation controller at substation S A or substation S B , a relay at A or B, a stand alone computer at A or B, or a computer at a central location. The digital relays receive analog voltage and current signals (V A , I A , V B , I B ) from the respective transducers and output digital phasor or oscillographic data to the fault location estimation block. The fault location estimation block is programmed to provide the fault location parameter m. The fault location estimation provided by the inventive technique is unaffected by the fault resistance, load current, mutual coupling effects from a parallel line, uncertainties in zero sequence values, shunt elements, and X/R characteristic of the system. The fault location can be estimated accurately even in cases of substantial resistance and load flow. In addition, the invention does not require synchronization of the data received from the respective A and B terminals, nor does it require pre-fault data or fault type selection.

Generating test cases for EFSM with given fault models

Abstract: A test case generation method is proposed for the conformance testing of communication protocols. Given a protocol specification and a fault model, both specified by extended finite state machines (EFSMs), the proposed method generates test cases that detect the given faults. A theoretical model is proposed to describe the dynamic properties of EFSMs. Test cases can be generated by analyzing the differences in the dynamic properties between the specification and the fault models. >

CMOS Brid es and Resistive Transistor Faults: I B DQ versus Delay Effects

Abstract: Beyond the static stuck-at fault model, delay fault testing and static overcurrent testing have been suggested as approaches yielding reasonable fault coverage in CMOS circuits. Based on detailed simulations of resistive stuck-on-, stuckopen-, and bridging faults for typical CMOS circuits, this paper presents an analysis of their detectability and requirements for current and timing resolutions in overcurrent and delay fault testing.

How To Do Weighted Random Testing For Bist

Abstract: In this paper, a strategy as proposed whach takes into account all aspects of wezghted random testzng for BIST. Our approach arwes from results concernzng the ampact of wezght roundang and a new combznataon of known technzques lake couplzng unweaghted and weighted pattern generatzon, basang weaght calculatzon on a precomputed test [2, 61, numerical maxzmazataon of pattern coverage [4], GURT-like hardware amplementatzon [lo], and avozdzng auto-correlataons. As an empiracal evaluation, we examzned the only random pattern resastant ISCAS 85 benchmarks c2670 and c7552. For these ctrcuats, 100% fault coverage was achieved after a total of 16,000 and 256,000 patterns, respectively. The hardware overhead compared to a pure random test as less than 2.5%.

CMOS bridges and resistive transistor faults: IDDQ versus delay effects

Abstract: Beyond the static stuck-at fault model, delay fault testing and static overcurrent testing have been suggested as approaches yielding reasonable fault coverage in CMOS circuits. Based on detailed simulations of resistive stuck-on-, stuck-open-, and bridging faults for typical CMOS circuits, this paper presents an analysis of their detectability and requirements for current and timing resolutions in overcurrent and delay fault testing. >

Multiple fault analog circuit testing by sensitivity analysis

Abstract: Analog circuit testing is considered to be a very difficult task. This difficulty is mainly due to the lack of fault models and accessibility to internal nodes. To overcome this problem, an approach is presented for analog circuit modeling and testing. The circuit modeling is based on first-order sensitivity computation. The testability of the circuit is analyzed by the multiple-fault model and by functional testing. Component deviations are deduced by measuring a number of output parameters, and through sensitivity analysis and tolerance computation. Using this approach, adequate tests are identified for testing catastrophic and soft faults. Some experimental results are presented for simple models as well as multiple-fault models.

Non-Scan Design-for-Testability Techniques for Sequential Circuits

Abstract: Recent studies show that a stuck-at test applied at the operational speed of the circuit identifies more defective chips than a test having the same fault coverage but applied at a lower speed. In this work, we investigate various design-for-testability (DFT) techniques for sequential circuits which permit at-speed application of tests while providing for very high fault coverage. The method involves parallel loading of flip-flops in test mode for enhanced controllability combined with probe point insertion for enhanced observability. Selection of candidate flip-flops and probe points is determined automatically by our OPUS-NS tool. Fault coverage and ATG effectiveness improved to greater than 96% and 99.7%, respectively, for the ISCAS89 sequential benchmark circuits studied when these non-scan DFT techniques were used.

Fault injection using boundary scan

Abstract: A system and method for fault injection utilizing boundary scan includes the provision of an additional fault injection register to the standard JTAG architecture in order to allow the intentional introduction of faults into a device or module forming part of a system under test. Through the use of the fault injection register of the present invention, faults may be intentionally introduced and the system response to such faults monitored and analyzed independently of the system software and without the use of mechanical probes or the like for introducing the fault. The system and method of the present invention is readily integrated with the existing test functions of the standard IEEE 1149.1 boundary scan architecture.

Model based alarm coordination

Abstract: A model-based alarm coordination system coordinates primary and secondary alarm notifications in order to ascertain whether they are caused by a single fault, or multiple faults, in a complex electrical system. The alarm coordination function is part of a larger overall Fault Management Support (FMS) system. The FMS system is a framework that, when combined with object-specific fault management parts, offers uniform fault management functions to managed objects (MOs) within the electrical system. Each MO is viewed as a self-contained, functional unit, and is responsible for its own internal fault management. Therefore, there are no global or centralized fault management functions. Object relation models, based on functional dependencies between objects, are used to automatically solve the alarm coordination problem which arises when a large number of faults are reported in response to a single fault which causes out-of-specification performance in many dependent objects. Little object-specific programming is required.

Fault simulation of linear analog circuits

Abstract: Research in the areas of analog circuit fault simulation and test generation has not achieved the same degree of success as its digital counterpart owing to the difficulty in modeling the more complex analog behavior. This article presents a novel approach to this problem by mapping the good and faulty circuits to thediscrete Zdomain. An efficient fault simulation is then performed on this discretized circuit for the given input test wave form. This simulator provides an order of magnitude speedup over traditional circuit simulators. An efficient fault simulator and the formulation of analog fault models opens up the ground for analog automatic test generation.

DRAFTS: Discretized Analog Circuit Fault Simulator

Abstract: The areas of analog circuit fault simulation and test generation have not achieved the same degree of success as their digital counterparts owing to the difficulty in modeling the more complex analog behavior. We present a novel approach to this problem by mapping the circuit and circuit-level faults to the discrete domain. An efficient fault simulation is then performed on this discretized circuit for the given input test waveform.

Generating tests for delay faults in nonscan circuits

Abstract: A delay test method that allows any sequential-circuit test generation program to produce path delay tests for nonscan circuits is presented. Using this method, a given path is tested by augmenting the netlist model of the circuit with a logic block, in which testing for a certain single stuck-at fault is equivalent to testing for a path delay fault. The test sequence for the stuck-at fault performs all the necessary delay fault test functions: initialization, path activation, and fault propagation. Results on benchmarks are presented for nonscan and scan/hold modes of testing. >

A fast and accurate gate-level transient fault simulation environment

Abstract: Mixed analog and digital mode simulators have been available for accurate transient fault simulation. However, they are not fast enough to simulate a large number of transient faults on a relatively large circuit in a reasonable amount of time. The authors describe a gate-level transient fault simulation environment which has been developed based on realistic fault models. The simulation environment uses a timing fault simulator as well as a zero-delay parallel fault simulator. The timing fault simulator uses high level models of the actual transient fault phenomenon and latch operation to accurately propagate the fault effects to the latch outputs, after which point the zero-delay parallel fault simulator is used to speed up the simulation without any loss in accuracy. The simulation environment is demonstrated on ISCAS-89 sequential benchmark circuits.

Quality and single-stuck faults

Abstract: The goal of IC production test is to avoid selling bad parts. The goal of fault grading is to assure that the test is so thorough that only an acceptably small fraction of shipped parts are bad. Fault grading is almost always based on a single-stuck fault, ssf, model. >

Simulation and generation of I/sub DDQ/ tests for bridging faults in combinational circuits

Abstract: In the absence of information about the layout and for better defect coverage test generation and fault simulation systems must target all bridging faults. The authors show that an I/sub DDQ/ Test Set that detects all two line bridging faults also detects all multiple line, single cluster bridging faults. A novel algorithm for simulating I/sub DDQ/ tests for all two-line bridging faults in combinational circuits is presented. Experimental results on using randomly generated I/sub DDQ/ test sets for detecting bridging faults are presented. These results point to the computational feasibility of targeting all two line bridging faults in combinational circuits, for the purpose of I/sub DDQ/ test generation. >

Distributed on-line diagnosis in the presence of arbitrary faults

Abstract: This paper introduces a new fault model for system-level diagnosis and a class of online distributed diagnosis algorithms that operate correctly in the presence of fault nodes that disseminate arbitrarily corrupted diagnostic information. The fault model addresses the practical issue of designing an internode test to cover diagnosis algorithm operation. Since an explicit test to detect arbitrary failures is not practical, evidence of a node's faulty behavior is provided by examining diagnositic messages exchanged by the node. In many practical systems, algorithm overhead using the new fault model is only twice that required for algorithms using the PMC fault model. The key results include a description of the new fault model, the specification of a class of online distributed diagnosis algorithms that use this fault model, and proofs of their correctness.

Design of self-testing and on-line fault detection combinational circuits with weakly independent outputs

Abstract: In this article we propose a structure dependent method for the systematic design of combinational selftesting fault detection circuits that is well adapted to the arbitrarily chosen technical fault model. According to the fault model considered the outputs of the circuit are partitioned into different generally nondisjoint groups of weakly independent outputs. The parities of these groups of weakly independent outputs are compared in test mode as well as in normal operation mode with the corresponding predicted parities by use of a self-checking checker. For on-line detection, the hardware is in normal operation mode, and for testing, it is in test mode. In the test mode, these fault detection circuits guarantee a 100% fault coverage for single stuck-at-0/1 faults and a high fault coverage for arbitrary faults. In normal operation mode all technical faults considered will be detected possibly, with some degree of latency.

NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits

Abstract: A test generation procedure for path delay faults is proposed, that targets all path delay faults in the circuit-under-test The procedure overcomes the difficulties in handling the exorbitant numbers of path delay faults in practical circuits by using a non-enumerative method of considering faults, ie, it never explicitly targets any specific path delay fault Experimental results demonstrate the effectiveness of the method in deriving tests to detect very large numbers of path delay faults in short run times

Method of finding faults in a branched electrical distribution circuit

Abstract: A PN modulated signal is applied to an end of a network electrical distribution circuit The signal produces a snapshot trace of energy reflected from various discontinuities along the circuit, including a fault Because the fault absorbs a large part of the energy in the applied signal, reflections from discontinuities in the same branch as the fault but farther from the input are reduced in amplitude By knowing the position of the branches and various discontinuities, such as transformers, the position of the fault can be logically determined If the fault is a high resistance fault a high voltage pulse is applied to the end of the circuit The PN signal is initially sensed at a time when the fault has a low resistance because of arcing due to the high voltage pulse

Validating Safety Models with Fault Trees

Abstract: In verifying a safety-critical system, one usually begins by building a model of the basic system and of its safety mechanisms. If the basic system model does not reflect reality, the verification results are misleading. We show how a model of a system can be compared with the system’s fault trees to help validate the failure behaviour of the model. To do this, the meaning of fault trees are formalised in temporal logic and a consistency relation between models and fault trees is defined. An important practical feature of the technique is that it allows models and fault trees to be compared even if some events in the fault tree are not found in the system model.

A comparison of stuck-at fault coverage and I/sub DDQ/ testing on defect levels

Abstract: This paper presents experimental data comparing the effect of functional stuck-at fault testing and I/sub DDQ/ testing on defect levels. Results obtained for parts tested with varying stuck-at fault coverage are compared with results from I/sub DDQ/ testing. Empirical data are analyzed against two theoretical fault models to demonstrate that correlation can be obtained. The results indicate that significant benefits can be gained from I/sub DDQ/ testing, even with non-deterministic test locations and relatively few measurements. Data are also presented on the impact of I/sub DDQ/ testing on burn-in monitoring and customer field failures of ASIC designs. Finally some practical issues associated with implementing I/sub DDQ/ tests are discussed. >