Showing papers on "Stuck-at fault published in 1997"

Automated fault location and diagnosis on electric power distribution feeders

Abstract: This paper presents new techniques for locating and diagnosing faults on electric power distribution feeders. The proposed fault location and diagnosis scheme is capable of accurately identifying the location of a fault upon its occurrence, based on the integration of information available from disturbance recording devices with knowledge contained in a distribution feeder database. The developed fault location and diagnosis system can also be applied to the investigation of temporary faults that may not result in a blown fuse. The proposed fault location algorithm is based on the steady-state analysis of the faulted distribution network. To deal with the uncertainties inherent in the system modeling and the phasor estimation, the fault location algorithm has been adapted to estimate fault regions based on probabilistic modeling and analysis. Since the distribution feeder is a radial network, multiple possibilities of fault locations could be computed with measurements available only at the substation. To identify the actual fault location, a fault diagnosis algorithm has been developed to prune down and rank the possible fault locations by integrating the available pieces of evidence. Testing of the developed fault location and diagnosis system using field data has demonstrated its potential for practical use.

System for locating faults and estimating fault resistance in distribution networks with tapped loads

Abstract: Both fault location and fault resistance of a fault are calculated by the present method and system. The method and system take into account the effects of fault resistance and load flow, thereby more accurately calculating fault resistance by taking into consideration the current flowing through the distribution network as well as the effect of fault impedance. A direct method calculates fault location and fault resistance directly while an iterative fashion method utilizes simpler calculations in an iterative fashion which first assumes that the phase angle of the current distribution factor Ds is zero, calculates an estimate of fault location utilizing this assumption, and then iteratively calculates a new value of the phase angle βs of the current distribution factor Ds and fault location m until a sufficiently accurate determination of fault location is ascertained. Fault resistance is then calculated based upon the calculated fault location. The techniques are equally applicable to a three-phase system once fault type is identified.

Automatic fault detection, isolation, and recovery in transparent all-optical networks

Abstract: Network fault identification is an important network management function, which is closely related to fault management and has an impact on other network management functions such as configuration management, and performance management. This paper investigates fault surveillance and fault identification mechanisms for a transparent optical network in which data travels optically from the source node to the destination node without going through any optical-to-electrical (O/E) or electrical-to-optical (E/O) conversion. Mechanisms and algorithms are proposed to detect and isolate faults such as fiber cuts, laser, receiver, or router failures. These mechanisms allow nonintrusive device monitoring without requiring any prior knowledge of the actual protocols being used in the data transmission.

An expert system for fault section diagnosis of power systems using fuzzy relations

Abstract: This paper proposes an expert system using fuzzy relations to deal with uncertainties imposed on fault section diagnoses of power systems. The authors build sagittal diagrams which represent the fuzzy relations for power systems, and diagnose fault sections using the sagittal diagrams. Next, they examine the malfunction or false alarms of relays and circuit breakers based on the alarm information and the estimated fault section. The proposed system provides the fault section candidates in terms of the degree of membership and the malfunction or false alarm. An operator monitors these candidates and is able to diagnose the fault section, coping with uncertainties. Experimental studies for real power systems reveal the usefulness of the proposed technique to diagnose faults that have uncertainty.

Fault-secure parity prediction arithmetic operators

Abstract: Although parity prediction arithmetic operators are compatible with systems checked by parity codes, they are not secure against single faults. The authors determine the necessary conditions for fault secureness and derive designs embodying these conditions.

Improved accuracy in quantitative fault tree analysis

Abstract: The fault tree diagram defines the causes of the system failure mode or 'top event' in terms of the component failures and human errors, represented by basic events. By providing information which enables the basic event probability to be calculated, the fault tree can then be quantified to yield reliability parameters for the system. Fault tree quantification enables the probability of the top event to be calculated and in addition its failure rate and expected number of occurrences. Importance measures which signify the contribution each basic event makes to system failure can also be determined. Owing to the large number of failure combinations (minimal cut sets) which generally result from a fault tree study, it is not possible using conventional techniques to calculate these parameters exactly and approximations are required. The approximations usually rely on the basic events having a small likelihood of occurrence. When this condition is not met, it can result in large inaccuracies. These problems can be overcome by employing the binary decision diagram (BDD) approach. This method converts the fault tree diagram into a format which encodes Shannon's decomposition and allows the exact failure probability to be determined in a very efficient calculation procedure. This paper describes how the BDD method can be employed in fault tree quantification.

Method and apparatus for recovering from software faults

Abstract: A method for recovering from software fault in a fault tolerant computing system includes a system status recording step to record the system status at the occurrence of the above software fault when the above fault is judged to be a software fault by a fault identifying step, a software fault factor diagnosing step to diagnose the fault factor of the above software fault, a software fault recovery action determining step to determine a recovery action to the above fault factor of the above software fault, and a software fault recovery action executing step to execute the recovery action the above fault factor of the above software fault determined by the above software fault recovery action determining step after roll back.

Fault diagnosis and temperature sensor recovery for an air-handling unit

Abstract: The presence of faults and the influence they have on system operation is a real concern in the heating, ventilating, and air-conditioning (HVAC) community. A fault can be defined as an inadmissible or unacceptable property of a system or a component. Unless corrected, faults can lead to increased energy use, shorter equipment life, and uncomfortable and/or unhealthy conditions for building occupants. This paper describes the use of a two-stage artificial neural network for fault diagnosis in a simulated air-handling unit. The stage one neural network is trained to identify the subsystem in which a fault occurs. The stage two neural network is trained to diagnose the specific cause of a fault at the subsystem level. Regression equations for the supply and mixed-air temperatures are obtained from simulation data and are used to compute input parameters to the neutral networks. Simulation results are presented that demonstrate that, after a successful diagnosis of a supply air temperature sensor fault, the recovered estimate of the supply air temperature obtained from the regression equation can be used in a feedback control loop to bring the supply air temperature back to the setpoint value. Results are also presented that illustrate the evolution of the diagnosismore » of the two-stage artificial neural network from normal operation to various fault modes of operation.« less

Properties of the input pattern fault model

Abstract: Recent work in IC failure analysis strongly indicates the need for fault models that directly analyze the function of circuit primitives. The input pattern (IP) fault model is a functional fault model that allows for both complete and partial functional verification of every circuit module, independent of the design level. We describe the IP fault model and provide a method for analyzing IP faults using standard SSL-based fault simulators and test generation tools. The method is used to generate test sets that target the IP faults of the ISCAS85 benchmark circuits and a carry-lookahead adder. Improved IP fault coverage for the benchmarks and the adder is obtained by adding a small number of test patterns to tests that target only SSL faults. We also conducted fault simulation experiments that show IP test patterns are effective in detecting non-targeted faults such as bridging and transistor stuck-on faults. Finally, we discuss the notion of IP redundancy and show how large amounts of this redundancy exist in the benchmarks and in SSL-irredundant adder circuits.

Parametric and catastrophic fault coverage of analog circuits in oscillation-test methodology

Abstract: This paper investigates parametric and catastrophic fault coverage of the oscillation-test strategy. A set of definitions to evaluate the efficiency of a test technique and to quantify the parametric fault coverage is therefore introduced. The oscillation-test strategy is a low-cost and practical test method which is very efficient for built-in self-testing of mixed-signal integrated circuits. Active analog filters are used as test vehicle and therefore design for testability techniques to convert them to oscillators have been presented. Discrete practical realizations and extensive simulations based on CMOS 1.2 /spl mu/m technology parameters affirm that the test technique presented for active analog filters ensures high fault coverage and requires a negligible area overhead.

One-terminal fault location system that corrects for fault resistance effects

Abstract: A one-terminal process for locating a fault associated with a multi-phase electric power transmission system is disclosed. The process is based on the principle that the impedance in a fault can be determined by correcting errors due to the interaction of fault resistance and load current. The fault may be a phase-to-ground fault or a multiple-phase fault.

Hierarchical specification-driven analog fault modeling for efficient fault simulation and diagnosis

Abstract: In this paper we discuss the capabilities of the MiST PROFIT (Mixed Signal Test Program for Fault Insertion and Testing) software for hierarchical fault modeling, tolerance modeling, fault clustering and fault diagnosis of complex mixed-signal systems. The software is designed to exploit the relationships between high level system specifications and module-level faults in complex and nonlinear mixed signal systems. Hierarchical simulation based methods are used to capture fault effects at different levels of circuit abstraction. The key features of our approach are: (a) the ability to compute tolerance effects from nonlinear behavioral models at different levels of circuit design hierarchy accurately using low-cost simulation based methods, (b) the ability to perform compaction of fault effects while transferring fault effects from the leaf cells to the highest level behavioral models, (c) the ability to capture parametric (soft) failure effects over the entire anticipated range of faulty parameter values and (d) the ability to construct fault dictionaries given a set of least replaceable units to diagnose.

An interactive approach to fault location on overhead distribution lines with load taps

Abstract: This paper presents a novel technique in single-ended fault location for overhead distribution systems based on the concept of superimposed components of voltages and currents rather than total quantities. It is shown that the fault locator is highly insensitive to variations in source impedances (both local and remote) and to the presence of taps with variable loads; this permits accurate fault location under a much wider range of system/fault conditions than has hitherto been possible.

Fast algorithms for static compaction of sequential circuit test vectors

Abstract: Two fast algorithms for static test sequence compaction are proposed for sequential circuits. The algorithms are based on the observation that test sequences traverse through a small set of states, and some states are frequently re-visited throughout the application of a test set. Subsequences that start and end on the same states may be removed if necessary and sufficient conditions are met for them. The techniques require only two fault simulation passes and are applied to test sequences generated by various test generators, resulting in significant compactions very quickly for circuits that have many revisited states.

Generation and verification of tests for analogue circuits subject to process parameter deviations

Abstract: The paper presents a test pattern generation and fault simulation methodology for the detection of catastrophic faults in analogue circuits. The test methodology chosen for evaluation is RMS AC supply current monitoring. Tests are generated and evaluated taking account of the potential fault masking effects of process spread on the faulty circuit responses. A new test effectiveness metric of probability of detection is defined and the application of the technique to an analogue multiplier circuit is presented. The fault coverage figures are therefore more meaningful than those obtained with a fixed threshold, although they appear lower.

On the fault coverage of gate delay fault detecting tests

Abstract: This paper addresses the problem of obtaining accurate fault coverages for the gate delay fault model. For a gate delay fault, it is not sufficient to only find a test. One also has to accurately determine the size of the fault detected. We first show that previous methodologies for determining gate delay fault coverages have certain limitations. A method is then investigated to determine all the possible ranges of detected fault sizes, using the traditional fixed sampling time approach. However, with the constraints of a realistic inertial delay model, it is then shown that it might still not be possible to achieve the coverages required to guarantee circuit operation without malfunctions. A new and more realistic delay model is proposed to obtain true fault coverages that extend up to the actual circuit slacks whenever possible. An alternate test application strategy, involving the usage of varying sampling times, is also proposed to further enhance the actual fault coverages obtained under the proposed delay model. Results of experiments performed to evaluate these methods are given.

A novel fault locator based on the detection of fault generated high frequency transients

Abstract: Contemporary methods for fault location on overhead lines and underground cables can be classified into two fundamental types: (i) methods based on the measurement of post-fault line impedance; and (ii) methods based on the measurement of the fault generated travelling wave component. This paper presents the application of these new techniques to fault location on transmission and distribution line/cable systems. The technique utilises the specially designed fault locators to capture the fault generated high frequency voltage or current transient signals from the faulted line/cable. The propagation time of the high frequency components is used to determine the fault position.

Application and analysis of IDDQ diagnostic software

Abstract: A current disadvantage of IDDq testing is lack of software-based diagnostic tools that enable IC vendors to create a large database of defects uniquely detected with this test method. We present a methodology for performing defect localization based upon IDDq test information (only). Using this technique, fault localization can be completed within minutes (e.g. <5 minutes) after IC testing is complete. This technique supports multiple fault models and has been successfully applied to a large number of samples-including ones that have been verified through failure analysis. Data is presented related to key issues such as diagnostic resolution, hardware-to-fault model correlation, diagnostic current thresholds, and the diagnosability of various defect types.

Design for testability and built-in self-test of mixed-signal circuits: a tutorial

Abstract: The advent of new electronic packaging technologies has fueled the drive towards rapid integration of digital and analog functions particularly in portable computing and communications applications. This integration of digital and analog circuits into closely coupled mixed-signal circuits has brought with it, many challenges in the design and test areas. The problem in testing mixed-signal circuits arises from the simple fact that digital and analog fault models are inherently different. Moreover, while digital fault models are well understood (i.e. stuck-at faults), analog fault models are not quite as well-defined and mature. Another key problem stems from the fact that analog signals are inherently imprecise. Hence, with any analog measurement one must associate an accuracy of measurement. For large systems, it therefore becomes necessary to incorporate design for testability and built-in self-test (BIST) features in order to achieve high coverage of digital and analog faults. Also, with use of these features, fault simulation and test generation becomes easier. In the following paper, the authors discuss recent work in the area of design for testability and BIST.

Classification and Test Generation for Path-Delay FaultsUsing Single Struck-at Fault Tests

Abstract: We classify all path-delay faults of a combinational circuit into three categories: {\it singly-testable} (ST), {\it multiply-testable} (MT), and {\it singly-testable\ dependent} (ST-dependent). The classification uses any unaltered single stuck-at fault test generation tool. Only two runs of this tool on a model network derived from the original network are performed. As a by-product of this process, we generate single and multiple input change delay tests for all testable faults. With these tests, we expect that most defective circuits are identified. All ST faults are guaranteed detection in the case of a single fault, and some may be guaranteed detection through robust and validatable non-robust tests even in the case of multiple faults. An ST-dependent fault can affect the circuit speed only if certain ST faults are present. Thus, if all ST faults are tested, the ST-dependent faults need not be tested. MT faults cannot be guaranteed detection, but affect the speed only if delay faults simultaneously exist on a set of paths, none of which is ST. Examples and results on several ISCAS ‘89 benchmarks are presented. The method of classification through test generation using a model network is complex and can be applied to circuits of moderate size. For larger circuits, alternative methods will have to be explored in the future.

Modeling the unmodelable: algorithmic fault diagnosis

Abstract: Because defect behavior is so variable, a fault model always leaves some faults unmodeled. One solution is to use improved matching algorithms to diagnose complex behaviors even with inaccurate modeling.

Digital circuit test generator

Abstract: Automatic test pattern generator for generating test patterns that are capable of detecting faults in a digital combinational circuit comprises a first forward network capable of emulating the digital combinational circuit; a second forward network capable of emulating the digital combinational circuit in the presence of any one target fault from a specified set of faults, and receiving a set of control signals for selecting the target fault; a first backward network having one primary input for every primary output of the digital combinational circuit and one primary output for every primary input of the digital combinational circuit, the first backward network generating one fault activation objective corresponding to the selected target fault, and receiving first signal values computed in the first forward network for propagating the fault activation objective towards a primary output; a second backward network having one primary input for every primary output of the digital combinational circuit and one primary output for every primary input of the digital combinational circuit, the second backward network receiving second signal values computed in the second forward network for propagating the fault activation objective towards a primary output, both the first and second backward networks independently generating and propagating fault-effect propagation objectives towards one or more of its respective primary outputs; a first control device for generating the set of control signals corresponding to a target fault, and selecting the target fault one at a time from the specified set of target faults; means for merging one or more objectives propagated to the primary outputs of the first and second backward network; comparator device for comparing the first and second sets of primary output signals from each the first and second forward network in response to primary input signals, and determining whether at least one pair of corresponding primary outputs have different binary values and providing an output therefor; and, second control device for receiving the merged objectives from the backward network and the comparator output, and determining therefrom primary input values of the first and second forward network for detecting the target fault in the combinational digital circuit.

False write through and un-restored write electrical level fault models for SRAMs

Abstract: Static random access memory fault modeling typically is done at the functional level of abstraction. Electrical level simulations, however, demonstrate real fault models which were previously overlooked. False write through and un-restored write fault models are introduced. Two patterns are defined to identify such faults. Further benefits of electrical level fault modeling are discussed.

STARBIST: scan autocorrelated random pattern generation

Abstract: This paper presents a new scan-based BIST schemewhich achieves very high fault coverage without the deficienciesof previously proposed schemes. This approach utilizes scan orderand polarity in scan synthesis, effectively converting the scanchain into a ROM capable of storing some "center" patterns fromwhich the other vectors are derived by randomly complementingsome of their coordinates. Experimental results demonstrate that avery high fault coverage can be obtained without any modificationof the mission logic, no test data to store and very simple BISThardware which does not depend on the size of the circuit.

Adaptive ground and phase fault detection for a power distribution system

Abstract: An adaptive method and apparatus for detecting fault conditions in a power distribution system that services both single phase loads and three phase loads. The present invention accomplishes this by providing an adaptive ground fault detection method and an adaptive phase fault detection method. Both methods provide the capability to distinguish gradual changes in phase current, due to ordinary current fluctuations, from more substantial changes in phase current due to various fault conditions. By making this distinction, the present invention minimizes unnecessary service interruptions.

Diagnostic test pattern generation for sequential circuits

Abstract: A method to perform diagnostic test generation in sequential circuits by modifying a conventional test generator is presented. The method utilizes circuit netlist modification along with a forced value at primary input in the modified circuit techniques to reduce the computational effort for diagnostic test pattern generation in sequential circuits. Speed-up of the diagnostic ATPG process is achieved by the identification of states that are impossible to justify with three-valued logic.