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Showing papers on "Stuck-at fault published in 2000"


Journal ArticleDOI
TL;DR: This paper considers the application of a particular sliding mode observer to the problem of fault detection and isolation using the equivalent output injection concept to explicitly reconstruct fault signals.

1,141 citations


Journal ArticleDOI
TL;DR: In this article, the authors describe a potential fault-based attack where key bits leak only through the information whether the device produces a correct answer after a temporary fault or not, and this information is available to the adversary even if a check is performed before output.
Abstract: In order to avoid fault-based attacks on cryptographic security modules (e.g., smart-cards), some authors suggest that the computation results should be checked for faults before being transmitted. In this paper, we describe a potential fault-based attack where key bits leak only through the information whether the device produces a correct answer after a temporary fault or not. This information is available to the adversary even if a check is performed before output.

338 citations


Journal ArticleDOI
TL;DR: In this paper, a fault estimation and compensation method was proposed to compensate for actuator and sensor faults in highly automated systems. But the method is limited to the case when there is a complete loss of an actuator.
Abstract: The general fault-tolerant control method described in the article addresses actuator and sensor faults, which often affect highly automated systems. These faults correspond to a loss of actuator effectiveness or fault sensor measurements. After describing these faults, a fault estimation and compensation method was proposed. In addition to providing information to operators concerning the system operating conditions, the fault diagnosis module is especially important in fault-tolerant control systems where one needs to know exactly which element is faulty to react safely. The method's abilities to compensate for such faults are illustrated by applying it to a winding machine, which represents a subsystem of many industrial systems. The results show that once the fault is detected and isolated, it is easy to reduce its effect on the system, and process control is resumed with degraded performances close to nominal ones. Thus, stopping the system immediately can be avoided. However, the limits of this method are reached when there is the complete loss of an actuator. In this case, only a hardware redundancy is effective and could ensure performance reliability. The method proposed here assumes the availability of the state variables for measurement.

269 citations


Proceedings ArticleDOI
30 Apr 2000
TL;DR: Using this notation, the space of all possible memory faults has been constructed and it has been shown that this space is infinite, and contains the currently established fault models.
Abstract: This paper presents a notation for describing functional fault models, which may occur in memory devices. Using this notation, the space of all possible memory faults has been constructed. It has been shown that this space is infinite, and contains the currently established fault models. New fault models in this space have been identified and verified using resistive and capacitive defect injection and simulation of a DRAM model.

187 citations


Proceedings ArticleDOI
03 Oct 2000
TL;DR: The data presented shows that N-detect test sets are particularly effective for both timing and hard failures, and the use of IDDq tests and VLV tests for detecting defects whose presence doesn't interfere with normal operation during manufacturing test, but which cause early life failure.
Abstract: This paper studies some manufacturing test data collected for an experimental digital IC. Test results for a large variety of single-stuck fault based test sets are shown and compared with a number of test sets based on other fault models. The defects present in the chips studied are characterized based on the chip tester responses. The data presented shows that N-detect test sets are particularly effective for both timing and hard failures. In these test sets each single-stuck fault is detected by at least N different test patterns. We also present data on the use of IDDq tests and VLV (very low voltage) tests for detecting defects whose presence doesn't interfere with normal operation during manufacturing test, but which cause early life failure.

182 citations


Journal ArticleDOI
TL;DR: A novel method of detecting and unambiguously diagnosing the type and magnitude of three induction machine fault conditions from the single sensor measurement of the radial electromagnetic machine vibration is described.
Abstract: This paper describes a novel method of detecting and unambiguously diagnosing the type and magnitude of three induction machine fault conditions from the single sensor measurement of the radial electromagnetic machine vibration. The detection mechanism is based on the hypothesis that the induction machine can be considered as a simple system, and that the action of the fault conditions are to alter the output of the system in a characteristic and predictable fashion. Further, the change in output and fault condition can be correlated allowing explicit fault identification. Using this technique, there is no requirement for a priori data describing machine fault conditions, the method is equally applicable to both sinusoidally and inverter-fed induction machines and is generally invariant of both the induction machine load and speed. The detection mechanisms are rigorously examined theoretically and experimentally, and it is shown that a robust and reliable induction machine condition-monitoring system has been produced. Further, this technique is developed into a software-based automated commercially applicable system.

176 citations


Proceedings ArticleDOI
03 Oct 2000
TL;DR: A logic diagnosis tool with applicability to a spectrum of logic DFT, ATPG and test strategies including full/almost fullscan circuits with combinational ATPG, partial-scan and non-scan circuits in general and to functional patterns in general is presented.
Abstract: Logic fault diagnosis or fault isolation is the process of analyzing the failing logic portions of an integrated circuit to isolate the cause of failure. Fault diagnosis plays an important role in multiple applications at different stages of design and manufacturing. A logic diagnosis tool with applicability to a spectrum of logic DFT, ATPG and test strategies including full/almost fullscan circuits with combinational ATPG, partial-scan and non-scan circuits with sequential ATPG and to functional patterns in general is presented. Novel features incorporated into the tool include static and dynamic structural processing for partial-scan circuits, windowed fault simulation, and diagnostic models for open defects and cover algorithms for multiple fault diagnosis. Experimental results include simulation results on processor functional blocks and silicon results on chipsets and processors from artificially induced defects and production fallout.

157 citations


Proceedings ArticleDOI
17 Apr 2000
TL;DR: On-line, multi-level fault tolerant (FT) technique for system functions and applications mapped to partially and dynamically reconfigurable FPGAs based on the roving self testing areas (STARs) fault detection/location strategy.
Abstract: In this paper we present an on-line, multi-level fault tolerant (FT) technique for system functions and applications mapped to partially and dynamically reconfigurable FPGAs. Our method is based on the roving self testing areas (STARs) fault detection/location strategy presented in Abramovici et al. (1999). In STARs, the area under test uses partial reconfiguration properties to modify the configuration of the area under test without affecting the configuration of the system function and dynamic reconfiguration properties to allow uninterrupted execution of the system function while reconfiguration takes place. In this paper we take this one step further. Once a fault (or multiple faults) is detected we dynamically reconfigure the working area application around the fault with no additional system function interruption (other than the interruption when a STAR moves to a new location). We also apply the concept of partially usable blocks to increase fault tolerance. Our method has been successfully implemented and demonstrated on the ORCA 2CA series FPGAs from Lucent Technologies.

147 citations


Journal ArticleDOI
TL;DR: The paper presents a robust fault diagnosis scheme for detecting and approximating state and output faults occurring in a class of nonlinear multiinput-multioutput dynamical systems and demonstrates the theoretical results by a simulation example of a fourth-order satellite model.
Abstract: The paper presents a robust fault diagnosis scheme for detecting and approximating state and output faults occurring in a class of nonlinear multiinput-multioutput dynamical systems. Changes in the system dynamics due to a fault are modeled as nonlinear functions of the control input and measured output variables. Both state and output faults can be modeled as slowly developing (incipient) or abrupt, with each component of the state/output fault vector being represented by a separate time profile. The robust fault diagnosis scheme utilizes on-line approximators and adaptive nonlinear filtering techniques to obtain estimates of the fault functions. Robustness with respect to modeling uncertainties, fault sensitivity and stability properties of the learning scheme are rigorously derived and the theoretical results are illustrated by a simulation example of a fourth-order satellite model.

134 citations


Journal ArticleDOI
TL;DR: A class of count-and-threshold mechanisms, collectively named /spl alpha/-count, which are able to discriminate between transient faults and intermittent faults in computing systems and adopt a mathematically defined structure, which is simple enough to analyze by standard tools.
Abstract: This paper presents a class of count-and-threshold mechanisms, collectively named /spl alpha/-count, which are able to discriminate between transient faults and intermittent faults in computing systems. For many years, commercial systems have been using transient fault discrimination via threshold-based techniques. We aim to contribute to the utility of count-and-threshold schemes, by exploring their effects on the system. We adopt a mathematically defined structure, which is simple enough to analyze by standard tools. /spl alpha/-count is equipped with internal parameters that can be tuned to suit environmental variables (such as transient fault rate, intermittent fault occurrence patterns). We carried out an extensive behavior analysis for two versions of the count-and-threshold scheme, assuming, first, exponentially distributed fault occurrencies and, then, more realistic fault patterns.

129 citations


Proceedings ArticleDOI
Said Hamdioui1, A.J. Van De Goor1
04 Dec 2000
TL;DR: A new march test detecting all realistic faults, with a test length of 14n, will be introduced, and its fault coverage is compared with other known tests.
Abstract: In this paper a complete analysis of spot defects in industrial SRAMs will be presented. All possible defects are simulated, and the resulting electrical faults are transformed into functional fault models. The existence of the usually used theoretical memory fault models will be verified and new ones will be presented. Finally, a new march test detecting all realistic faults, with a test length of 14n, will be introduced, and its fault coverage is compared with other known tests.

Book ChapterDOI
19 Jun 2000
TL;DR: In this paper, a test suite is complete with respect to a given fault model when each implementation from the fault domain passes it if and only if the postulated conformance relation holds between the implementation and its specification.
Abstract: The annotated bibliography highlights work in the area of algorithmic test generation from formal specifications with guaranteed fault coverage, i.e., fault model-driven test derivation. A fault model is understood as a triple, comprising a finite state specification, conformance relation and fault domain that is the set of possible implementations. The fault model can be specialized to Input/Output FSM, Labeled Transition System, or Input/Output Automaton and to a number of conformance relations such as FSM equivalence, reduction or quasiequivalence, trace inclusion or trace equivalence and others. The fault domain usually reflects test assumptions, as an example, it can be the universe of all possible I/O FSMs with a given number of states, a classical fault domain in FSM-based testing. A test suite is complete with respect to a given fault model when each implementation from the fault domain passes it if and only if the postulated conformance relation holds between the implementation and its specification. A complete test suite is said to provide fault coverage guarantee for a given fault model.

Journal ArticleDOI
TL;DR: In this paper, a number of different fundamental problems in fault detection and fault identification are formulated and necessary and sufficient conditions for the solvability of the fundamental problems are derived, which are weaker than the ones found in the literature since we do not assume any particular structure for the residual generator.
Abstract: A number of different fundamental problems in fault detection and fault identification are formulated in this paper. The fundamental problems include exact, almost, generic and class-wise fault detection and identification. Necessary and sufficient conditions for the solvability of the fundamental problems are derived. These conditions are weaker than the ones found in the literature since we do not assume any particular structure for the residual generator. At the end of the paper, a time domain synthesis procedure based on state-space methods to construct appropriate residual generators is given. Copyright © 2000 John Wiley & Sons, Ltd.

Journal ArticleDOI
TL;DR: Polynomial time algorithms are proposed in this paper for the first time to generate minimal set of test nodes in analog circuit fault diagnosis and they are much faster than well-known methods.
Abstract: In this paper, the selection of test nodes has been studied extensively and efficient techniques are proposed. Two broad categories of methods called inclusion methods and exclusion methods are suggested. Strategies are presented to select or delete a test node without affecting the diagnosis capabilities. Examples show that these strategies give a lesser number of test nodes some times. Starting from the fault-wise integer coded table of the test circuit, sorting is employed to generate valid sets and minimal sets. The order of computation of these methods is shown to depend linearly on number of test nodes. It is also proportional to (f log f) where "f" is the number of faults. This is much faster than well-known methods. The concept of minimal set of test nodes is new in analog circuit fault diagnosis. Polynomial time algorithms are proposed in this paper for the first time to generate such sets.

Journal ArticleDOI
TL;DR: In this article, an accurate fault location algorithm for series compensated power transmission lines is presented, which makes use of two subroutines for estimation of the fault distance-one for faults behind the series capacitors and another one for faults in front of the series capacitor.
Abstract: In this paper, an accurate fault location algorithm for series compensated power transmission lines is presented. A distributed time domain model is used for modeling of the transmission lines. The algorithm makes use of two subroutines for estimation of the fault distance-one for faults behind the series capacitors and another one for faults in front of the series capacitors. Then a special procedure to select the correct solution is utilized. Samples of voltages and currents at both ends of the line are taken synchronously and used to calculate the location of the fault. The proposed algorithm is independent of fault resistance and does not require any knowledge of source impedance. The proposed method has been tested using the EMTP/ATP model of a 100 kV, 300 km transmission line, which is compensated, by a three-phase capacitor bank in the middle. The results of computer simulation confirm the accuracy of the proposed method.

Journal ArticleDOI
01 Aug 2000
TL;DR: In the first stage, the fault is detected on the basis of residuals generated from a bank of Kalman filters, while, in the second stage, fault identification is obtained from pattern recognition techniques implemented by Neural Networks.
Abstract: Fault diagnosis and identification (FDI) have been widely developed during recent years. Model-based methods, fault tree approaches and pattern recognition techniques are among the most common methodologies used in such tasks. Neural networks have been used in FDI problems for model approximation and pattern recognition as well. However, because of difficulties to perform Neural Network training on dynamic patterns, the second approach seems more adequate. In this paper, the FDI methodology consists of two stages. In the first stage, the fault is detected on the basis of residuals generated from a bank of Kalman filters, while, in the second stage, fault identification is obtained from pattern recognition techniques implemented by Neural Networks. The proposed fault diagnosis tool has been tested on a model of a power plant and results from simulations are reported and commented in the paper.

Patent
28 Nov 2000
TL;DR: In this article, a fault interrupter having a microcontroller is provided to detect actual faults and initiate a periodic self-test and provide external notification to the user upon successful or unsuccessful completion of the test.
Abstract: A fault interrupter having a microcontroller is provided to detect actual faults The fault interrupter initiates a periodic self-test and provides external notification to the user upon successful or unsuccessful completion of the test The fault interrupter generates the test signal at a selected time to substantially coincide with the zero-crossing of the AC power source A manual test can also be performed using a manual test switch provided as a direct input to the microcontroller

Journal ArticleDOI
TL;DR: In this article, two new fault point location algorithms are proposed for parallel double-circuit multi-terminal transmission lines by using voltages and currents information from CCVTs and CTs at all terminals.
Abstract: Two new methods are proposed for fault point location in parallel double-circuit multi-terminal transmission lines by using voltages and currents information from CCVTs and CTs at all terminal. These algorithms take advantage of the fact that the sum of currents flowing into a fault section equals the sum of the currents at all terminals. Algorithm 1 employs an impedance calculation and algorithm 2 employs the current diversion ratio method. Computer simulations are carried out and applications of the proposed methods are discussed. Both algorithms can be applied to all types of fault such as phase-to-ground and phase-to-phase faults. As one equation can be used for all types of fault, classification of fault types and selection of faulted phase are not required. Phase components of the line impedance are used directly, so compensation of unbalanced line impedance is not required.

Patent
27 Jul 2000
TL;DR: In this paper, a distributed method and system of controlling a communications network having a plurality of spans of interconnected network elements some of which include a network element processor distributes network topology information to respective span databases; stores original fault objects in the respective span database; advertises fault objects to other network element processors in a local span when the original fault affects network elements other than the network element in which the fault occurred.
Abstract: A distributed method and system of controlling a communications network having a plurality of spans of interconnected network elements some of which include a network element processor distributes network topology information to respective span databases; stores original fault objects in the respective span databases; advertises fault objects to other network element processors in a local span when the original fault affects network elements other than a network element in which the fault occurred; advertises alarm objects to other network element processors that are respectively associated with a circuit affected by the original faults; stores the advertised fault and alarm objects in the respective span databases; and performs distributed processing of the advertised fault and alarm objects with the other network element processors and the respective span databases. Aggregation of other faults and alarms that may be occurring on the communications network due to other faults other than the received fault aids in determining causality of the fault. Causality may be determined by correlating other faults and alarms with the received fault. If not a root cause of another fault or alarm, the received fault is sympathetic to another fault or alarm. Sympathetic faults are suppressed while root cause faults are promoted to an alarm and reported to affected network elements. The number of alarms viewed by a network manager as well as the reporting of alarms and underlying faults are reduced by performing such distributed alarm correlation and fault reporting suppression.

Journal ArticleDOI
TL;DR: In this paper, a fault transient detector unit at the relaying point is used to capture fault generated high frequency transient signals contained in the primary currents, and the decision to trip is based on the relative arrival times of these high frequency components as they propagate through the system.
Abstract: This paper presents a new technique for high-speed protection of transmission lines, the positional protection technique. The technique uses a fault transient detector unit at the relaying point to capture fault generated high frequency transient signals contained in the primary currents. The decision to trip is based on the relative arrival times of these high frequency components as they propagate through the system. Extensive simulation studies of technique were carried out to examine the response to different power system and fault conditions. Results show that the scheme is insensitive to fault type, fault resistance, fault inception angle and system source configuration, and that it is able to offer both very high accuracy and speed in fault detection.

Proceedings ArticleDOI
25 Oct 2000
TL;DR: Analyzing at an early stage of the design the potential faulty behaviors of a circuit becomes a major concern due to the increasing probability of faults using fault injections in RT-level VHDL descriptions and hardware prototyping of the circuit under design.
Abstract: Analyzing at an early stage of the design the potential faulty behaviors of a circuit becomes a major concern due to the increasing probability of faults. It is proposed to carry out such an analysis using fault injections in RT-level VHDL descriptions and hardware prototyping of the circuit under design. Injection of erroneous transitions is automated and results are presented.

Journal ArticleDOI
TL;DR: Radial basis functions networks (RBFN) are used to process circuit input–output measurements, and to perform soft fault location, and results show that the developed nets succeeded in classifying faults.

Proceedings ArticleDOI
08 Oct 2000
TL;DR: In this article, an on-line neural network based diagnostic scheme for induction machine stator winding turn fault detection is presented, consisting of a feed-forward neural network combined with a self-organizing feature map (SOFM) to visually display the operating condition of the machine on a two-dimensional grid.
Abstract: A novel on-line neural network based diagnostic scheme, for induction machine stator winding turn fault detection, is presented. The scheme consists of a feed-forward neural network combined with a self-organizing feature map (SOFM) to visually display the operating condition of the machine on a two-dimensional grid. The operating point moves to a specific region on the map as a fault starts developing and can be used to alert the motor protection system to an incipient fault. This is a useful tool for commercial condition monitoring systems. Experimental results are provided, with data obtained from a specially wound test motor, to illustrate the robustness of the proposed turn fault detection scheme. The new method is not sensitive to unbalanced supply voltages or asymmetries in the machine and instrumentation.

Patent
27 Jul 2000
TL;DR: In this article, a distributed method and system of controlling a communications network having a plurality of spans of interconnected network elements some of which include a network element processor distributes network topology information to respective span databases; stores original fault objects in the respective span database; advertises fault objects to other network element processors in a local span when the original fault affects network elements other than the network element in which the fault occurred.
Abstract: A distributed method and system of controlling a communications network having a plurality of spans of interconnected network elements some of which include a network element processor distributes network topology information to respective span databases; stores original fault objects in the respective span databases; advertises fault objects to other network element processors in a local span when the original fault affects network elements other than a network element in which the fault occurred; advertises alarm objects to other network element processors that are respectively associated with a circuit affected by the original faults; stores the advertised fault and alarm objects in the respective span databases; and performs distributed processing of the advertised fault and alarm objects with the other network element processors and the respective span databases. Aggregation of other faults and alarms that may be occurring on the communications network due to other faults other than the received fault aids in determining causality of the fault. Causality may be determined by correlating other faults and alarms with the received fault. If not a root cause of another fault or alarm, the received fault is sympathetic to another fault or alarm. Sympathetic faults are suppressed while root cause faults are promoted to an alarm and reported to affected network elements. The number of alarms viewed by a network manager as well as the reporting of alarms and underlying faults are reduced by performing such distributed alarm correlation and fault reporting suppression.

Proceedings ArticleDOI
03 Oct 2000
TL;DR: This paper presents the first BIST approach for testing interconnects of SRAM-based FPGAs using error control coding, which has superior multiple fault coverage on wire segment stuck-at, stuck-open and bridging faults, programmable switch stuck on/off faults, and the combinations of these faults in global routing resources.
Abstract: This paper presents the first BIST approach for testing interconnects of SRAM-based FPGAs using error control coding. The proposed scheme requires a total of six test configurations and has superior multiple fault coverage on wire segment stuck-at, stuck-open and bridging faults, programmable switch stuck on/off faults, and the combinations of these faults in global routing resources.

Journal ArticleDOI
TL;DR: In this paper, an improved fault location method based on the traveling wave theory of the transmission lines is presented. But the proposed method also takes advantage of the different travel times of the modal components in differentiating between close-in and remote end faults.

Journal ArticleDOI
TL;DR: In this article, the authors present a theoretical study of fault coupling, based on a simple model of fault-based testing, and the conclusion reached being that fault coupling only occurs infrequently.
Abstract: Fault coupling is the phenomenon whereby a test set is able to detect faults when they occur in isolation, but fails to do so when they occur in combination. It is widely regarded as a nuisance in fault-based approaches to software testing, which focus on the detection of single faults and normally neglect multiple faults. This paper presents a theoretical study of fault coupling, based on a simple model of fault-based testing. This provides for the presence of two faults that interact with each other and thus includes the possibility of fault coupling between them. The model is analysed mathematically, the conclusion reached being that fault coupling only occurs infrequently. This result provides support for current approaches to fault-based testing, but it is not quite enough to conclude that they are thereby validated. In effect, the paper generalizes the results of a previous paper that dealt with the restricted case where the functions underlying programs are bijective as well as finite. The restriction that functions be bijective is lifted here, but they are still required to be finite. Though the same theoretical framework is used in both cases, and more or less the same results are obtained, the techniques employed to arrive at the results in the general case are quite different. Copyright © 2000 John Wiley & Sons, Ltd.

Patent
18 Oct 2000
TL;DR: In this paper, the authors present a system for testing a computer system by using software to inject faults into the computer system while the system is operating, by allowing a programmer to include a fault point into source code for a program, which causes a fault to occur if a trigger associated with the fault point is set and if an execution path of the program passes through the fault points.
Abstract: One embodiment of the present invention provides a system for testing a computer system by using software to inject faults into the computer system while the computer system is operating. This system operates by allowing a programmer to include a fault point into source code for a program. This fault point causes a fault to occur if a trigger associated with the fault point is set and if an execution path of the program passes through the fault point. The system allows this source code to be compiled into executable code. Next, the system allows the computer system to be tested. This testing involves setting the trigger for the fault point, and then executing the executable code, so that the fault occurs if the execution path passes through the fault point. This testing also involves examining the result of the execution. In one embodiment of the present invention, if the fault point is encountered while executing the executable code, the system executes the fault point by: looking up a trigger associated with the fault point; determining whether the trigger has been set; and executing code associated with the fault point if the trigger has been set.

Proceedings ArticleDOI
01 Jun 2000
TL;DR: A new fault representation mechanism for digital circuits based on fault tuples, which shows a 17% reduction of average CPU time when performing sim ulation on all fault types simultaneously, as opposed to individually.
Abstract: We introduce a new fault representation mechanism for digital circuits based on fault tuples. A fault tuple is a simple 3-element condition for a signal line, its value, and clock cycle constrain t. AND-OR expressions of fault tuples are used to represent arbitrary misbehaviors. A fault simulator based on fault tuples was used to conduct experiments on benc hmark circuits. Simulation results show that a 17% reduction of average CPU time is achiev ed when performing sim ulation on all fault types simultaneously, as opposed to individually. We expect further improvements in speedup when the shared characteristics of the various fault types are better exploited.

Proceedings ArticleDOI
30 Apr 2000
TL;DR: The synthesis algorithm for synthesizing BIST test pattern generators using the C-compatibility technique into ATOM, an advanced ATPG system for combinational circuits achieves 100% stuck-at fault coverage in much smaller test application time than the previously published counter-based exhaustive BIST pattern generators.
Abstract: This paper presents a new technique, called C-compatibility, for reducing the test application time of the counter-based exhaustive built-in-self-test (BIST) test pattern generators. This technique reduces the test application time by reducing the size of the binary counter used in the test pattern generators. We have incorporated the synthesis algorithm for synthesizing BIST test pattern generators using the C-compatibility technique into ATOM, an advanced ATPG system for combinational circuits. The experimental results showed that the test pattern generators synthesized using this technique for the ISCAS 85 and full scan versions of the ISCAS 89 benchmark circuits achieve 100% stuck-at fault coverage in much smaller test application time than the previously published counter-based exhaustive BIST pattern generators.