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Showing papers on "Stuck-at fault published in 2005"


Journal ArticleDOI
TL;DR: In this paper, the authors proposed a method to extend the conventional fault analysis methods so that IIDG contribution can be estimated in the fault analysis, which gives rms profiles of the fault currents of interest (IIDG contributions and the fault current the protective device will see).
Abstract: This paper shows that the current an inverter interfaced distributed generator (IIDG) contributes to a fault varies considerably, due mainly to fast response of its controller. This paper proposes a method to extend the conventional fault analysis methods so that IIDG contribution can be estimated in the fault analysis. The proposed method gives rms profiles of the fault currents of interest (IIDG contribution and the fault currents the protective device will see). Test results, based on a prototype feeder, show that the proposed approach can estimate the fault current's contributions under both balanced and unbalanced fault conditions.

240 citations


Journal ArticleDOI
TL;DR: In this paper, a fuzzy-logic-based algorithm to identify the type of faults for digital distance protection system has been developed, which is able to accurately identify the phase(s) involved in all ten types of shunt faults that may occur in a transmission line under different fault resistances, inception angle, and loading levels.
Abstract: In this paper, a fuzzy-logic-based algorithm to identify the type of faults for digital distance protection system has been developed. The proposed technique is able to accurately identify the phase(s) involved in all ten types of shunt faults that may occur in a transmission line under different fault resistances, inception angle, and loading levels. The proposed method needs only three line-current measurements available at the relay location and can perform the fault classification task in about a half-cycle period. Thus, the proposed technique is well suited for implementation in a digital distance protection scheme.

221 citations


Proceedings ArticleDOI
01 Jan 2005
TL;DR: In this article, a performance evaluation for the inverter connected to the machine with variable stator voltage and frequency is presented, showing the influence of the applied standard field oriented control on the currents during a fault.
Abstract: Variable speed drives have become industrial standard in many applications Therefore fault diagnosis of voltage source inverters is becoming more and more important One possible fault within the inverter is an open circuit transistor fault An overview of the different strategies to detect this fault is given, including the algorithms used to localize the open transistor Previous work showed significant differences among the available methods to detect such a fault for a mains side active rectifier This paper extends the performance evaluation for the inverter connected to the machine with variable stator voltage and frequency Simulation results are presented They show the influence of the applied standard field oriented control on the currents during a fault An experimental setup in the laboratory is used to validate simulation results Typical detection results are presented including time-to-detection measurements Robust detection of open transistor faults has been found to be possible

179 citations


Proceedings ArticleDOI
05 Apr 2005
TL;DR: In this paper, the authors describe one-and two-ended impedance-based fault location experiences using simple reactance, Takagi, zero-sequence current with angle correction, and twoended negative-sequence.
Abstract: In this paper, we describe one- and two-ended impedance-based fault location experiences. We define terms associated with fault location and describe several impedance-based methods of fault location (simple reactance, Takagi, zero-sequence current with angle correction, and two-ended negative-sequence). We examine several system faults and analyze the performance of the fault locators given possible sources of error (short fault window, nonhomogeneous system, incorrect fault type selection, etc.). Finally, we show the laboratory testing results of a two-ended method, where we automatically extracted a two-ended fault location estimate from a single end.

132 citations


Proceedings ArticleDOI
18 Dec 2005
TL;DR: A family of logical fault models for reversible circuits composed of k- CNOT (k-input controlled-NOT) gates and implementable by many technologies are derived, extensions of the previously proposed single missing-gate fault (MGF) model, and include multiple and partial MGFs.
Abstract: Reversibility is of interest in achieving extremely low power dissipation; it is also an inherent design requirement of quantum computation. Logical fault models for conventional circuits such as stuck-at models are not wellsuited to quantum circuits. We derive a family of logical fault models for reversible circuits composed of k- CNOT (k-input controlled-NOT) gates and implementable by many technologies. The models are extensions of the previously proposed single missing-gate fault (MGF) model, and include multiple and partial MGFs. We study the basic detection requirements of the new fault types and derive bounds on the size of their test sets. We also present optimal test sets computed via integer linear programming for various benchmark circuits. These results indicate that, although the test sets are generally very small, partial MGFs may need significantly larger test sets than single MGFs.

132 citations


Journal ArticleDOI
TL;DR: This analysis of the relationships between variable and literal faults, and among literal, operator, term, and expression faults, produces a richer set of findings that interpret previous empirical results, can be applied to the design and evaluation of test methods, and inform the way that test cases should be prioritized for earlier detection of faults.
Abstract: Kuhn, followed by Tsuchiya and Kikuno, have developed a hierarchy of relationships among several common types of faults (such as variable and expression faults) for specification-based testing by studying the corresponding fault detection conditions. Their analytical results can help explain the relative effectiveness of various fault-based testing techniques previously proposed in the literature. This article extends and complements their studies by analyzing the relationships between variable and literal faults, and among literal, operator, term, and expression faults. Our analysis is more comprehensive and produces a richer set of findings that interpret previous empirical results, can be applied to the design and evaluation of test methods, and inform the way that test cases should be prioritized for earlier detection of faults. Although this work originated from the detection of faults related to specifications, our results are equally applicable to program-based predicate testing that involves logic expressions.

122 citations


Journal ArticleDOI
24 Oct 2005
TL;DR: In this paper, the authors present a systematic classification of all electrical faults, short and open-circuits, in the switched reluctance drive (excluding the controller itself), and the investigation of fault patterns and possible remediation.
Abstract: The switched reluctance drive is known to be fault tolerant, but it is not fault free. The goals of this study are the systematic classification of all electrical faults, short-and open-circuits, in the switched reluctance drive (excluding the controller itself), and the investigation of fault patterns and possible remediation. Each situation is analyzed via finite element analysis, and/or experiments. The transient effects during the faults are described. Possible remediation schemes other than disabling the faulted phase are explored. There is a particular focus on switch short-circuit for which new results are presented.

120 citations


Journal ArticleDOI
TL;DR: In this paper, a fault location algorithm for parallel transmission lines using two terminal currents is proposed, which is based on the fact that the difference between voltage distributions, calculated from two terminals currents, is the smallest at fault point.
Abstract: This paper presents a novel time-domain fault location algorithm for parallel transmission lines using two terminal currents. Parallel transmission lines with faults can be decoupled into the common component net and differential component net. Since the differential component net is only composed of the parallel lines and its terminal voltages equal zero, the proposed algorithm is based on the fact that the difference between voltage distributions, calculated from two terminal currents, is the smallest at fault point. To be practical, unsynchronized data and the transient transferring ability of the current transformer are taken into consideration. The algorithm needs a very short data window, and any segment of current data can be used to locate faults. The proposed algorithm is verified successfully using the simulation data generated by the frequency-dependent line model of the Alternative Transients Program and the field recording data provided by traveling-wave fault locators. Locating results show the satisfactory accuracy of the algorithm for various fault types, fault distances, and fault resistances.

101 citations


Journal ArticleDOI
TL;DR: In this article, a finite element model was used to perform simulations under three types of fault conditions, single-phase open circuit fault, phase-to-phase terminal short-circuit, and internal turn-toturn shortcircuit have been studied.
Abstract: Three-phase trapezoidal back-EMF permanent magnet (PM) machines are used in many applications where the reliability and fault tolerance are important requirements. Knowledge of the machine transient processes under various fault conditions is the key issue in evaluating the impact of machine fault on the entire electromechanical system. The machine electrical and mechanical quantities whose transient behaviors are of importance under fault conditions include the voltages and currents of the coils and phases, the electromagnetic torque, and the rotor speed. Experimental test based on true machines for such a purpose is impractical for its high cost and difficulty to make. Computer simulation based on the finite element method has shown its effectiveness in fault study in this paper. Before the finite element model was used to perform simulations under fault conditions, it was validated by test data under normal conditions. Three types of fault conditions-single-phase open circuit fault, phase-to-phase terminal short-circuit, and internal turn-to-turn short-circuit have been studied.

99 citations


Proceedings ArticleDOI
11 May 2005
TL;DR: Experimental results show that the proposed method reduces the peak current and power dissipation during the fast capture cycle by 40.59% on average and up to 54.17% for large ISC AS 89 circuits.
Abstract: This paper presents a progressive match filling (PMF) technique to reduce the peak current and power dissipation during the fast capture cycle in broadside delay fault testing. The proposed method fills the unspecified values (X) in the generated initialization vector such that the resulting launch vector at a minimal Hamming distance from the initialization vector. The proposed method does not require any hardware modification and can be used to obtain any test sets that require two pattern tests. Experimental results show that the proposed method reduces the peak current and power dissipation during the fast capture cycle by 40.59% on average and up to 54.17% for large ISC AS 89 circuits.

92 citations


Proceedings ArticleDOI
03 Oct 2005
TL;DR: This work proposes new techniques to determine illegal states of circuits that can be used during ATPG to prohibit tests using such states, which are essentially functional or pseudofunctional.
Abstract: In designs using DFT, such as scan, some of the faults that are untestable in the circuit without DFT become testable after DFT insertion. Additionally, scan tests may scan in illegal or unreachable states that cause nonfunctional operation of the circuit during test. This may cause higher than normal power dissipation and demands on supply current. We propose new techniques to determine illegal states of circuits that can be used during ATPG to prohibit tests using such states. The resulting tests are essentially functional or pseudofunctional.

Book
01 Jan 2005
TL;DR: Fault and Fault Modelling, Test Stimulus Generation, Fault Diagnosis Methodology, and Design for Testability and Built-In Self-Test are studied to improve testability and built-in self-Test.
Abstract: Fault and Fault Modelling.- Test Stimulus Generation.- Fault Diagnosis Methodology.- Design for Testability and Built-In Self-Test.

Journal ArticleDOI
TL;DR: A decision-making module based on fuzzy logic for model-based fault diagnosis applications, based on the input-output linear model parity equations approach, has been successfully applied in laboratory equipment, resulting in a reduction of the uncertainty due to disturbances and modelling errors.

Journal ArticleDOI
TL;DR: In this paper, a general architecture for fault tolerant control is proposed based on the (primary) YJBK parameterization of all stabilizing compensators and uses the dual YJBJ parameterization to quantify the performance of the fault tolerant system.
Abstract: A general architecture for fault tolerant control is proposed. The architecture is based on the (primary) YJBK parameterization of all stabilizing compensators and uses the dual YJBK parameterization to quantify the performance of the fault tolerant system. The approach suggested can be applied for additive faults, parametric faults and for system structural changes. The modelling for each of these fault classes is described. The method allows for design of passive as well as for active fault handling. Also, the related design method can be fitted either to guarantee stability or to achieve graceful degradation in the sense of guaranteed degraded performance. A number of fault diagnosis problems, fault tolerant control problems, and feedback control with fault rejection problems are formulated/considered, mainly from a fault modelling point of view. The method is illustrated on a servo example including an additive fault and a parametric fault.

Proceedings ArticleDOI
01 Jan 2005
TL;DR: In this paper, a fast fault detection method for microgrid system based on micro-sources equipped with power electronics interfaces is explored, which provides reliable and fast detection for different types of faults within the micro-grid.
Abstract: In this paper a fast fault detection method for Microgrid system based on micro-sources equipped with power electronics interfaces is explored. This method provides reliable and fast detection for different types of faults within the micro-grid. The micro-source output voltages are monitored and then converted to dc quantities in the d-q reference frame. Thus, any disturbance at the micro-source output due to any type of fault is reflected as disturbances in the d-q values. The disturbance is used to detect the fault and this leads to the initiation of the associated breaker to isolate the faulted section from the network. Analysis and simulation results are presented for different types of faults within the micro-grid

Journal ArticleDOI
TL;DR: This paper aims at developing a generic neurofuzzy model-based strategy for detecting broken rotor bars, which is one of the most common type of faults that may occur in a squirrel-cage induction motor.
Abstract: Many fault detection and diagnosis schemes are based on the concept of comparing the plant output with a model in order to generate residues. A fault is deemed to have occurred if the residue exceeds a predetermined threshold. Unfortunately, the practical usefulness of model-based fault detection schemes is limited because of the difficulty in acquiring sufficiently rich experimental data to identify an accurate model of the system characteristics. This paper aims at developing a generic neurofuzzy model-based strategy for detecting broken rotor bars, which is one of the most common type of faults that may occur in a squirrel-cage induction motor. A neurofuzzy model that captures the generic characteristics of a class of asynchronous motor is the key component of the proposed approach. It is identified using data generated by a simulation model that is constructed using information on the name plate of the motor. Customization for individual motors is then carried out by selecting the threshold for fault detection via an empirical steady-state torque-speed curve. Since data obtained from a practical motor are used to select the threshold and not to build a complete model, the objective of reducing the amount of experimental input-output data required to design a model-based fault detector may be realized. Experimental results are presented to demonstrate the viability of the proposed fault detection scheme.

Journal ArticleDOI
TL;DR: A model-free incremental diagnosis algorithm is outlined, which alleviates the need for an explicit fault model, and extensive results on combinational and full-scan sequential benchmark circuits confirm its resolution and performance.
Abstract: Fault diagnosis is important in improving the circuit-design process and the manufacturing yield. Diagnosis of today's complex defects is a challenging problem due to the explosion of the underlying solution space with the increasing number of fault locations and fault models. To tackle this complexity, an incremental diagnosis method is proposed. This method captures faulty lines one at a time using the novel linear-time single-fault diagnosis algorithms. To capture complex fault effects, a model-free incremental diagnosis algorithm is outlined, which alleviates the need for an explicit fault model. To demonstrate the applicability of the proposed method, experiments on multiple stuck-at faults, open-interconnects and bridging faults are performed. Extensive results on combinational and full-scan sequential benchmark circuits confirm its resolution and performance.

Proceedings ArticleDOI
02 Oct 2005
TL;DR: Experimental results indicate that this approach can instantly catch a fault within a scan chain quite accurately in most cases.
Abstract: In this paper we address the scan chain diagnosis problem. We propose a new diagnosis flow based on the concept of signal profiling to accurately pinpoint the location of a faulty flip-flop in a scan chain. As compared to the conventional cause-effect or effect-cause analysis, this approach is much more computationally efficient because it does not have to simulate the behaviors of a large number of fault candidates. Also, it is general and applicable to all kinds of faults because it does not assume any specific fault model. Experimental results indicate that this approach can instantly catch a fault within a scan chain quite accurately in most cases.

Proceedings ArticleDOI
15 May 2005
TL;DR: An extended symptom-fault-action model is proposed to incorporate actions into fault reasoning process to tackle the above problem and shows both performance and accuracy of fault reasoning can be greatly improved by taking actions.
Abstract: Fault localization is a core element in fault management. Many fault reasoning techniques use deterministic or probabilistic symptom-fault causality model for fault diagnoses and localization. Symptom-fault map is commonly used to describe symptom-fault causality in fault reasoning. However, due to lost and spurious symptoms in fault reasoning systems that passively collect symptoms, the performance and accuracy of the fault localization can be significantly degraded. In this paper, we propose an extended symptom-fault-action model to incorporate actions into fault reasoning process to tackle the above problem. This technique is called active integrated fault reasoning (AIR), which contains three modules: fault reasoning, fidelity evaluation and action selection. Corresponding fault reasoning and action selection algorithms are elaborated. Simulation study shows both performance and accuracy of fault reasoning can be greatly improved by taking actions, especially when the rate of spurious and lost symptoms is high.

Proceedings ArticleDOI
30 Nov 2005
TL;DR: New models of saboteurs and mutants that can be easily applicable in VFIT, a fault injection tool developed by the Fault-Tolerant Systems Research Group (GSTF) of the Technical University of Valencia are presented.
Abstract: Fault injection techniques based on the use of VHDL as design language offer important advantages with regard to other fault injection techniques First, as they can be applied during the design phase of the system, they allow reducing the time-to-market Second, this type of techniques presents high controllability and reachability Among the different techniques, those based on the use of saboteurs and mutants are especially attractive due to their high capability of fault modeling However, it is difficult to implement automatically these techniques in a fault injection tool, mainly the insertion of saboteurs and the generation of mutants In this paper, we present new models of saboteurs and mutants that can be easily applicable in VFIT, a fault injection tool developed by the Fault-Tolerant Systems Research Group (GSTF) of the Technical University of Valencia

Proceedings ArticleDOI
12 Jun 2005
TL;DR: Based on the sudden reduction of absolute value of the change rate of power swing centre voltage (PSCV), the presented detector can detect the symmetrical fault reliably and sensitively in two cycles.
Abstract: Distance relay should be blocked during power swing to ensure the reliability, but still should trip as soon as possible after an internal fault occurs during power swing. It was very difficult to detect the symmetrical fault reliably and fast during power swing with complex power swing conditions and fault conditions considered. This paper presents a new fast detector of symmetrical fault during power swing. Based on the sudden reduction of absolute value of the change rate of power swing centre voltage (PSCV), the presented detector can detect the symmetrical fault reliably and sensitively in two cycles. This detector is easy to set and immune to the swing period, fault arc, fault location and power angle. EMTP simulations and real-time digital simulator system (RTDS) tests prove the presented detector is fast, sensible and reliable.

Journal ArticleDOI
TL;DR: In this paper, transient pattern analysis is explored as a tool for fault detection and diagnosis of an HVAC system, and the results show that the evolution of fault residuals forms clear and distinct patterns that can be used to isolate faults.

Patent
24 Jun 2005
TL;DR: In this paper, a system and method for fault detection in turbine engines and other mechanical systems that have nonlinear relationships is presented. But the authors focus on the ability of the system to detect symptoms of fault.
Abstract: A system and method for fault detection is provided. The fault detection system provides the ability to detect symptoms of fault in turbine engines and other mechanical systems that have nonlinear relationships. The fault detection system uses a neural network to perform a data representation and feature extraction where the extracted features are analogous to principal components derived in a principal component analysis. This neural network data representation analysis can then be used to determine the likelihood of a fault in the system.

Proceedings ArticleDOI
08 Nov 2005
TL;DR: This paper introduces a method which extends the use of available gate level stuck-at fault diagnosis tools to stuck-open fault diagnosis, and transforms the transistor level circuit description to a gate level description where stuck- open faults are represented by stuck- at faults.
Abstract: While most of the fault diagnosis tools are based on gate level fault models, for instance the stuck-at model, many faults are actually at the transistor level. The stuck-open fault is one example. In this paper we introduce a method which extends the use of available gate level stuck-at fault diagnosis tools to stuck-open fault diagnosis. The method transforms the transistor level circuit description to a gate level description where stuck-open faults are represented by stuck-at faults, so that the stuck-open faults can be diagnosed directly by any of the stuck-at fault diagnosis tools. The transformation is only performed on selected gates and thus has little extra computational cost. This method also applies to the diagnosis of multiple stuck-open faults within a gate. Successful diagnosis results are presented using wafer test data and an internal diagnosis tool from Philips

Journal ArticleDOI
TL;DR: A diagnosis technique to locate single stuck-at faults and multiple timing faults in scan chains is presented, which applies single excitation (SE) patterns, in which only one bit is flipped in the presence of multiple faults.
Abstract: A diagnosis technique to locate single stuck-at faults and multiple timing faults in scan chains is presented. This technique applies single excitation (SE) patterns, in which only one bit is flipped in the presence of multiple faults. With SE patterns, the problem of unknown values in scan chains is eliminated. The diagnosis result is therefore deterministic, not probabilistic. In addition to the first fault, this technique also diagnoses the remaining timing faults by applying multiple excitation patterns. Experiments on benchmark circuits show that average diagnosis resolutions are mostly less than five, even for the tenth fault in the scan chain.

Journal ArticleDOI
TL;DR: This paper starts with a paradigmatic fault tolerance scheme that systematically adds redundancy into a discrete-time dynamic system in a way that achieves tolerance to transient faults in both the state transition and the error-correcting mechanisms, and obtains an efficient way of providing fault tolerance to k identical unreliable LFSMs that operate in parallel on distinct input sequences.
Abstract: This paper discusses fault tolerance in discrete-time dynamic systems, such as finite-state controllers or computer simulations, with focus on the use of coding techniques to efficiently provide fault tolerance to linear finite-state machines (LFSMs). Unlike traditional fault tolerance schemes, which rely heavily-particularly for dynamic systems operating over extended time horizons-on the assumption that the error-correcting mechanism is fault free, we are interested in the case when all components of the implementation are fault prone. The paper starts with a paradigmatic fault tolerance scheme that systematically adds redundancy into a discrete-time dynamic system in a way that achieves tolerance to transient faults in both the state transition and the error-correcting mechanisms. By combining this methodology with low-complexity error-correcting coding, we then obtain an efficient way of providing fault tolerance to k identical unreliable LFSMs that operate in parallel on distinct input sequences. The overall construction requires only a constant amount of redundant hardware per machine (but sufficiently large k) to achieve an arbitrarily small probability of overall failure for any prespecified (finite) time interval, leading in this way to a lower bound on the computational capacity of unreliable LFSMs.

Journal ArticleDOI
TL;DR: In this article, an accurate time domain algorithm for fault location using one-terminal data is presented based on the modal analysis and the R-L model of transmission lines, and utilizes the fault-superimposed components effectively.

Journal ArticleDOI
TL;DR: The diagnosis techniques take the test-pattern sequence into account, and therefore, produce precise diagnosis results and the technique handles multiple faults of different fault models.
Abstract: A resistive-open defect is an imperfect circuit connection that can be modeled as a defect resistor between two circuit nodes that should be connected. A stuck-open (SOP) defect is a complete break (no current flow) between two circuit nodes that should be connected. Conventional single stuck-at fault diagnosis cannot precisely diagnose these two defects because the test results of defective chips depend on the sequence of test patterns. This paper presents precise diagnosis techniques for these two defects. The diagnosis techniques take the test-pattern sequence into account, and therefore, produce precise diagnosis results. Also, our diagnosis technique handles multiple faults of different fault models. The diagnosis techniques are validated by experimental results. Twelve SOP and one resistive-open chips are diagnosed out of a total of 459 defective chips.

Proceedings ArticleDOI
29 Jun 2005
TL;DR: An autonomous self-repair approach for SRAM-based FPGAs is developed based on competitive runtime reconfiguration (CRR) that enables evolution of a customized fault-specific repair, realized directly as new configurations using the FPGA's normal throughput processing operations.
Abstract: An autonomous self-repair approach for SRAM-based FPGAs is developed based on competitive runtime reconfiguration (CRR). Under the CRR technique, an initial population of functionally identical (same input-output behavior), yet physically distinct (alternative design or place-and-route realization) FPGA configurations is produced at design time. At run-time, these individuals compete for selection based on a fitness function favoring fault-free behavior. Hence, any physical resource exhibiting an operationally-significant fault decreases the fitness of those configurations which use it. Through runtime competition, the presence of the fault becomes occluded from the visibility of subsequent FPGA operations. Meanwhile, the offspring formed through crossover and mutation of faulty and viable configurations are reintroduced into the population. This enables evolution of a customized fault-specific repair, realized directly as new configurations using the FPGA's normal throughput processing operations. Multiple phases of the fault handling process including detection, isolation, diagnosis, and recovery are integrated into a single cohesive approach. FPGA-based multipliers are examined as a case study demonstrating evolution of a complete repair for a 3-bit /spl times/ 3-bit multiplier from several stuck-at-faults within a few thousand iterations. Repairs are evolved in-situ, in real-time, without test vectors, while allowing the FPGA to remain partially online.

Proceedings ArticleDOI
06 Jul 2005
TL;DR: This paper proposes a new approach combining formal property checking and the generation of specific circuit mutants to achieve efficient early identification of unacceptable effects of multiple faults.
Abstract: The interest for early analyses of the functional impact of faults in a circuit is growing, due to the increasing probability of transient faults. However, experiments are often very long, especially when spatial and temporal multiplicity has to be taken into account in the fault model. Formal property checking is an appealing approach to perform comprehensive functional validations but is intended to validate properties only in nominal operation, not after a fault has occurred. This paper proposes a new approach combining formal property checking and the generation of specific circuit mutants to achieve efficient early identification of unacceptable effects of multiple faults.