Showing papers on "Stuck-at fault published in 2006"

Software Reliability Analysis by Considering Fault Dependency and Debugging Time Lag

Abstract: Over the past 30 years, many software reliability growth models (SRGM) have been proposed. Often, it is assumed that detected faults are immediately corrected when mathematical models are developed. This assumption may not be realistic in practice because the time to remove a detected fault depends on the complexity of the fault, the skill and experience of personnel, the size of debugging team, the technique(s) being used, and so on. During software testing, practical experiences show that mutually independent faults can be directly detected and removed, but mutually dependent faults can be removed iff the leading faults have been removed. That is, dependent faults may not be immediately removed, and the fault removal process lags behind the fault detection process. In this paper, we will first give a review of fault detection & correction processes in software reliability modeling. We will then illustrate the fact that detected faults cannot be immediately corrected with several examples. We also discuss the software fault dependency in detail, and study how to incorporate both fault dependency and debugging time lag into software reliability modeling. The proposed models are fairly general models that cover a variety of known SRGM under different conditions. Numerical examples are presented, and the results show that the proposed framework to incorporate both fault dependency and debugging time lag for SRGM has a better prediction capability. In addition, an optimal software release policy for the proposed models, based on cost-reliability criterion, is proposed. The main purpose is to minimize the cost of software development when a desired reliability objective is given

Failure proximity: a fault localization-based approach

Abstract: Recent software systems usually feature an automated failure reporting system, with which a huge number of failing traces are collected every day. In order to prioritize fault diagnosis, failing traces due to the same fault are expected to be grouped together. Previous methods, by hypothesizing that similar failing traces imply the same fault, cluster failing traces based on the literal trace similarity, which we call trace proximity. However, since a fault can be triggered in many ways, failing traces due to the same fault can be quite different. Therefore, previous methods actually group together traces exhibiting similar behaviors, like similar branch coverage, rather than traces due to the same fault. In this paper, we propose a new type of failure proximity, called R-Proximity, which regards two failing traces as similar if they suggest roughly the same fault location. The fault location each failing case suggests is automatically obtained with Sober, an existing statistical debugging tool. We show that with R-Proximity, failing traces due to the same fault can be grouped together. In addition, we find that R-Proximity is helpful for statistical debugging: It can help developers interpret and utilize the statistical debugging result. We illustrate the usage of R-Proximity with a case study on the grep program and some experiments on the Siemens suite, and the result clearly demonstrates the advantage of R-Proximity over trace proximity.

An iterative learning observer for fault detection and accommodation in nonlinear time-delay systems

Abstract: This article addresses fault detection, estimation, and compensation problem in a class of disturbance driven time delay nonlinear systems. The proposed approach relies on an iterative learning observer (ILO) for fault detection, estimation, and compensation. When there are no faults in the system, the ILO supplies accurate disturbance estimation to the control system where the effect of disturbances on estimation error dynamics is attenuated. At the same time, the proposed ILO can detect sudden changes in the nonlinear system due to faults. As a result upon the detection of a fault, the same ILO is used to excite an adaptive control law in order to offset the effect of faults on the system. Further, the proposed ILO-based adaptive fault compensation strategy can handle multiple faults. The overall fault detection and compensation strategy proposed in the paper is finally demonstrated in simulation on an automotive engine example to illustrate the effectiveness of this approach. Copyright © 2005 John Wiley & Sons, Ltd.

Fault analysis on distribution feeders with distributed generators

Abstract: Summary form only given. This paper shows that the current an inverter interfaced distributed generator (IIDG) contributes to a fault varies considerably, due mainly to fast response of its controller. The paper proposes a method to extend the conventional fault analysis methods so that IIDG contribution can be estimated in the fault analysis. The proposed method gives rms profiles of the fault currents of interest (IIDG contribution and the fault currents the protective device will see). Test results, based on a prototype feeder, show that the proposed approach can estimate the fault currents contributions under both balanced and unbalanced fault conditions.

Strategies of fault tolerant operation for three-level PWM inverters

Abstract: This paper proposes fault tolerant operation strategies for three-level neutral point clamped pulsewidth modulation inverters in high power, safety-critical applications. Likely faults are identified and fault tolerant schemes based on the inherent redundancy of voltage vectors are presented. Simulation verification is performed to show fault handling capabilities. Prototyping and principle investigation are performed on a 150-KW inverter and testing results are presented.

An analytical approach for stochastic assessment of balanced and unbalanced voltage sags in large systems

Abstract: In this paper, voltage sags produced by balanced and unbalanced short circuits are analyzed by means of a new analytical method. The main feature of this approach is that contrary to the fault positions method, it does not require a preassignation of discrete fault positions along the lines. The developed algorithm has been applied to the 24-buses IEEE Reliability Test System (RTS) and to a real transmission system to illustrate its application. Results are analyzed and compared with the fault positions method. The mathematical formulation of the proposed approach is straightforward and different fault distributions along the lines can be effortlessly considered. The proposed method is adequate for the analysis of any size networks.

A Logic Diagnosis Methodology for Improved Localization and Extraction of Accurate Defect Behavior

Abstract: DIAGNOSIX is a comprehensive fault diagnosis methodology for characterizing failures in digital ICs. Using limited layout information, DIAGNOSIX automatically extracts a fault model for a failing IC by analyzing the behavior of the physical neighborhood surrounding suspect lines. Results from several simulated and over 800 failing ICs reveal a significant improvement in localization. More importantly, the output of DIAGNOSIX is an accurate model of the logic-level defect behavior that provides useful insight into the actual defect mechanism. Experiment results for the failing chips with successful physical failure analysis reveal that the extracted faults accurately describe the actual defects.

Fault detection and isolation based on novel unknown input observer design

Abstract: With an emphasis on fault isolation and by treating fault detection as a byproduct of fault isolation, both actuator and sensor fault detection and isolation (FDI) problems for a class of uncertain Lipschitz nonlinear systems are studied using an unknown input observer (UIO) design technique. To solve the actuator fault detection and isolation problem, we develop a particular system structure by regrouping the system inputs, which is suitable for UIO design. By filtering the regrouped outputs properly, the same system structure can be developed for sensor fault detection and isolation problem, which allows us to treat the sensor fault detection and isolation problem as an actuator fault detection and isolation problem. To accomplish FDI efficiently, a novel full order nonlinear UIO is designed with a special property suitable for fault isolation purposes and a necessary and sufficient condition for its existence are presented. The LMI based sufficient condition enables the designers to use Matlab LMI toolbox and makes the computationally difficult UIO design much easier. For UIO based FDI, the following three problems are investigated: 1) under what conditions is it possible to isolate single and/or multiple faults? 2) What is the maximum number of faults that can be isolated simultaneously? 3) How to design fault isolation schemes to achieve multiple fault isolation (that is, to make decisions on how many faults have occurred and the location of each fault)? Conditions for problem 1) are derived and the maximum number of faults that can be isolated is determined for problem 2) to solve problem 3) an FDI scheme is designed using a bank of nonlinear UIOs and its design procedure is presented in a step by step fashion. An example is given to show how to use the proposed FDI scheme and simulations results illustrate that the proposed technique works well for FDI in uncertain Lipschitz nonlinear systems.

Internal Short Circuit Fault Diagnosis for PM Machines Using FE-Based Phase Variable Model and Wavelets Analysis

Abstract: This paper presents a procedure using the finite-element (FE)-based phase variable model combined with wavelet analysis to facilitate the fault diagnostic study for permanent magnet machines with internal short circuit faults. Our efforts are dedicated to the aspects of fault modeling and fault extraction. The FE-based phase variable model is developed to describe the PM machine with internal short circuit faults. This model is built with the parameters [inductances and back Electromotive Force (EMF)] obtained from FE computations of the machine with the same type of fault. The developed model has two features. It includes the detailed information of the fault including the location of the shorted turns and the number of turns involved. It keeps the accuracy of the FE model by taking only a fraction of time needed by FE operation. This is particularly desired for diagnosing faults in machines connected to a control circuit. The wavelet transform is used to perform machine current/voltage signature analysis. Excellent results were obtained providing information that would not be otherwise available except by measurement

On innovative methods of induction motor interturn and broken-bar fault diagnostics

Abstract: A fault indicator, the so-called swing angle, for broken-bar and interturn faults is investigated in this paper. This fault indicator is based on the rotating magnetic-field pendulous-oscillation concept in faulty squirrel-cage induction motors. Using the "swing-angle indicator," it will be demonstrated here that an interturn fault can be detected even in the presence of machine manufacturing imperfections. Meanwhile, a broken-bar fault can be detected under both direct-line and PWM excitations, even under the more difficult condition of partial-load levels. These two conditions of partial load and motor manufacturing imperfections, which are considered as difficult situations for fault detection, are investigated through experimentally obtained test results for a set of 2- and 5-hp induction motors.

Fuzzy logic-based fault-type identification in unbalanced radial power distribution system

Abstract: In this paper, a fuzzy logic-based algorithm to identify the type of faults in radial, unbalanced distribution system has been developed. The proposed technique is able to accurately identify the phase(s) involved in all ten types of shunt faults that may occur in an electric power distribution system under different fault types, fault resistance, fault inception angle, system topology and loading levels. The proposed method needs only three line current measurements available at the substation and can perform the fault classification task in about half-cycle period. All the test results show that the proposed fault identifier is well suited for identifying fault types in radial, unbalanced distribution system.

Ground distance relay Compensation based on fault resistance calculation

Abstract: The fault resistance introduces an error in the fault distance estimate, and hence may create an unreliable operation of a distance relay. A new compensation method based on fault resistance calculation is presented. The fault resistance calculation is based on monitoring the active power at the relay point. The compensated fault impedance measures accurately the impedance between the relay location and the fault point. The relay has shown satisfactory performances under various fault conditions especially for the ground faults with high fault resistance. This new compensation method avoids the under-reach problem in ground distance relays

Hybrid System State Tracking and Fault Detection Using Particle Filters

Abstract: When particle filters are used for fault detection, they have the problem of sample impoverishment, which means there are not enough particles that can transition to a rare-occurring faulty mode. The consequence is that the fault cannot be properly detected. This paper proposes a method to overcome this problem. Essentially, we develop an algorithm for tracking the states of hybrid systems where fault detection is modeled as a special case of the state tracking of a hybrid system. Extensive simulations are carried out to analyze the effects of various parameters on the performance of the algorithm. It is shown that our algorithm can detect both known and unknown faults using a very small number of particles

Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic

Abstract: This paper presents hardening techniques against fault attacks and the practical evaluation of their efficiency. The circuit technology investigated to improve the resistance against fault attacks is asynchronous logic. Specific properties of asynchronous circuits make them inherently resistant against a large class of faults. An analysis of their behavior in the presence of faults shows that they are an interesting alternative to design robust systems. A behavior diagnosis enables us to propose hardening techniques that improve fault tolerance and resistance. They are applied at design time and aim at exploiting quasi-delay insensitive (QDI) circuit properties to significantly harden the architecture with a very low area overhead and a reasonable performance penalty. To validate these techniques, a hardened DES crypto-processor is presented. The countermeasures are evaluated using laser beam fault injection

Design and evaluation of a directional algorithm for transmission-line protection based on positive- sequence fault components

Abstract: A directional relay algorithm for EHV transmission lines using positive-sequence fault components is presented. By comparing the phase relationship between the voltage and current measured at the relay point, the algorithm can determine correctly whether a fault is in the forward or backward direction. Specially designed techniques and logic are adopted to solve the difficult problems that exist in a real system. The signal-processing procedure for extracting the required fault components is provided in detail. Extensive simulation studies were conducted on a 500 kV system model using EMTDC. Theoretical analysis and simulation results show that the proposed algorithm provides adequate sensitivity, reliability and a fast operating response under a variety of system and fault conditions. In addition, it provides significant advantages over conventional directional relays, and these are discussed in the paper.

Extensive Events Database Development using ATP and Matlab to Fault Location in Power Distribution Systems

Abstract: Opportune fault location in power distribution systems is an important aspect related to power quality, and especially to maintain good continuity indexes Fault location methods which use more information than RMS values of voltage and current, are the commonly known as Knowledge Based Methods - KBM Those require of a complete fault database to adequately perform the training and validation stages, and as a consequence successfully perform the fault location task In this paper, the modeling of a power distribution system and its protective relaying to obtain an extensive fault database using the capabilities of ATP and Matlab is described The obtained database can be used to perform different types of system analysis and in this specific case to solve the problem of fault location in power distribution systems As a result a methodology to perform automatic simulations and a data base with 930 fault situations in a 25 kV test system was obtained

Parity-Based Fault Detection Architecture of S-box for Advanced Encryption Standard

Abstract: In this paper, the authors present parity-based fault detection architecture of the S-box for designing high performance fault detection structures of the advanced encryption standard. Instead of using look-up tables for the S-box and its parity prediction, logical gate implementations based on the composite field are utilized. After analyzing the error propagation for injected single faults, the authors modify the original S-box and suggest fault detection architecture for the S-box. Using the closed formulations for the predicted parity bits, the authors propose a parity-based fault detection scheme for reaching the maximum fault coverage. Moreover, the overhead costs, including space complexity and time delay of our modified S-box and the parity predictions are also compared to those of the previously reported ones

Integrated Fault Detection and Fault-Tolerant Control Architectures for Distributed Processes

Abstract: This paper presents an integrated fault detection (FD) and fault-tolerant control (FTC) architecture for spatially distributed processes described by quasi-linear parabolic partial differential equations (PDEs) with control constraints and control actuator faults. Under full state feedback conditions, the architecture integrates model-based fault detection, spatially distributed feedback, and supervisory control to orchestrate switching between different actuator configurations in the event of faults. The various components are designed on the basis of appropriate reduced-order models that capture the dominant dynamics of the distributed process. The fault detection filter replicates the dynamics of the fault-free reduced-order model and uses its behavioral discrepancy from that of the actual system as a residual for fault detection. Owing to the inherent approximation errors in the reduced-order model, appropriate fault detection and control reconfiguration criteria are derived for the implementation of ...

Analysis and methodology for multiple-fault diagnosis

Abstract: In this paper, we propose a multiple-fault-diagnosis methodology based on the analysis of failing patterns and the structure of diagnosed circuits. We do not consider the multiple-fault behavior explicitly, but rather partition the failing outputs and use an incremental simulation-based technique to diagnose failures one at a time. Our methodology can be further improved by selecting appropriate diagnostic test patterns. The n-detection tests allow us to apply a simple single-fault-based diagnostic algorithm, and yet achieve good diagnosability for multiple faults. Experimental results demonstrate that our technique is highly efficient and effective. It has an approximately linear time complexity with respect to the fault multiplicity and achieves a high diagnostic resolution for multiple faults. Real manufactured industrial chips affected by multiple faults can be diagnosed in minutes of central processing unit (CPU) time.

Improving Precision Using Mixed-level Fault Diagnosis

Abstract: For nanometer manufacturing fabrication process, it is critical to narrow down the defect location for successful physical failure analysis. In this paper, we present a mixed-level diagnosis technique, which first performs diagnosis at logic level, and then performs switch-level analysis to locate a defect at transistor level. An efficient single pass mixed-mode diagnosis flow proposed to isolate defects within a cell. Experimental results showed significant improvement in precision over traditional logic diagnosis with only a fractional increase in run-time. The proposed mixed-level diagnosis technique was applied to successfully isolate silicon defects.

Fault diagnosis apparatus

Abstract: A fault diagnosis section activates a driving component alone, measures an operation state signal and a paper passage time, and stores feature values (Vm, σv, Tqs, σts) extracted as a determination reference in a storage medium. A paper passage fault determination section determines whether or not a fault has arisen on the basis of the paper passage time when an apparatus is under normal operating conditions. A diagnosis target block determination section determines an order to operate a detail fault diagnosis when it is determined that there is a plurality of diagnosis target blocks. When the driving component is activated alone under actual operation conditions, the operation state signal Vf is obtained, and an operation state fault determination section conducts diagnosis on whether or not a fault has arisen on the driving component and a state of the fault, and whether or not a fault has arisen on other power transmission components and a nature of the fault with reference to the feature values as the determination reference on the basis of a degree of deviation from a normal range.

An algorithm for multiple fault diagnosis in analogue circuits

Abstract: The paper deals with multiple fault diagnosis of analogue AC or DC circuits with limited accessible terminals for excitation and measurement and brings an algorithm for identificating faulty elements and evaluating their parameters. The main achievement is a method enabling us to efficiently identify faulty elements. For this purpose some testing equations are derived playing a key role in identification of possibly faulty elements which are next verified using a test of acceptance. The proposed approach is described in detail for double fault diagnosis. Also extension to triple fault diagnosis is given. Although the method pertains to linear circuits, some aspects of multiple fault diagnosis of non-linear circuits can be also performed using the small signal approach. Two numerical examples illustrate the proposed method and show its efficiency. Copyright © 2006 John Wiley & Sons, Ltd.

Diagnostic Test Generation for Arbitrary Faults

Abstract: It is now generally accepted that the stuck-at fault model is no longer sufficient for many manufacturing test activities. Consequently, diagnostic test pattern generation based solely on distinguishing stuck-at faults is unlikely to achieve the resolution required for emerging fault types. In this work we describe a new diagnostic ATPG implementation that uses a generalized fault model. It can be easily used in any diagnosis framework to refine diagnostic resolution for complex defects. For various types of faults that include, for example, bridge, transition, and transistor stuck-open, we show that diagnostic resolution can be significantly enhanced over a traditional diagnostic test set aimed only at stuck-at faults. Finally, we illustrate the use of our diagnostic ATPG to distinguish faults derived from a state-of-the-art diagnosis flow based on layout.

Simulating Resistive-Bridging and Stuck-At Faults

Abstract: The authors present a simulator for resistive-bridging and stuck-at faults. In contrast to earlier work, it is based on electrical equations rather than table look up, thus, exposing more flexibility. For the first time, simulation of sequential circuits is dealt with; interaction of fault effects in current time frame and earlier time frames is elaborated on for different bridge resistances. Experimental results are given for resistive-bridging and stuck-at faults in combinational and sequential circuits. Different definitions of fault coverage are listed, and quantitative results with respect to all these definitions are given for the first time

Analyzing Fault Models for Reversible Logic Circuits

Abstract: Reversible logic computing is a rapidly developing research area. Testing such circuits is obviously an important issue. In this paper, we consider a new fault model, labeled crosspoint faults, for reversible logic circuits. A randomized Automatic Test Pattern Generation algorithm targeting this specific kind of fault is introduced and analyzed. Simulation results show that the algorithm yields very good performance. The relationship between the crosspoint faults and stuck-at faults is also investigated. We show that the crosspoint fault model is a better fault model for reversible circuits since it dominates the traditional stuck-at fault model in most instances.