Showing papers on "Stuck-at fault published in 2007"

Fault Diagnostic System for a Multilevel Inverter Using a Neural Network

Abstract: In this paper, a fault diagnostic system in a multilevel-inverter using a neural network is developed. It is difficult to diagnose a multilevel-inverter drive (MLID) system using a mathematical model because MLID systems consist of many switching devices and their system complexity has a nonlinear factor. Therefore, a neural network classification is applied to the fault diagnosis of a MLID system. Five multilayer perceptron (MLP) networks are used to identify the type and location of occurring faults from inverter output voltage measurement. The neural network design process is clearly described. The classification performance of the proposed network between normal and abnormal condition is about 90%, and the classification performance among fault features is about 85%. Thus, by utilizing the proposed neural network fault diagnostic system, a better understanding about fault behaviors, diagnostics, and detections of a multilevel inverter drive system can be accomplished. The results of this analysis are identified in percentage tabular form of faults and switch locations

Fault Direction Estimation in Radial Distribution System Using Phase Change in Sequence Current

Abstract: When a remotely sited wind farm is connected to the utility power system through a distribution line, the overcurrent relay at the common coupling point needs a directional feature. This paper presents a method for estimating the direction of fault in such radial distribution systems using phase change in current. The difference in phase angle between the positive-sequence component of the current during fault and prefault conditions has been found to be a good indicator of the fault direction in a three-phase system. A rule base formed for the purpose decides the location of fault with respect to the relay in a distribution system. Such a strategy reduces the cost of the voltage sensor and/or connection for a protection scheme which is of relevance in emerging distributed-generation systems. The algorithm has been tested through simulation for different radial distribution systems.

Sensor fault reconstruction and sensor compensation for a class of nonlinear state-space systems via a descriptor system approach

Abstract: A descriptor system approach is introduced to investigate sensor fault reconstruction and sensor compensation for a class of nonlinear state-space systems with Lipschitz constraints. Letting the sensor fault term be an auxiliary state vector, an augmented descriptor system is constructed. Using the linear matrix inequality technique, a state-space nonlinear estimator is designed for the augmented descriptor plant. Accurate asymptotic estimates of the original system state vector and the sensor fault term are thus obtained readily. By subtracting the estimated sensor fault term from the measurement output, sensor compensation is performed, allowing the existing controller for the original plant (without sensor faults) to continue to function normally even when a sensor fault occurs. Robust sensor fault reconstruction and sensor compensation are also discussed in detail for systems with simultaneous sensor faults, input disturbances and output noises. Finally, numerical examples and simulations are given to illustrate the design procedures and demonstrate the efficiency of the approaches. The sensor fault considered may be in any form, and may even be unbounded. As a result, the present work possesses a wide scope of applicability.

Perturbation-based Fault Screening

Abstract: Fault screeners are a new breed of fault identification technique that can probabilistically detect if a transient fault has affected the state of a processor. We demonstrate that fault screeners function because of two key characteristics. First, we show that much of the intermediate data generated by a program inherently falls within certain consistent bounds. Second, we observe that these bounds are often violated by the introduction of a fault. Thus, fault screeners can identify faults by directly watching for any data inconsistencies arising in an application's behavior. We present an idealized algorithm capable of identifying over 85% of injected faults on the SpecInt suite and over 75% overall. Further, in a realistic implementation on a simulated Pentium-III-like processor, about half of the errors due to injected faults are identified while still in speculative state. Errors detected this early can be eliminated by a pipeline flush. In this paper, we present several hardware-based versions of this screening algorithm and show that flushing the pipeline every time the hardware screener triggers reduces overall performance by less than 1%

A Direct Three-Phase Circuit Analysis-Based Fault Location for Line-to-Line Fault

Abstract: From a direct three-phase circuit analysis, an accurate fault-location algorithm has been obtained for the line-to-line fault as an extension of the author's previous work for line-to-ground fault location. Robustness of the proposed algorithm to load impedance uncertainty is enhanced by the introduction of impedance compensation using voltage and current measurements. Simulation results show a high degree of accuracy and robustness to load uncertainty.

Adaptive Debug and Diagnosis without Fault Dictionaries

Abstract: Diagnosis is essential in modern chip production to increase yield, and debug constitutes a major part in the pre-silicon development process. For recent process technologies, defect mechanisms are increasingly complex, and continuous efforts are made to model these defects by using sophisticated fault models. Traditional static approaches for debug and diagnosis with a simplified fault model are more and more limited. In this paper, a method is presented, which identifies possible faulty regions in a combinational circuit, based on its input/output behavior and independent of a fault model. The new adaptive, statistical approach combines a flexible and powerful effect-cause pattern analysis algorithm with high-resolution ATPG. We show the effectiveness of the approach through experiments with benchmark and industrial circuits.

Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Model

Abstract: This paper presents an efficient method for online testing of NoC switches. This method deals with control faults of NoC switches; i.e. the routing faults which cause NoC packets to be sent to output ports not intended to. A high level fault model has been proposed in this paper to model switch routing faults. The proposed method is evaluated by fault simulation that is based on our high-level fault model. This simulation and evaluation environment is modeled at the transaction level in VHDL.

Symbolic fault tree analysis for reactive systems

Abstract: Fault tree analysis is a traditional and well-established technique for analyzing system design and robustness. Its purpose is to identify sets of basic events, called cut sets, which can cause a given top level event, e.g. a system malfunction, to occur. Generating fault trees is particularly critical in the case of reactive systems, as hazards can be the result of complex interactions involving the dynamics of the system and of the faults. Recently, there has been a growing interest in model-based fault tree analysis using formal methods, and in particular symbolic model checking techniques. In this paper we present a broad range of algorithmic strategies for efficient fault tree analysis, based on binary decision diagrams (BDDs). We describe different algorithms encompassing different directions (forward or backward) for reachability analysis, using dynamic cone of influence techniques to optimize the use of the finite state machine of the system, and dynamically pruning of the frontier states. We evaluate the relative performance of the different algorithms on a set of industrial-size test cases.

Adaptive actuator fault detection, isolation and accommodation in uncertain systems

Abstract: Adaptive actuator fault detection, isolation, and accommodation problems for linear multi-input single-output (MISO) systems with unknown system parameters are investigated. To solve the detection problem, we construct an adaptive estimate of the output signal. By comparing it with the output of the system, any type of actuator faults can be detected. However, the fault isolation problem is much more complicated. In order to solve it using an adaptive approach, the article considers constant actuator faults, which arise when the actuator output (such as a valve) is stuck at some fixed value. A novel idea which entails controller design for fault isolation is proposed. Thus, the controller in this case is not only designed to meet the control objective, but also to help with fault isolation, in case of an actuator failure. To accomplish this, assuming that there are m inputs, a group of additive functions, called fault isolation design functions in m − 1 inputs, solely used for fault isolation, are introdu...

Study of the Effects of SEU-Induced Faults on a Pipeline Protected Microprocessor

Abstract: This paper presents a detailed analysis of the behavior of a novel fault-tolerant 32-bit embedded CPU as compared to a default (non-fault-tolerant) implementation of the same processor during a fault injection campaign of single and double faults. The fault-tolerant processor tested is characterized by per-cycle voting of microarchitectural and the flop-based architectural states, redundancy at the pipeline level, and a distributed voting scheme. Its fault-tolerant behavior is characterized for three different workloads from the automotive application domain. The study proposes statistical methods for both the single and dual fault injection campaigns and demonstrates the fault-tolerant capability of both processors in terms of fault latencies, the probability of fault manifestation, and the behavior of latent faults.

A Novel Fault Detection Scheme for Voltage Fed PWM Inverter

Abstract: This paper presents a new fault detection scheme for voltage fed inverter to improve the reliability of power electronic system, which is of paramount importance in the wide industrial applications. The proposed method is achieved by using voltage across lower switches in each phase under the switch fault condition. The reconfiguration method is achieved by the four-switch topology connecting a faulty leg to the middle point of DC-link using bidirectional switches. The proposed method has a simple algorithm and fast fault detection time. Therefore, normal operation of the system after faults is continuously achieved by reconfiguration of system topology. The superior performance of the proposed fault detection and tolerance method are proved by simulation.

A Test Generation Framework for Quantum Cellular Automata Circuits

Abstract: In this paper, we present a test generation framework for quantum cellular automata (QCA) circuits. QCA is a nanotechnology that has attracted recent significant attention and shows promise as a viable future technology. This work is motivated by the fact that the stuck-at fault test set of a circuit is not guaranteed to detect all defects that can occur in its QCA implementation. We show how to generate additional test vectors to supplement the stuck-at fault test set to guarantee that all simulated defects in the QCA gates get detected. Since nanotechnologies will be dominated by interconnects, we also target bridging faults on QCA interconnects. The efficacy of our framework is established through its application to QCA implementations of MCNC and ISCAS'85 benchmarks that use majority gates as primitives

A Fault tolerant mechanism for handling Permanent and Transient Failures in a Network on Chip

Abstract: Network on chips (NoC) have emerged as a feasible solution to handle growing number of communicating components on a single chip. The scalability of chips however increases the probability of errors, hence making reliability a major issue in scaling chips. We hereby propose a comprehensive fault tolerant mechanism for packet based NoCs to deal with packet losses or corruption due to transient faults as well as a dynamic routing mechanism to deal with permanent link and/or router failure on-chip

System and method for rapidly diagnosing bugs of system software

Abstract: A system and a method for rapidly diagnosing bugs of system software are apply for rapidly localizing a system program fault that causes a system error and then feeding back to a subscriber. First, according to the subscriber's requirement, a program of system fault analysis standard is preset and written into the system. Next, a plurality of fault insertion points is added into a program module of the system according to the subscriber's requirement for the precision of the fault analysis result. Then, fault management information is generated at the fault insertion points during the running process of the system program, and the management information is monitored for collecting relevant system fault data. After that, the collected system fault data is analyzed in real time through the program of system fault analysis standard, so as to obtain the minimum fault set for causing the system error.

System fault diagnostics using fault tree analysis

Abstract: Over the last 50 years, advances in technology have led to an increase in the complexity and sophistication of systems. More complex systems can be harder to maintain and the root cause of a fault more difficult to isolate. Downtime resultin from a system failure can be dangerous or expensive, depending on the type of system. In aircraft systems the ability to diagnose quickly the causes of a fault can have a significant impact on the time taken to rectify the problem and to return the aircraft to service. In chemical prcess plants the need to diagnose causes of a safety-critical failure in a system can be vital and a diagnosis may be required within minutes. Speed of fault isolation can save time, reduce costs, and increase company productivity and therefore profits. System fault diagnosis is the process of identifying the cause of a malfunction by observing its effect at various test points. Fault tree analysis (FTA) is a method that describes all possible causes of a specified system state in terms of the state of the components within the system. A system model is used to identify the states that the system should be in at any point in time. This paper presents a method for diagnosing faults in systems using FTA to explain the deviations from normal operation observed in sensor outputs. The causes of a system’s failure modes will be described in terms of the component states. This will be achieved with the use of coherent and non-coherent fault trees. A coherent fault tree is constructed from AND and OR logic and therefore considers only component-failed states. The non-coherent method expands this, allowing the use of NOT logic, which implies that the existence of component-failed states and component-working states are both taken into account. This paper illustrates the concepts of this method by applying the technique to a simplified water tank level control system.

Fault-tolerant typed assembly language

Abstract: A transient hardware fault occurs when an energetic particle strikes a transistor, causing it to change state. Although transient faults do not permanently damage the hardware, they may corrupt computations by altering stored values and signal transfers. In this paper, we propose a new scheme for provably safe and reliable computing in the presence of transient hardware faults. In our scheme, software computations are replicated to provide redundancy while special instructions compare the independently computed results to detect errors before writing critical data. In stark contrast to any previous efforts in this area, we have analyzed our fault tolerance scheme from a formal, theoretical perspective. To be specific, first, we provide an operational semantics for our assembly language, which includes a precise formal definition of our fault model. Second, we develop an assembly-level type system designed to detect reliability problems in compiled code. Third, we provide a formal specification for program fault tolerance under the given fault model and prove that all well-typed programs are indeed fault tolerant. In addition to the formal analysis, we evaluate our detection scheme and show that it only takes 34% longer to execute than the unreliable version.

Fault Dictionary Based Scan Chain Failure Diagnosis

Abstract: In this paper, we present a fault dictionary based scan chain failure diagnosis technique. We first describe a technique to create small dictionaries for scan chain faults by storing differential signatures. Based on the differential signatures stored in a fault dictionary, we can quickly identify single stuck-at fault or timing fault in a faulty chain. We further develop a novel technique to diagnose some multiple stuck-at faults in a single scan chain. Comparing with fault simulation based diagnosis technique, the proposed fault dictionary based diagnosis technique is up to 130 times faster with same level of diagnosis accuracy and resolution.

Design of a TS Based Fuzzy Nonlinear Unknown Input Observer with Fault Diagnosis Applications

Abstract: An approach for nonlinear unknown input observer (NUIO) design for nonlinear systems representable by a Takagi-Sugeno (TS) fuzzy system. The proposed NUIO design for TS fuzzy systems is carried out for two cases: 1) the premise variables do not depend on the unmeasured state variables; and 2) the premise variables depend on the unmeasured state variables. Sufficient conditions for the existence of NUIOs are derived, and an LMI based observer design strategy is proposed. Once the NUIOs are designed, fault detection and isolation problems for nonlinear systems described by TS fuzzy systems using the new NUIO is presented. To solve the actuator fault isolation problem, a system structure with two groups of inputs where one group is treated as unknown inputs is developed. A bank of NUIOs is then designed in order to investigate the following fault diagnosis problems: 1) How can the NUIOs be used for detecting faults? 2) Under what conditions is it possible to isolate single and/or multiple faults? 3) What is the maximum number of faults that can be isolated simultaneously? 4) How can multiple fault isolation be achieved? The article presents an NUIO based fault detection scheme for problem 1, gives sufficient conditions for problem 2, determines the maximum number of faults that can be isolated for problem 3, and proposes a fault diagnosis scheme using a bank of NUIOs to solve problem 4.

Transient fault detectors

Abstract: We present fault detectors for transient faults, (i.e., corruptions of the memory of the processors, but not of the code of the processors). We distinguish fault detectors for tasks (i.e., the problem to be solved) from failure detectors for implementations (i.e., the algorithm that solves the problem). The aim of our fault detectors is to detect a memory corruption as soon as possible. We study the amount of memory needed by the fault detectors for some specific tasks, and give bounds for each task. The amount of memory is related to the size and the number of views that a processor has to maintain to ensure a quick detection. This work may give the implementation designer hints concerning the techniques and resources that are required for implementing a task.

Behavioral Fault Modeling for Model-based Safety Analysis

Abstract: Recent work in the area of model-based safety analysis has demonstrated key advantages of this methodology over traditional approaches, for example, the capability of automatic generation of safety artifacts. Since safety analysis requires knowledge of the component faults and failure modes, one also needs to formalize and incorporate the system fault behavior into the nominal system model. Fault behaviors typically tend to be quite varied and complex, and incorporating them directly into the nominal system model can clutter it severely. This manual process is error-prone and also makes model evolution difficult. These issues can be resolved by separating the fault behavior from the nominal system model in the form of a "fault model", and providing a mechanism for automatically combining the two for analysis. Towards implementing this approach we identify key requirements for a flexible behavioral fault modeling notation. We formalize it as a domain-specific language based on Lustre, a textual synchronous dataflow language. The fault modeling extensions are designed to be amenable for automatic composition into the nominal system model.

Model-Based Fault Diagnosis in Electric Drive Inverters Using Artificial Neural Network

Abstract: This paper presents research in model based fault diagnostics for the power electronics inverter based induction motor drives. A normal model and various faulted models of the inverter-motor combination were developed, and voltages and current signals were generated from those models to train an artificial neural network for fault diagnosis. Instead of simple open-loop circuits, our research focuses on closed loop circuits. Our simulation experiments show that this model-based fault diagnostic approach is effective in detecting single switch open-circuit faults as well as post-short-circuit conditions occurring in power electronics inverter based electrical drives.

Cable fault detection

Abstract: A cable fault detection component (168) receives input data indicative of a fault in an electrical power system. The component (168) analyzes the input data to determine if the fault is indicative of a self-clearing cable fault and generates corresponding output data (276). In one implementation, the cable fault detection component (168) is implemented as a software module which operates on a computer (105) of a substation intelligence system (104).

Induction Motor-Drive Systems with Fault Tolerant Inverter-Motor Capabilities

Abstract: A low-cost fault tolerant drive topology for low- speed applications such as "self-healing/limp-home" needs for vehicles and propulsion systems, with capabilities for mitigating transistor open-circuit switch and short-circuit switch faults is presented in this paper. The present fault tolerant topology requires only minimum hardware modifications to the conventional off-the-shelf six-switch three-phase drive, with only the addition of electronic components such as triacs/SCRs and fast-acting fuses. In addition, the present approach offers the potential of mitigating not only transistor switch faults but also drive related faults such as rectifier diode short-circuit fault or dc link capacitor fault. In this new approach, some of the drawbacks associated with the known fault mitigation techniques such as the need for accessibility to a motor neutral, overrating the motor to withstand higher fundamental rms current magnitudes above its rated rms level, the need for larger size dc link capacitors, or higher dc bus voltage, are overcome here using the present approach. Given in this paper is a complete set of simulation results that demonstrate the soundness and effectiveness of the present topology.

An Adaptive Fault Location Technique Based on PMU for Transmission Line

Abstract: A new adaptive fault location technique based on Phasor Measurement Unit (PMU) for transmission line is presented in this paper. Voltage and current phasors of both terminals of the transmission line are obtained through PMU. The online parameter-calculation algorithm is adopted to obtain the practical operating parameters when fault occurs, solving the problems that parameters provided by electric power company is different from the practical parameters because of the running environment and the operation history. The suddenly changed voltage and current are utilized to obtain suddenly changed positive voltage and current components to solve the system's impedance at the fault time. The on-line calculated system's impedance and parameters of the line are employed in the fault location equation and the fault location accuracy is high. The proposed fault location method is applied in single transmission line, parallel transmission line as well as teed transmission line. Extensive EMTP simulations as well as practical system data testing results have shown that the proposed technique accurately locate the fault point adaptively, not influenced by factors such as operation mode, fault resistance at fault point, fault type, prefault load and fault distance.

Improved qualitative fault propagation analysis

Abstract: Fault propagation analysis is the cornerstone to assure safe operation, optimized maintenance, as well as for the management of abnormal situations in chemical and petrochemical plants. Due to plant complexity and dynamic changes in plant conditions, current approaches have major limitations in identifying all possible fault propagation scenarios. This is due to the lack of realistic equipment and fault models. In this paper, practical framework is proposed to synthesize and assess all possible fault propagation scenarios based on robust modeling methodology. Fault models are constructed where deviations are identified and associated with symptoms, faults, causes, and consequences. Fault models are tuned using real time process data, simulation data, and human experience. The proposed system is developed and applied on case study experimental plant.

Fault tree map generation

Abstract: A method for Fault Tree Map generation employs to transformation of Fault Trees of production installation, specific installation, technical system (Hardware and integrated Hardware/Software) to new Fault Tree diagram (Fault Tree Map), which permits drastically compact the Fault Tree depiction and facilitates performing of the Fault Tree qualitative analysis, including evaluation of combination of latent failures and evident failures, repeated events and critical events position influence, and failure propagation potentiality, besides facility of localization of each Fault Tree logical Gate and relevant failures in the fault tree printed report. Generation takes place using special symbols, which permit to reflect the Fault Tree logic, present all Fault Tree failures with graphically identification of the failure type, and show the failure repetition and also the failure critically (importance) to Fault Tree Top Event probability. The method presents exceptional advantages to analysis of large-scale, extended Fault Trees, allowing vastly decrease the time of analysis and elevate the analysis quality and Fault Tree perception, including for specialists, who are not the Fault Tree authors.

Early Analysis of Fault-based Attack Effects in Secure Circuits

Abstract: Security often relies on functions implemented in hardware. But, various types of attacks have been developed, in particular, fault-based attacks allowing a hacker to observe abnormal behaviors from which secret data can be inferred. Analyzing very early, during a circuit design, the potential impact of faults therefore becomes necessary to avoid security flaws. Dependability analysis environments have been developed to analyze the effect of "natural" faults, for example, those induced by particles. This paper discusses the similarities and differences between the two types; of application areas and proposes extensions of the classical fault models to cover security-related constraints. Experimental results on a coprocessor for RSA encryption demonstrate the need for such an extended fault model.

Achieving serendipitous N-detect mark-offs in Multi-Capture-Clock scan patterns

Abstract: Multi-capture-clock scan patterns for the traditional stuck-at-fault model have been used to reduce down pattern counts while still maintaining high test coverage. This paper studies how the same test patterns provide a decent N-detect fault coverage.